NO153997B - IMPLANT DIGITAL HEART STIMULATOR. - Google Patents

Abstract

IMPLANTABLE DIGITAL HEART STIMULATOR.

Description

The present invention relates to implantable heart stimulators or pacemakers of the type in which operating parameters can be varied from the outside and controlled remotely.

Pacemakers are often equipped with various devices for regulating selected operating parameters, so that e.g. the pacemaker can be set to react to and produce signals for a patient in accordance with the person concerned's individual needs. After the pacemaker has been implanted, however, it can be a major problem to make changes to any particular operating parameter of the pacemaker. However, such changes will often be necessary,

e.g. due to an improvement or deterioration of the patient's condition, which makes certain adjustments necessary, e.g. of the rate at which stimulation pulses are delivered to the patient's heart, the width and height of the pulses, the stimulation-free period produced by the pacemaker, the sensitivity to naturally produced heart signals, as well as the pacemaker's working mode, such as e.g. demand mode, working

fixed rate mode and the like.

Various proposals have previously been made with regard to

to produce changes in selected pacemaker parameters for an implanted cardiac pacemaker without performing major surgical interventions. It is e.g. proposed to arrange a magnetically sensitive switch which can be influenced by a magnet outside the patient's body, e.g. to change the pacemaker's work mode from demand mode to work at a fixed rate. Pacemakers with receiving organs for receiving inserted surgical needles have also been proposed, which can be inserted into the patient's body for setting e.g. a resistance value etc.

US Patent No. 3,805,796 describes an implantable cardiac pacemaker with certain adjustable working parameters. This circuit comprises a first and a second digital pulse counter. The first counter receives a first, predetermined set of input pulses, after which it generates a control signal to direct subsequent input pulses to the second counter. The second counter comprises a number of outputs to vary different switching means which are connected in parallel to each of the resistances of a number of series-connected resistors, in order in this way to control the input current of a transistor in a multivibrator circuit, so that the time constant of the circuit can be modified. Another output signal from the second counter controls a switching device which is arranged to bypass part of the drive current to the clock generator's output amplifier, thereby controlling its output current.

The circuit described above responds to an access code which simply consists of a pulse train of seven pulses. A requirement built into this circuit is that the seven pulses must occur in sequence for counting in the first counter. If, however, the wearer of the pacemaker e.g. is exposed to an electromagnetic field that affects the timing circuit, the circuit may mistakenly detect pulsations of the field as the access code, and then set the various parameters in the timing circuit accordingly, which can be a serious disadvantage.

In addition, the present previously known pacing circuit is only equipped with means for modifying the pulse rate (as well as possibly the pulse width) and the pacing device's output current, none of the many other, above-mentioned pacing parameters being taken into account.

Another disadvantage of the above-mentioned, previously known circuit is that when the access pulses have once been counted and the other counter switched on, the data pulses supplied to it will produce immediate changes on the various output lines. These changes will cause corresponding changes in the selection of the various timing resistors during the time data is received. If it e.g. if only a change in the output current is desired upon activation of the switching means affected by the counter's last output pulse, each individual combination of time-determining resistor connections will actually be performed before the final activation of the bypass switch that was originally desired.

In light of what has been stated above, it is therefore an object of the present invention to produce a cardiac pacemaker which includes external equipment at a distance from the pacemaker for varied and preselected setting of the pacemaker's working parameters.

It is another object of the invention to provide a digital heart pacemaker which, after implantation in the user's body, can be set from a place outside the body for variation of one or more operating parameters that are selected in advance, e.g. stimulation pulse width and height, demand mode or working mode at a fixed rate for the stimulation pulses, the duration of the stimulation-free period, as well as the sensitivity to cardiac signals.

It is a further object of the invention to provide a digital cardiac pacemaker which includes storage equipment which can record and store signals which determine the pacemaker's operating parameters, before these parameters are set.

It is still a further object of the invention to produce a digital stimulator or pacemaker and control means for controlling the setting of the pacemaker's operating parameters, these means comprising a special recognition circuit for an access code, thereby ensuring that signals which can determine the setting of the operating parameters do not is inadvertently recorded.

It is a further object of the invention to provide a circuit for use in a cardiac pacemaker for the purpose of regulating the pacemaker's sensitivity to heart rate signals.

These and other purposes, features and advantages will be better understood by professionals in the field from the following detailed description with reference to the attached drawings and the

subsequent patent claims.

The present invention thus relates to an implantable digital heart stimulator designed for supplying stimulating pulses to a heart contact electrode in accordance with selectable operating parameters determined by remote signals supplied from the outside, said remote signals comprising a first signal section, which indicates a predetermined access code, followed by a data section which determines the said operating parameters of the stimulator, and the heart stimulator comprises: a pulse generator for producing said stimulating pulses, and which is in connection with said cardiac contact electrode,

equipment to receive said remote signals and produce corresponding digital signals,

a feedback circuit for said access code and arranged to emit a control signal on receipt of a predetermined such code,

storage equipment for receiving and storing said parameter-determining data sections,

a port device for receiving the parameter-determining data section, but arranged to only pass through this data section to the storage equipment upon receipt of said

control signals from the recognition circuit, as well as control means for controlling the stimulator's operating parameters

in accordance with the stored data section in the storage device.

On this background of known technology, the heart stimulator according to the invention has as a distinctive feature that said recognition circuit is arranged to only recognize a distinctive predetermined access code with both high and low logic states, and exclusively to emit said control signal to the gate device upon such recognition to open this for data transfer to the storage device.

The cardiac stimulator preferably comprises transmission means which connect said receiving equipment for the remote signals and the storage equipment and are arranged to allow the introduction of said parameter-determining data section into the storage equipment only after the relevant data section has been received in its entirety by the receiving equipment.

According to the invention, the stimulator is preferably designed so that the data section of the remote signals comprises a train of electromagnetic pulses, and said storage equipment comprises means for counting these pulses in order to produce output signals indicating the transmitted information of the pulses, while a memory device is arranged for storing said output signals from the counter means for controlling the stimulator's operating parameters.

The invention will be described in more detail with reference to the attached drawings, on which: Fig. 1 is a block diagram of a heart pacemaker or stimulator according to the invention and with various controllable parameters. Fig. 2 is a block diagram showing the main circuit for parameter control, and which includes the recognition circuit for the access or opening code, the instruction memory and the circuit for writing the instruction code into the memory, in accordance with a first embodiment of the invention. Figs. 3A, 3B and 3C are detailed electrical wiring diagrams for the main parameter control circuit of Figs. 2. Fig. 4 is a detailed electrical connection core for the pulse generator and the amplitude regulation circuits as well as the R-wave amplifier and the circuits for sensitivity regulation in the pacemaker in fig. 1. Figs. 5A and 5B are a detailed electrical circuit diagram of the counter control circuit, the stimulation-free period control circuit, the asynchronous generator reset circuit, the operating mode control circuit, the asynchronous interval generator circuit, the asynchronous pulse rate control circuit, and the pulse width control circuit in the cardiac pacemaker of Fig. . 1, and Fig. 6A, 6B, 60 and 6D show a detailed electrical connection diagram of an external control unit used for transferring the opening code and parameter instruction to the main circuit for parameter control in Fig. 3A, 3B and 3C.

In the different figures in the drawings, the same reference numbers are used to indicate corresponding parts. Connections between the various circuits in the drawings are further indicated by corresponding letters (A, B, C etc).

A preferred embodiment of the light timer 10 according to the invention is shown in the form of a block diagram in fig. 1. The various electrical circuits in the tachometer in fig. 1 will be further discussed and described below with special reference to fig. 2-5-

The cardiac pacemaker 10 which is shown in its entirety in fig. 1,

receives naturally produced heart signals and other signals from the clamps 11, and emits stimulation signals to the same clamps,

which is arranged for connection with cardiac electrodes in a manner well known in this field.

The pacemaker 10 is operated in accordance with a digital clock 12 which emits clock pulses with a frequency of e.g. 6.82 KHz. The pulses from the clock 12 are divided in a frequency divider 13 for transmission over a line 1^- to an asynchronous interval generator 15 with a number of outputs T1-T8 in connection with an asynchronous clock control circuit 16. The outputs T1-T8 each represent an asynchronous interval within the relevant range , and the asynchronous clock control circuit 16 selects one of the outputs T1-T8 from the asynchronous interval generator 15 under control from a main circuit 150 for parameter control.

The selected output from the asynchronous interval generator 15 is connected to a control circuit 17 for pulse width control and which produces an output pulse of selected width under control from the main control circuit 150. This work function is driven by clock pulses which are fed directly to the width circuit via the line ih

17 as well as to a frequency divider 19, which produces further

clock pulses at a rate which is a submultiple of the frequency of the clock 12, with the purpose of supplying further signals to the control circuit 17 for the pulse width, so that different widths of the output pulse can be selected.

The output pulses from circuit 17 are used to trigger a pulse generator 21 to produce an output pulse on line 22 for delivery to heart clamps 11. The amplitude of the pulse produced by pulse generators 21 is controlled by an amplitude control circuit 2h, which in turn is also controlled by the executive board 1 50.

The output signal from the width circuit 17 is also supplied via a NOG gate 30 to a reset terminal for the asynchronous interval generator 15. Upon achieving a predetermined counting step for the asynchronous generator 15 and producing a corresponding output pulse from the width circuit 17, the asynchronous interval generator 15 be reset to begin the countdown of a subsequent asynchronous interval.

The part of the pacemaker that has been described so far serves as a so-called pacemaker in a fixed pulse rate, and generates pulses asynchronously at a rate controlled by the selected output from the asynchronous interval generator 15- To make the pacemaker able to work as a demand generator is an R-wave amplifier 32 is arranged. The heart clamps 11 are connected via a line 32 to an input to the R-wave amplifier 32 with the purpose of transferring naturally occurring heart pulses to the amplifier 32. Other signals, such as e.g. stimulation pulses produced by the pulse generator 21 on line 22, as well as a disturbing electromagnetic noise which is picked up by the heart electrodes or the connected circuits, can also occur on line 33? but is filtered out or rejected, or may possibly trigger an interference mode or working mode at a fixed rate, as will be apparent from the following description. The sensitivity of the R-wave amplifier 32 is controlled by a control circuit 35> which in turn is under overall control of the main control circuit 150.

The R-wave amplifier 32 produces an output signal at

detection of a naturally occurring R-wave, a stimulation pulse or a disturbance signal, for transfer to a control counter 38. The control counter 38 also receives clock pulses from 12 o'clock via a NOG port ^-0 and produces output signals at times , T ? and I-, after reset. The output signal produced at time T. is transferred to a reset circuit <*>+1 for the asynchronous generator, this circuit ^-1 producing an output signal which is emitted via a NOG gate 30 for resetting the counting process in the

asynchronous interval generator 15. Thus, if during operation an R-wave, a stimulation pulse or a disturbance signal is received by the R-wave amplifier 32 for the time at which a signal appears on a selected output from the asynchronous interval generator 15, this generator 15 will be reset for on again to begin its counting process, in a way that will be known in this field as operation in demand mode.

In addition, one of the outputs T~ or from the control counter is selected

by a control circuit ^+3 for the stimulation-free period, and which in turn is controlled from the main control circuit 1 50. The selected output signal is transferred to an inverted NOG port *+5, before being applied to the NOG port <>>+0 which controls the transmission of clock pulses along the line 11+ as well as to the reset circuit h^ for the asynchronous generator in order to produce in this circuit a condition which allows the passage of a subsequent reset pulse to the asynchronous generator from the control counter 38. The circuit for controlling the stimulation-free period thus works so that it produces a "standby" condition in the reset circuit ^1 of the asynchronous generator after the control counter 38 has reached a predetermined count step determined by the control circuit <>>+3 for stimulation-free periods. After producing the aforementioned standby state, such a logical state is created on the input side of the N0G-

the circuit ^0 that transmission of clock pulses along the line ^ l+ is prevented, which causes an end to the counting process in the control counter 38. After this, any output signal from the R-wave amplifier 32 will produce a pulse which resets the control counter 38 and enables it to begin a new counting process. When this counting process has reached the time , the reset circuit !+1 which has previously been activated by the control circuit V3, will produce a reset pulse for resetting the count in the asynchronous interval generator. Before said "standby state" is established, however, the pacemaker is in a so-called "control state" during which reception of a signal from the R-wave amplifier 32 does not generate a reset pulse for the asynchronous interval generator, but instead only resets the control counter 38 to begin the countdown of the previous fixed stimulation-free period from the beginning.

In addition, a mode control circuit 50 is arranged to be controlled from the main control circuits 150. The mode control circuit 50, however, when put into operation, provides for switching off the working function of the reset circuit ^1 of the asynchronous generator, thereby causing the clock generator 10 to to work in a work mode with a fixed rate. The mode control 50 can also be operated by means of a temporary external control, such as an electromagnet or the like, to make the circuit work at a fixed rate for test purposes, as will be well known in this field.

The main control circuit 150, which will be described in more detail below, is programmed by means of an external control signal which is supplied to a receiver element 215 such as, for example a magnetically controlled reed switch or similar, as indicated below.

As previously mentioned, the pacemaker 10 according to the invention includes equipment for varying the pacemaker's working parameters, such as e.g. the width and amplitude of the stimulation pulse, the stimulation-free period, the sensitivity to cardiac signals as well as the pacemaker's working mode (which means working in a fixed rate or demand mode) and the generation rate for the asynchronous pulses. These working parameters can in turn be varied after the pacemaker has been implanted into a patient's body. To facilitate the above-mentioned parameter control, a main control circuit 150 is used. This circuit 150 is shown in the form of

a block diagram in fig. 2, and in more detail in fig. 3A-3C.

As will be understood, the main control circuit 150 is for the clock generator

parameters arranged to be affected by input signals supplied from an external instruction device, as described below. This instruction device produces an initial opening train of electromagnetic pulses followed by a train of pulses which determine the operating parameters of the pacemaker. The control circuit 150 must first recognize the added opening row for the control row will be accepted and entered into the control circuit's memory. Specifically and as indicated in fig. 2, the externally supplied input signal will be received by a digital monostable pulse generator 151, which produces an output pulse of regulated amplitude and width for each externally supplied input pulse, in order to overcome problems associated with backlash and oscillations in the detector switch of the input signal (described below ). The output signal from the digital monostable pulse generator 151 is applied to a latch and start circuit 152 as well as a NOG gate 156. The output signal from the NOG gate 156 is fed to the input of a shift register 165, whose various outputs are connected to a monster recognition circuit 172.

At the same time, clock pulses are supplied from 12 o'clock to the digital monostable generator 151? a reset circuit' 155 and a counter 162. Three output signals from teHerenl62, which occur at different times, are supplied to the shift register 165, a sample-seeking stop and lock circuit 166, and a stop circuit 167. In addition, the output signal from the NOG gate 156 is routed to an input for the shift register 165, as well as to another NOG port 170.

An output from the monster-recognizing circuit 172, as well as an output from the monster-seeking circuit 166, are fed as input signals to a NOG gate 17^- The output signal from this gate is transferred to the input of an activating latch circuit 176, and the output of this circuit 176 is fed to another input for the AND gate 170 and an AND gate 180. The output signal from the stop circuit 167 is fed to another input for the AND gate 180 and to a reset terminal for the start and latch circuit 152. The output signal from the AND gate 170 is fed to the input of a data counter 182, and the output signals from the data counter 182 are supplied to a data collecting memory circuit 18<*>+. The output signal from the AND gate 180 is applied to a "storage" terminal of the data acquisition memory circuit 18*+.

Briefly, application of an externally supplied input signal to the digital monostable pulse generator 151 will cause activation of the start and latch circuit 152. This circuit 152 then activates the reset circuit 155 which initiates

the shift register 165, the sampling latch circuit 166, the activating latch circuit 176, the stop circuit 167 and the data counter 182. In addition, the activation of the initiation circuit 152 causes the counter 162 to begin its counting process. Counter 162, which will be described in more detail below, produces output signals that are submultiples of the clock frequency.

The generated data from the digital monostable pulse generator is then transferred via the NOG circuit 156 (set to allow passage of data due to the output signal from the enable circuit 152) to the monster-recognizing shift register 165-

The first seven data bits are clocked into the shift register 165 at a rate which is a submultiple of the clock frequency of the clock 160 (1/32 of this frequency in the embodiment shown). Data from the shift register 165 is continuously applied to the combined monster recognition logic circuit 172, which produces an output signal if, and only if, the predetermined recognition code appears in the shift register 165. At the same time, the monster search stop and lock circuit 166 is activated by another output signal from the counter 162 at a other submultiple of the frequency from the clock 160 (eg 1/256 of the clock frequency, namely the time required to clock the first seven data bits into the shift register 165). The output signal from the monster-seeking stop and lock circuit 166 activates the activation circuit 176, when applied together with the output signal from the monster-recognizing combination circuit 172 on the NOG gate 17l+. The data that appears on the output page

of the NOG port 156? is thus transferred through the NOG port 170

to the data counter 182 and from there to the data storage circuit 18^.

At a time when all data has been entered into the data storage circuit '\8l+, the stop and latch circuit 167 is activated to produce a signal which is applied to a "storage" terminal of the storage circuit 18*+ through the AND gate 180. At the same time, the output signal from the circuit 167 to the initiation and locking circuit 152 for resetting this to its initial state in order to exclude further data transfer into the main control circuit 150.

At this time, data from the external instruction device is stored in the storage circuit 1 8H- with the purpose of changing the operating parameters of the pacemaker.

The pulse receiving circuit in fig. 2 is shown in more detail in fig. 3A-3C Specifically, clock 12 (FIG. 3A) is shown to include a bistable multivibrator 200 which produces an oscillation on line 201 for supplying clock pulses to the rest of the clock circuit. There is also arranged a frequency derating circuit 13? which includes a J-K master/slave multivibrator 203? to which a frequency-divided output signal from the bistable multivibrator 200 is supplied to the multivibrator's clock input, as well as a D-type multivibrator 20^+ and to which the Q output from the multivibrator 203 is connected via a clock input. The Q output of the multivibrator 20^ is connected to the D input, whereby the output of the multivibrator alternates between high and low signal states with a series of clock pulses to divide the clock frequency by two. The output signal from the D-multivibrator 20h is fed out of the clock circuit via line 208 (this connection continues from point BB to the width regulating control

circuit 17, fig. 5B). Since the Q output from the bistable multivibrator 200 is half of the generated oscillation frequency, the output signal from the D multivibrator 20h will be the clock frequency divided by four. The set and reset terminals of the D-multivibrator 2.01+ and the J-K multivibrator 203 are connected to a low level 190 to ensure continuous operation of the

respective multivibrators.

The Vss clamp, the positive trigger, the external reset and the 200 clock trigger terminals are fast to low potential,

while the bistable, negative release and V,-, are associated with high potential. The integrated circuit 200 will therefore work as a bistable multivibrator whose output signal appears on line 201, while a submultiple with half the frequency appears on line 210 for supply to the multivibrator 203? as stated above. The output signal over line 201 thus constitutes the primary clock frequency, while the output signal on line 1<*>+

(point AA) is the first divided by the primary clock frequency, created by the divider circuit 13? and the output on line 208 (point BB) is the second divided clock frequency, created by the dividing circuit 19. The frequency of the clock 12 is determined by the values of the capacitance 211 and the resistance 212, which are connected respectively. between the capacitance terminal and the resistor terminal and the common R/C terminal of the bistable multivibrator 200. The clock frequency can be set by changing the value of the resistor 212. In the shown embodiment, this resistor is around 2MA, while the capacitance has a value of around 100 pf, provided that the clock frequency can be set to a value around 6.82 KHz. A zener diode 213 is connected between the capacitance terminal of the multi-vihator 200 and ground, to cause the oscillator frequency to decrease with decreasing battery voltage.

They transferred data from the external instruction device (which will

be described below) is received by a magnetically controlled reed switch 215 and transferred to the digital monostable generator 151 (Fig. 3A). The pulse generator 151 ensures that the pulse received from the reed switch 215 has the appropriate shape and width to be processed by the rest of the circuit, and comprises two D-type multivibrators 220 and 221, a ripple-carrying binary counter 222 and an AND port 223. The added data is transferred to the clock input of the D multivibrator 220, whose D input is connected to a high potential. The Q output of the multivibrator 220 is connected to the D input of the D multivibrator 221, while

The Q output of D multivibrator 221 through AND gate 223 is connected to the reset terminals of multivibrators 220 and 221. The primary clock pulses appearing on line 201 are additionally applied to AND gate 223 to synchronize the resets of D multivibrators 220 and 221. The Q output of D-multivibrator 220 is connected to a reset terminal of counter 222. The clock terminal of counter 222 is connected to line 201 to receive primary clock pulses therefrom. The output signal from the counter 222 is taken e.g. out from the output Q^ and the clock terminal for the D-multivibrator 221 is applied.

Thus, when a data pulse is received by switch 215, it will serve to clock the high state of the D terminal to the Q output and from there to the D input of multivibrator 221. When the Q output is brought high, the Q output will shift to a low level, thereby removing the high reset state from counter 222 and allowing it to begin counting clock pulses applied to line 201. When the output line Qg goes high

(after 2^ times the clock frequency divided by two, sec.), the high level of the D input of the multivibrator 221 will be clocked through to the Q output of this multivibrator to enable an input of the AND gate 223 to be applied. next clock pulse on line 201, the high level will be applied to the reset terminals of multivibrators 220 and 221 to return them to their initial state. The pulses that appear on the output line 230 will thus have a constant width, which is determined by the time it takes for the output Qg for the counter 222 to assume a high level, counted from the time the relevant pulse is received from the switch 215 - The amplitude of the output pulse on the line 230 will naturally be constant and equal to the high level.

The output signal from the digital monostable generator is applied to the start and lock circuit 152 (Fig. 3A). This circuit 152 comprises a J-K master/slave multivibrator 235? whose clock input is supplied with the output signal from the digital monostable generator 151. The K input of the multivibrator 235 is connected low, and the J input is connected to the Q output. The Q output will therefore be continuously at a high level after receiving the first clock pulse and until the multivibrator 235 is reset. The reset terminal is connected to the stop and latch circuit 167 (fig-3B), which will be described below. The Q output from the multivibrator 235 is applied to one input terminal for a NOG gate 156, and data produced on the output line 230 from the pulse generator 151 is applied to the other terminal. The output signal from the NOG gate 156 is applied to the shift register 165 (fig. 3B) as well as the one input terminal for the NOG gate 170 (fig. 30) for transfer to the data counter 182

(Fig. 3C) as described below.

The Q output signal from the multivibrator 235 is applied to the reset circuit 155 (fig. 3B), which comprises two D-type multivibrators 2^-0 and 2^1. The D input of the multivibrator 2^0 is connected high, while the output across line 239 of the enable and latch circuit is connected to the clock input. Thus, when the state of line 239 changes from low to high level, the high level of the D input will be transferred to the Q output of the multivibrator 2^0, to act on the D input of the multivibrator 2>+1 . The clock terminal of the multivibrator 2hl is connected to receive primary clock pulses appearing on line 201. Upon activation of the triggering circuit 235, the high level of the D input of the multivibrator 2^0 will thus be transferred through it, upon the simultaneous occurrence of a clock pulse, to The Q output of the multivibrator 2^-1, in order thereby to produce a high reset level on the output line 2^3, which is connected to the reset terminals of the multivibrator 2^-0, the shift register 165, the enable circuit 176 (Fig. 3C), the sample seeking circuit 166 (fig. 30) and the data counter 182 (fig. 30), as will be described below. The reset pulse is, however, of self-limiting duration, as the pulse ends when s-in occurs on the reset terminal for the multivibrator 2^0 after the occurrence of a subsequent primary clock pulse on line 201.

The Q output signal from the multivibrator 235 (Fig. 3A) is applied to the reset terminal for the counter circuits in the counter 162

(Fig. 3B). The counter 162 comprises a ripple-carrying binary counter 258, a ripple-carrying binary counter 259 and an AND gate 260. Both the counter 258 and the counter 259 are reset by the Q output signal from the multivibrator 235. Thus, when the start and latch circuit 235 is activated, the reset condition that normally occurs on the reset terminals 258 and 259 is removed, so that the counting process in the counter 162 is initiated.

The primary clock pulses on line 201 are connected to the clock input of the counter 259? and the output signals produced on the lines Q^, Q^ and Q12 are transmitted respectively. to the shift register 165 (fig. 3B), the sampling circuit 166 (fig. 30) and the clock clamp for the counter 258. The output signals from the counter 259 thus appear at submultiples of the clock frequency that appears on line 201, and since the clock frequency is around 6.82 KHz with a period of around 0.1^66 millisec., can e.g. the pulses on the line Q^ have a period of about ^.69 millisec. , the output signals on line Q^ have a period of approximately 75.07 milliseconds, and the output signals on line Q^ have a period of approximately 600.58 milliseconds.

The output line from the output terminal Q1 of the counter 258 is

connected to one input terminal of AND gate 260, while the output of line Q^ is connected to the gate's other input.

As the counter 258 receives its clock pulses from the Q^ 2 ~ output from the counter 259, the output signals Q^ and from the counter 258

on the output side of the AND gate 260 change its state from low to high level with a period of duration of about 5-^05.28 milliseconds. It will be obvious that the data received by the switch 215 will be received in the frequency period that appears on the output terminal Q^ of the counter 259, which means h.69 milliseconds. The state change on the output side of the AND gate 260 will therefore be 1,152 data pulses after the counters have been given permission to begin their counting process, for activation of the stop and latch circuit 167 (fig. 3B), as described below.

In operation, the circuit will first seek out an opening code monster

pulses received from the input switch 215. For this purpose, a monster-recognizing circuit 270 (fig. 3B) is arranged, which comprises a shift register 165 and a monster-recognizing NOG gate 172. The output Qr of the counter 259 is connected to the clock input of the shift register 165. The data produced by the monostable pulse generator 151 (Fig. 3A) is transferred through the NOG port 156 to the data input for the shift register 165 - The available data is clocked into the shift register 165 with the frequency of the pulses produced on terminal Q, - for the counter 259- It will thus be realized that if the pulses transmitted to the circuit are not of the frequency produced on the line Q,- from the counter 259, data will not be able to be clocked correctly into the shift register 165, and will not be recognized by it monster recognition circuit 172 which will be described below. This requirement for the clocking process thus imposes a frequency limitation on the available input data in addition to other requirements (especially the monster of high and low levels), whereby the statistical improbability of accidental activation of the parameter-determining coding circuits is greatly increased.

As data is shifted into shift register 165~, it will appear on output terminals Q1, Q2, , Q^, , Q6 and Q^. The output terminals from the slate register 165 are connected to the input terminals for the NOG gate 172. If desired, certain output lines from the shift register 165 can be inverted, e.g. by means of inverters 272 and 273, thereby enabling an unmistakable, unmistakable encoding of the required recognition sample to the circuit.

The NOG gate 172 produces a low output signal only when all possible input signals to the gate are available. Only when the output signals from the shift register 165 correspond to the previously determined opening code will they thus produce a state change on the output terminal for the NOG gate 172. The output signal from this gate 172 is inverted by means of an inverter 27^ to then be applied to an input for the NOG gate 17^.

After a sufficient period of time for the opening monster to be recognized, the circuit will be relieved from continuing its search for opening monsters by the stop circuit 166 (Fig. 3C). The monster search stop circuit 166 comprises a J-K master/slave multivibrator 276 which receives its clock input signal from the output Qq. for the counter 259. The K input of the multivibrator 276 is connected to low potential, while the J input is connected to the ^ output. Thus, upon receipt of a clock pulse on the clock terminal, the Q output will change from a normal low to a high level, where it will remain until the multivibrator 276 is reset. The Q output is connected to the second input terminal of the NOG gate 17^ to prevent further signal transmission from the monster recognition circuit 270 through this gate. Then the clock input signal to the multivibrator 276

is derived from the output terminal Q^ of the multivibrator 259? the monster sweep stop circuit will be activated approximately 37.55 millisec. after the initiation circuit 152 has been activated.. This corresponds to the period it takes to transfer eight data bits

at the rate determined by the output Q^ of the counter 259- Thus, if the opening monster is not recognized within the first 8 pulses after the monster search has begun, the circuit will abort its search and will not accept further data for the time required for a complete program cycle , has expired.

Immediately prior to the activation of the monster search stop circuit 166, and if the opening monster is recognized, the output signal from the monster recognition circuit 270 through the NOG gate 1 ?k will be applied to the enable circuit 176 (Fig. 30), which comprises a J-K master/slave multivibrator 280. The multivibrator 280 has its K input connected to low potential and its Q output connected to the J input. The signal from the monster recognition circuit is applied to the clock input. As soon as the activating pulse monster is recognised, the activation circuit thus produces a high-level output signal at its Q output terminal, which will persist until the circuit is reset. The Q output terminal of the multivibrator 280 is connected to one input of the AND gate 170 for controlling the data transfer through gate 156. The Q output of the multivibrator 280 is additionally connected to an input of the AND gate 180 for comparison with the output signal of the latch circuit 167 (Fig. 3^0 , which will be described below. As soon as the activation circuit 176 changes state after recognition of the opening pattern, data from the multivibrator 230 will be transferred to the data counter circuit 182 (Fig. 30.

The data counter 182 comprises a ripple-carrying counter 291. Data from the monostable pulse generator 151 (Fig. 3A) is applied to the clock input of the counter 291. As data is fed into the counter 291, the output states Q-]"Q-jq will indicate the number of received pulses It should be noted that the output signals produced at the terminals Q^-Q^q are the binary number corresponding to the number of pulses received over the clock input, the most significant digit being located on the line Q-jq.

Data on the lines Q-j-Qg from the counter 291 is connected directly to the data storage circuit 18^- (Fig. 3C). The storage circuit 18<*>+ comprises a latch circuit 295 and two D-type multivibrators 290 and 292 for storing the added signals. The various outputs Q-j-Qg of the counter 291 are connected to the various data inputs of the latch circuit 2955 whose storage terminals are connected to the output of the AND gate 180, which, as described above, receives its input signals from the outputs of the stop circuit 167 (Fig. 3B) and the activation circuit 176 (Fig. 3C). The outputs Qq and Q1Q from the counter 291 are connected to the D input for the respective the multivibrators 290 and 292. The Q outputs of these multivibrators 290 and 292 form two additional control data states at points EE and FF.

The stop circuit 167 comprises two D-type multivibrators 300 and 301. The primary clock pulses on line 201 are applied to the clock input of the multivibrator 301, and as indicated above, the outputs from the outputs Q1 and Q^ of the counter 258 are applied through the AND gate 260 to the clock input of the second multivibrator 300. The D input of the multivibrator 300 is connected to high potential, while the Q output is connected to the D input of the multivibrator 301. The Q output of the riiultivibrator 301 is connected to one of the input terminals of the AND gate 180 as well as to the reset terminal of the multivibrator 300.

Thus, when all data has been received by the circuit within it

period determined by state changes on the outputs Q and Qi of the counter 258 is received, the stop circuit 167 and the enable circuit 176 (Fig. 3C) will produce a signal to the "storage" terminals of the latch circuit 295 (Fig.'30) for thereby effecting the introduction of the data that appears on the data inputs for this circuit. Relevant data will then be stored in the locking circuit until another signal set, which includes a correct opening code, is supplied to the circuit. The output signals that appear on the latch circuit 295? is then available for transfer to the various modification circuits for changing the cardiac pacemaker's working parameters.

The electrical connection diagram for the pulse generator 21 (see fig. 1) is shown in detail in fig. h. The pulse generator 21 serves as a voltage amplifying circuit, and comprises two n-p-n transistors 310 and 311- Collector and emitter of the transistor 311 connect one side of a capacitor 313 in series with the output line 22 through a capacitor 31 1+- A resistor 316 connects the base of the transistor 311 to a negative terminal 190, and a resistor 322 connects the collector of the transistor 311 to a ground terminal 191? so that the collector/base layer in transistor 311 is biased opposite to the conduction direction.

The side of the capacitor 313 which is connected to the emitter of the transistor 311 is also connected to a negative potential at the terminal 190 across a resistor 318. The opposite side of the capacitor 313 is connected to the collector of the transistor 310 and a ground potential 191 across a resistor 320. The emitter of the transistor 310 is connected directly to the negative terminal 190. Thus, when the transistors 310 and 311 are in the normal, non-conducting state, the capacitance 313 °PP? as suggested, of the voltage between the negative terminal 190 and the ground terminal 191? through resistors 318 and 320.

When the transistor 310 is biased to the conducting state, as will be described below, will the negative potential on the emitter of the transistor be connected in series with the previously charged capacitance 313? thereby increasing the voltage that exists between the emitter of the transistor 311 ° and ground.

This added negative potential also produces biasing of the base/emitter layer of the transistor 311 in the conduction direction, so that this transistor is caused to conduct and emit the amplified voltage to the output line 22, as described above.

A zener diode 32^ is connected between the output line 22 and ground

191 for protection against unwanted high switching voltages that may occur.

Generation of a stimulation pulse, as indicated above, is controlled by the supply of base current to the transistor 310. This base current is created in a resistance path in series between the base of the transistor 310 and the output of the NOG gate 327. The input to the gate 327 is derived from the output side of the wide- control circuit 17 (see Fig. 1), which will be described in detail below.

The resistance in said resistance path and consequently the base current for the transistor 310 is controlled by an amplitude control circuit 2<l>+. This circuit 2h comprises three resistors 326, 329 and 330. The resistors 329 and 330 are connected in parallel with each other as well as with the resistor 326 across each of their bilateral switches 332 and 333 - The switches 332 and 333 receive digital drive signals over their respective lines II and JJ, as these signals are derived from the output side of the data storage circuit 295 in the main control circuit 150 (see Fig. 3C). Thus, during operation, a logic state 00 on the respective terminals II and JJ results in the total value of the resistor 326 being switched on to control the base current of the transistor 310. The presence of a logic state 01 on the terminals II and JJ will cause the switch 332 to close , leading to a resistance value corresponding to the parallel combination of resistors 329 and 326 in the base circuit. A present logic value of 10 on terminals II and JJ will cause switch 333 to be closed to produce the parallel combination of resistors 330 and 326 in the base circuit. Finally, the logic value 11 on terminals II and JJ will cause both switches 332 and 333 to be closed to produce a parallel combination of all three resistors 329, 330 and 326 in the base circuit. The collector/emitter current in transistor 310 is thus controlled by the logic value present at terminals II and JJ.

The degree to which the transistor 310 is biased to the conducting state under control of the logic states on the terminals II and JJ determines the amplitude of the output pulse that is transmitted over the line 22. This means that the voltage drop that exists between collector and emitter determines the voltage that will be present in series with the voltage previously impressed capacity 313*

The output line 22 serves, in addition to transmitting stimulation pulses from the pulse generator 21 as described above, to transmit naturally produced heart pulses to the detector part of the pacemaker 10 via the line 33- A resistor 3^0 is connected in series with a capacity 3<1>+ 1 to a non-inverting input for an operational amplifier 3<1>+3. The resistor 3<*>+0 and the capacitor 341 serve, in addition to signal transmission to the input, as a low-frequency filter, the capacitor 3^0 having a high impedance for the low-frequency components of the detected signal on line 22. A diode 31+1+ is disconnected a point between the resistance 3^-0 and the capacitance 3^1 'to a ground clamp 191, in order to lock the amplitude of the stimulation pulse to an acceptable voltage to prevent overloading of the amplifier 3^3-

A resistor 3*+° is connected in series with a capacitance 3*+7 between a ground terminal 191 and an inverting input of the operational amplifier 3^3. A feedback resistor 3<1>+9 is connected between the output of the amplifier 3l+3 °§ and its inverting input. The resistor 3^° °g the capacitance 3^7 also serves as a low-frequency filter for the signal produced on the output side of the operational amplifier 31+3- A compensation capacitance 350

is arranged for determining the 3db weakening point on the high frequency side. Finally, the non-inverting input to

the amplifier 3^3 connected with a voltage divider, which comprises two resistors 352 and 353? connected in series between a negative terminal 190 and a ground terminal 191. A balance offset resistor 355 is connected between the ground terminal 191 and a balance offset terminal of the amplifier 3^3- The output of the amplifier 3<l>+3 is connected to the gate electrode of a FET transistor 356 for controlling the current through this transistor. Upon receiving a naturally produced heart pulse (or another signal with similar frequency characteristics), the amplifier 3^3 thus produces a voltage which activates a FET 356. The degree of activation of the FET 356 naturally depends on the output voltage of the amplifier 3^3, which in turn is determined by the amplitude of the signal sensed on line 22.

The timer's sensitivity to the signal produced by the R-wave amplifier 32 can be set by the sensitivity circuit 35 (see Fig. 1). This sensitivity circuit 35 comprises a NOG gate 358,

whose inputs are connected to the output terminals GG of the data storage circuit 295 (see Fig. 30). The exit from the NOG port 358

is connected to a control terminal for a bilateral switch 359

which is connected in parallel with a Schottky diode 361.

Another terminal HH for the circuit 295 (Fig. 30) is connected with

another bilateral switch 362, which is connected in parallel with a silicon diode 36^. In addition, the anode of diode 361 is connected to a ground terminal 191, and the cathode of diode 36<*>+ is connected to the source electrode of FET 356. A resistor 365 is connected between the drain electrode of FET 356 and a negative terminal 190. Thus, a current path from the earth terminal 191 through the diodes 361 and 36h, the ki2d,e electrode and the drain electrode for FET 356 and the resistor 365 to the negative terminal 190. Then the resistance in the conduction direction for the respective The Schottky diode 361 and the silicon diode 36<*>+ are of the order of magnitude respectively. 0.2 and 0.7 ohms, the current through the resistor 365, when the FET 356 is in the conducting state, can be controlled by activating one or the other, none or both of the bilateral switches 359 and 362. If, for example, . the logic value 00 is applied to the respective terminals GG and HH, the bilateral switch 359 will be turned on while the bilateral

switch 362 is turned off, to form a current path from ground terminal 191 through switch 359 and diode 36^ to the source electrode of FET 356. A logic value 01 on terminals GG and HH will ensure that both switches 359 and 362 are turned on, so that both diodes 361 and 36^ are bypassed in the current path from the ground terminal 191 to the source electrode. A logical value 10 on the respective terminals GG and HH will turn off both the switch 359 °g the switch 362, so that a current path is formed through both diodes 361 and 36^ from the ground terminal 191 to the source electrode. Finally, a logic value of 11 on input terminals GG and HH will turn switch 359 off while switch 362 is turned on, so that a current path is formed from ground terminal 191 through diode 361 and switch 362 to the source electrode of FET 356. By applying the appropriate logic value to the terminals GG and HH, the potential on the source electrode in FET 356 can thus be appropriately varied to determine the voltage level at which FET 356 is switched on.

When FET 356 is switched on, a voltage arises across resistor 365 which is applied to an input for a pair of inverters 370 and 371, for supply to control counter 38 (see fig. 1).

The control counter 38, the stimulation-free period control circuit '+3, the reset circuit ^1, the asynchronous interval generator 15, the asynchronous clock control 16, and the width control circuit 17, all of which are indicated in FIG. 1, is shown in more detail in fig. 5A and 5B.

Pulses representing first divided clock pulses with a frequency produced by dividing the primary clock pulses from 12 o'clock (see Fig. 3A) by four are transferred to the various circuit components over the line "ih", as shown.

The output signal from the R-wave amplifier 32 is transmitted over the line

Z to the reset terminal for the control counter 38, such as

shown in fig. 5A. Upon detection of a suitable signal in the R-wave amplifier 32, a reset signal is applied to the control counter 38 - First divided clock pulses on the line 1<*>+ are transferred to the one input for the NOG gate ho, whose output is connected to the clock input for the counter 38. Counter 38 is a ripple-carrying counter, and produces output signals at its various output terminals in accordance with corresponding counts of clock

pulses applied to the counter's clock terminal. The primary function of the control counter 38 is, as briefly described above, to define a stimulation-free state or regulation interval, during which the reception of a naturally occurring heart pulse has no resetting effect, while the reception of such a pulse after this period will produce a resetting pulse, which indicates that heart functions are correct. There are two selectable output lines from the counter 38, one of which is taken out via line 373 from output Q^, and the other is taken out via line 37^ from outputs Q^ and Q1Q via an AND gate 376. The signals on lines 373 and

37^f represents a state change corresponding to clock pulses of respectively 2<9>/2= 256 and (2<10> + 27) /2= 576. The clock pulses on line 1^-, which have a duration of about 0.587 milliseconds, produce state changes on lines 373 °§ 37<*> + according to 150.15 and 337.83 milliseconds. A choice has thus been made between the different state change times on the lines 373 °g 37^ for determining the pacemaker's stimulation-free period. The choice between the signals on line 373 °S

37<*>+ is done by a multiplexer 377. Lines 373 and 37^ are respectively connected to the 0 input and the 1 input of the multiplexer 377. The A input is connected to the terminal Qg (NN) of the circuit 295 (Fig. 30) to pass the signal on this terminal to the multiplexer 377. The truth table of the multiplexer 377 indicates that pressing of a 0 state on the A terminal causes the signal on the 0 input terminal to be transferred to the output terminal and line 379. A 1 state applied to the A terminal connects the signal on the 1 input to the output line 379- The signal present on the output Qg for circuit 295 (fig. 30) and represents the control signal for the stimulation-free period, determines whether the circuit's stimulation-free period should be 150.1>+ millisec. as determined by the signal on line 373, or 337.83 milliseconds. as determined by the signal on line 37*+ - The output signal from the multiplexer 377 on line 379 is transferred to an inverting NOG gate l+5, the output of which is connected to the reset circuit k^ of the asynchronous generator as well as to one of the input terminals of the NOG gate ho on the entrance side of

the control counter 38. In operation, after it has been reset, the counter 38 begins to count clock pulses which are supplied to the counter's clock input through the NOG gate k-0. Upon reaching the predetermined counting step for the selected output line 373

or Y/h, an output signal is produced on line 379 to the inverting NOG gate <h>?<, so that a state change is produced on output line 382 from a normally high to a low level. Upon the change of state on line 382, the NOG gate *f0 is prevented from passing through further clock pulses to the counter 38, so that its counting process is stopped. The control counter 38 is thus caused to interrupt its counting until it is reset by a subsequent received pulse of the R-wave amplifier 32.

In addition to the output signals produced on the terminals

What? Q 7 and Q1Qj, an output signal is created on the terminal for the counter 38, so that this signal is transferred to the reset circuit kl for the asynchronous generator, as it now

will be described.

The reset circuit Kl for the asynchronous generator comprises two D-type multivibrators 38^ and 385. The D input of the multivibrator 38^ is connected to a high level, while the Q output of the multivibrator is connected to the D input of the multivibrator 385. The Q output of this multivibrator 385 is connected to the reset terminal of the multivibrator 38*+ ?

and the Q output of the multivibrator 385 provides the output signal from the reset circuit <>>+1, for transfer to the one input of the NOG gate 30 (Fig. 5B). The output signal from the NOG gate k$ on line 382 represents the selected stimulation-free period and is applied to the clock input of the multivibrator 38^. The output signal on the counter's terminal Q^ is applied to the clock input of the second multivibrator 385- After the control counter 38 has been reset, it thus begins its counting process and first reaches a counting step which produces an output signal on the terminal Q^_

thereby clocking the high signal level on the counter's D input through to the D input of the multivibrator 385. Uo the counter 38

then when the count step for the selected output line 373 or 37^5 is applied a clock pulse to the clock input of the multivibrator 385? so that a change of state is produced at its outputs, the Q output changing from low to high level and the Q output changing from high to low level. The output change from high to low level on the Q output, after it is applied to the NOG gate 30 (Fig. 5B), forms the reset signal for output to the asynchronous interval generator 15 (Fig. 5B).

Thus, it will be appreciated that if a reset signal is received on the reset terminal of the counter 38 before it reaches the count stage of the selected output line 373 or 37^, the counter is reset to begin its counting process all over again, without producing an output pulse from the multivibrator 385- This reset condition can be extended indefinitely, if e.g. an interference signal is caused to continuously reset the counter 38 within the stimulation-free period determined by the main control circuit 150. However, after the predetermined count step has been reached, the multivibrator 385, which has been previously "armed" with the signal on the terminal Q^ for the counter, a reset signal on the output terminal Q of the multivibrator 385-

It should be noted here that the presence or absence of a reset signal from the reset circuit for the asynchronous generator controls the work operation in demand mode for the entire clock generator circuit 10. If, for example, no reset signal is produced, the asynchronous interval generator 15 is allowed to carry out a continuous counting process, so that stimulation signals are produced at a preselected rate.

A NOG gate 387 is provided with its output connected to the reset terminal for the multivibrator 385 • One input to the NOG gate 387 is connected to the inverter 216

(see Fig. 3A). The other input to the NOG gate 387 is connected to the output Q (FF) of the D-type multivibrator 292

(Fig. 3C). If the switch 215 (fig. 3A) is closed, e.g.

of the proximity of a magnet for testing purposes or the like, a high output state is produced by the NOG gate 387 to continuously supply a reset voltage to the multivibrator 385, thereby blocking the generation of reset pulses, so that the clock generator circuit 10 is made to work asynchronously. In addition, the presence of a 0 signal on the output Q (FF) of the multivibrator 292 also produces a constant reset voltage on the output side of the NOG gate 387, to maintain the clock circuit 10 in asynchronous mode of operation or fixed clock operation.

The reset signal from the circuit !+1 which is output to the NOG gate 30, as indicated above, is transferred over a line 388 to a reset terminal of the asynchronous interval generator 15 (Fig. 5B). The asynchronous interval generator 15, which is of the ripple carrying counter type, receives clock pulses across the line 1 ■+ to its clock terminal to produce output signals at its various output terminals. In the embodiment shown, these output signals are derived, e.g. from terminals Qg-Q^*

These output signals are in themselves logical combinations of selected outputs, and such a combination selection can be used to determine the asynchronous interval out-clock for the clock generator circuit 10. More specifically, output signals from the terminals Q,-,, and Q1Q are used on the counter 15 in combination with a AND gate 390 to produce a change in the output state after about <1>+89,<1>+1 millisec. The output signal from the AND gate 390 is passed to input 7 of a multiplexer 391. The outputs at terminals Q^, Qg, Q^ and Q^q are combined by an AND gate 393 to produce a change in the output state after approximately 5M+.29 milliseconds. The output signal from the AND gate 393 is passed to the input terminal 6 of the multiplexer 391. The output terminal Q^ of the counter 15 is passed directly across the line 39<*>+ to the input 5 of the multiplexer 391, and exhibits a signal that changes state after approximately 600.58 milliseconds. The signals from the output terminals Qg and Q^ are combined by an AND gate 395, the output of which is connected to the input terminal k of the multiplexer 391, and which produces a state for change after approximately 675.66 milliseconds. The output terminals Q<, and Q11 provide signals which are combined in the AND gate 396, the output of which is passed to the input terminal 3 of the multiplexer 391 to produce a change of state after about 750.73 milliseconds. Terminals Qg, <Q>^ and Q1^ combine in AND gate 397, the output of which is passed to input terminal 2 of multiplexer 391 and produces a state change after about 825.81 milliseconds. Terminals Qg, Q^q and are combined in an AND gate 398, the output of which is passed to terminal 1 of multiplexer 391 and produces a state change after about 975.96 milliseconds. Finally, the signal from output terminal Q^2 is transferred directly to input terminal 0 of multiplexer 391 over line 399, causing a change of state after about 1201.17 milliseconds.

The control terminals A, B and C for the multiplexer 391 are each connected to a clock control terminal, respectively. Q^, Qg and Q^ (KK, LL, MM) for circuit 295 (see Fig. 3C). These control signals, which determine which of the inputs 0-7 should be connected to the output line ^-00, operate in accordance with the truth table given below:

The output time for any one of the different multiplex lines can thus be selected by a logical input signal to the multiplexer's input terminals, and the asynchronous working clock for the clock generator 10 can thus be chosen from among the different time intervals indicated above.

The output signal on the line <>>+00 from the multiplexer 391 is transferred to the width control circuit 17, which will be described in the following. The width control circuit 17 comprises two J-K master/slave multivibrators '+02 and <*>+03. The J input of the multivibrator <>>+02 is connected to a high potential, while the K input is connected to a low potential. The outputs Q and Q for the multivibrator k02 are connected respectively. with the J input and the K input of the multivibrator <h>Q2>. The Q output of the multivibrator <>>+03 is connected to the reset terminal of the multivibrator ^t-02,

and the Q output of the multivibrator ^03 forms the output of the width control circuit 17 as a whole. The signal on the '+00 line from the multiplexer 391 constitutes a clock signal for the multivibrator h02, which, when this signal occurs, produces a high signal level at the output Q and a low signal level at the output Q. The output of the width-determining multiplex circuit (described below) is connected to the clock input of the multivibrator ^03 for

clocking the input to the J-K terminals to the output terminals Q and Q. Specifically, the multiplexer <>>+05 receives first divided clock pulses over the line 1<*>+ to its 0 input terminal. In addition, it receives second divided clock pulses at a different division frequency from multivibrator 20^ (Fig. 3A) over line 208 (BB) to its 1 input terminal. Control terminal A receives its input signal from the width control signal on the Q output (EE) of the D multivibrator 290 (Fig. 3C). Depending on whether the present signal on the control terminal is of a high or low level, it is thus determined whether it is the input signal 0 or 1 that is transferred via the output terminal to the line ko6 for output to the clock terminal for the multivibrator <I>+03- It will be realized that the selection of clock pulses at the lower frequency produces a longer change of state on the output Q of the multivibrator k0$ than the higher clock pulse frequency on the input line 0 of the multiplexer, so that the possibility of width control of the stimulation pulses is created

which is produced by the pacemaker. The output signal from the multivibrator hO^ across the Q output is transferred over the line ho8

as a drive signal to the pulse generator circuit 21 (fig. 1 and h). The output signal on terminal Q of the multivibrator ^03 is transmitted

in addition to one of the inputs for the NOG gate 30, to form a further reset signal to the asynchronous interval generator 15. Thus, after generating an asynchronous signal, the asynchronous interval generator is reset to resume its timing of its next following asynchronous interval.

The external control unit, which is designated in its entirety by the reference number 500, is arranged for generating and transmitting both opening code and pulses for determining working parameters for the clock transmitter 10 as described above, and is shown in more detail in fig. 6A, 6B, 60 and 6D. The connections between these figures are indicated by corresponding letters. It will be seen that the circuits shown in fig. 6A-6D, in contrast to the circuits described above in the iTolantable clock generator 10 with reference to FIG. 1-5, are connected to ground to indicate a 0 state or low logic level, while +v represents a 1 state or high logic level.

The outer control circuit 500 comprises four main parts, each of which is surrounded by dashed lines. An oscillator part 501 (Fig. 6B) generates clock pulses to the rest of the circuits in the external control unit. The unlock code generator 502 (Fig. 6B) produces a special pulse train which will provide access to the main control circuit 150 for parameter setting (Figs. 1 and 3A-3C). A parameter code generator 503 (Fig. 60) produces an adjustable number of pulses, each number corresponding to a specific set of selectable clock generator parameters. Finally, a pulse output circuit 50h (Fig. 6D) generates the electromagnetic pulses for transmission to the main control circuit in accordance with the opening code generator 502 and the parameter code generated by the parameter code generator 503-

More specifically, the clock pulse generator 501 (fig. 6B) is activated by setting the switch 507 (fig. 6A). When moving from the upper position 508 to the lower position 509, the switch 507 produces a change from a low to a high state on the output line 510 for an oscillation-free circuit, which is designated in its entirety by the reference number 512. After returning the switch 507 to the upper position 508 , will the state of line 510 change from high to low, triggering a monostable multivibrator 515? which produces a reset signal on line 525 to the various circuit elements in the control unit as well as a subsequent activation pulse, as described below.

The oscillation-free circuit 512 comprises two NOG gates 516 and 517 as well as the monostable multivibrator 515? which is extended so that it cannot be triggered after the initial trigger signal has been received.

One input for the NOG gate 516 is connected through a resistor 519 to a positive terminal 520 for determining a normally high state on this terminal, which is additionally connected to the upper terminal 508 for the start-up switch 507. The other input to the NOG port 516 is connected to the output for the NOG port 517- In a similar way, one input for the NOG port 517 through a resistor 521 is connected to a positive terminal 520 and also to the lower terminal 509 of the switch 507. The other input for the NOG- gate 517 is connected to the output of the NOG gate 516. The output from the NOG gate 517 constitutes the output terminal for the entire circuit, and is connected to the monostable multivibrator 515-

As indicated above, the monostable multivibrator 515 is triggered

of a negatively directed pulse (ie a change from a high to a low state). Upon the occurrence of such a change of state, the output Q changes from a low to a high level, where it remains for a period of time that depends on the value of a resistor 523 and a capacitance 52<*>+, which forms the connection between

the multivibrator's RC terminal and resp. its R terminal and its C terminal. The R terminal is connected to the positive terminal 520.

The positive trigger input is connected to the Q output to produce the above-mentioned feature that the monostable multivibrator 515 cannot be triggered again after it has first been triggered by a negatively directed trailing edge of the generated pulse.

It will therefore be realized that when a negative is printed

rectified signal on the release input for the multivibrator 515? the Q output will change from a low to a high state, during which a reset signal is issued across line 525 to the various circuit components, as will be described below, to produce an initial initial state for these circuits. After the output Q of the multivibrator 515 is maintained at a high level for the time determined by the time constant of the capacitance 52^ and the resistor 523? it will change its state from high to low. This condition triggers another monostable multivibrator 527 (Fig. 6B), which provides a signal to a J-K master/slave multivibrator 528, which serves as a trigger circuit.

The monostable multivibrator 527 is connected in a similar manner to said monostable multivibrator 515? to be triggered by a negative-going pulse edge supply the trigger input with a minus level, fji to be maintained in the triggered state for a period of time determined by the RC time constant of the capacitance 530 and the resistor 531, which is connected between the RC terminal and the respective The C-clamp and the R-clamp. The R terminal is also connected to a positive

terminal 520. The positive trigger input is connected to the Q output to ensure that the monostable multivibrator 527 cannot be triggered again.

The J and K inputs of the multivibrator 528 are connected low, along with the clock input. The output of the monostable multivibrator 527 is connected to the setting terminal of the multivibrator 528, the output of which is taken from the Q terminal. The reset terminal is connected to the output of a pulse generator 523, which emits a pulse after completion of the generated pulse train in the control unit 500, as will be explained in more detail below. The output signal from the terminal Q of the multivibrator 528 produces an activation signal for the clock pulse generator 501 over the line 53^.

The clock pulse generator 501 comprises a ripple-carrying binary counter/divider and oscillator 53° in fourteen stages, a decade counter 537 and three NOG gates 539, 5^-0 and 5>+1. Oscillator/counter 536 and decade counter 537 are each equipped with a reset terminal connected to reset line 525, which is described above. The oscillator/counter 536 has its clock terminal and inverted clock terminal (0 and 0) connected by a capacitance 5<*>+3, a fixed resistor 5 l+ 1+ and a variable resistor 5^5 in series connection. Another fixed resistor 5^7 is connected from a point between the capacitance 5^3 and the resistor 5kk to an input of the NOG gate 539. The other input of the NOG gate 539 is connected to the output of the start-up multivibrator 528 across the line 53> +. The output signal from Qg of the oscillator/counter 536 is passed to an inverted NOG gate 570, to generate clock pulses for the opening code generator 520, which will be described in more detail below.

The frequency derived from the terminal Q^ of the oscillator/counter 536 corresponds to the internal clock frequency in the timer for clocking the received opening code and parameter control code into the various registers. This clock frequency is produced on the Q^ output of the counter 259 (fig. 3B).

The output signal on the terminal Qn 7 is connected to the clock input of the decade counter 537 and to the one input of the NOG gate 5^1• The output of the NOG gate 5*+1 , which feeds the clock pulses that appear on the terminal Q^ of the oscillator 536, is connected to the one input terminal for the NOG gate 577 (fig. 60), as well as to the clock input for the counter 558 (fig. 60). The output from terminal "6" for the decade counter 537 is connected to the counter's activating clock input, thereby stopping the counting process in the decade counter 537 after the counting step "6" has been reached. The output "6" of the counter 537 is additionally connected to another input of the NOG gate 5<>>+1 as well as to the various setting and resetting terminals of the parameter code generator 503 (Fig. 60), which are described below.

In operation, the clock pulse generator 501 will produce pulses as long as the signal on the line 53<*>+ is at a high level. However, when the signal level on line 53^ is low, the clock input to counter/oscillator 536 cannot vary, so that the generation of output pulses stops. The decade counter 537 serves to switch from the output of the opening code generator 502 (fig. 6B), after the opening code has been generated and emitted, to the output

for the parameter code generator 503 (Fig. 60), for outputting this generator's output code. This is achieved with the help of NOG- .

the port 5<*>+1 which is arranged to select between the output signals from the opening code generator and the subsequent parameter code. For the time at which the counter 537 reaches its "6" counter stage, the input to the NOG gate from said counter stage in the counter 537 will be at a low level, so that the passage of clock pulses from the output Qg of the oscillator 536 is prevented. Thus, the input to the NOG gate 555 due to the parameter code pulse train remains at a high level, allowing only the opening code produced by the generator 502 to be output to the output line 556. Upon reaching the count step "6" in the counter 537? the clock pulses produced on the output line Qq_ from the oscillator 536 are allowed to pass the NOG gate 5<*>+1 for output to the output line 556 through the NOG gates 577, 578 (Fig. 60) and 555 (Fig. 6B). The high state of the output "6" of the counter 537 creates a continuous reset state for the multivibrator 551 of the opening code generator 502, thereby creating a persistent high state at the output Q of this generator, for the purpose of allowing the parameter code stream to pass NOG -port 555? as will be described below.

The access code generator 502 comprises three J-K master/slave multivibrators 550, 551 and 552. The J input and the K input of the multivibrator 550 are connected to the Q output of the multivibrator.

552. The outputs Q and Q for the multivibrator 550 are connected respectively. with the J input and the K input of the multivibrator 551,

and the outputs Q and Q for the multivibrator 551 are in turn connected to the respective The J input and K input for the 552 multivibrator. The reset terminals for the 550 and 552 multivibrators as well as the set terminal for the 551 multivibrator

is connected to the feedback line 525- The setting terminals for the multivibrators 550 and 552, as well as the reset terminal for the multivibrator 551, are connected to the "6" output of the decade counter 537. The output of the opening code circuit is taken from the Q terminal of the multivibrator 551. Thus, the multivibrators 550 are put into operation -552 in the opening code generator starting by the signal on the reset line 525- After receiving clock pulses from the clock pulse generator 501, the output signal will . from the Q terminal of the multivibrator 551 produce the following logic sequence: 1000010 - at a frequency that is half the frequency of the output Qg of the oscillator/counter 536 (at the same frequency as from Q^).

The output Q of the multivibrator 551 is connected to one input to a NOG gate 555. It is assumed that the other input to the NOG gate 555 is at a high signal level

(which it maintains until the count step "6" of the decade counter 537 is reached, as will be apparent from the explanation below), thus the inverted output on line 556 will be: 1000010, which is inverted again by the transmitter coil, as described below.

As indicated above, the monostable pulse generator 151 (Fig. 3A) in the main control circuit 150 produces an output pulse only in response to a change in the input state from low to high level. The code produced by this monostable pulse generator in response to an over-transmitted digital signal equal to 01100010 is therefore 1000010. This is precisely the tKning code recognized by the circuit 270 (fig. 3B).

The parameter code generator 503 (Fig. 60) comprises a ripple carrying counter 558 with twelve stages, four BCD/decimal decoders 559,

560, 561 and 562, two inverting NOG gates 564 and 565, a

NOG port capable of comparison of at least six

inputs 566, as well as a J-K master/slave multivibrator 567.

Specifically, the counter receives 558 clock pulses from the output

for the NOG gate 541 (Fig. 6B), this being the clock frequency produced by the oscillator 536 divided by 2q. This reset terminal is connected to the reset line 525, and the output O^-Q]^ is connected to the externally controlled parameter selector circuit, which will be described below. The gate Q12 is connected to a main stop circuit 532, as indicated above,

for stopping the oscillator after complete counting of the parameter code. Furthermore, the outputs Q1 and Q2 of the counter 558 are connected to the inputs A and B of the BCD/decimal decoder 559.

The inputs C and D of the BCD/decimal decoder 559 are connected

a ground clamp to give these clamps a low signal level. A switch 570 with four positions and corresponding terminals connected to each of terminals 0,1,2 and 3 for the BCD/decimal decoder. The movable contact arm in the switch 570 is connected to a

of the inputs to the NOG gate 566 with six inputs.

The outputs Q 3 and of the counter 558 are connected to input terminals A and B, respectively, of the BCD/decimal decoder 560. Inputs C and D are connected to ground or low level. The outputs 0,1, 2 and

3 from the BCD/decimal decoder 560 are connected to each terminal in a further switch 571 with four contact positions. The movable contact arm of the switch 571 is connected to another input of the NOG gate 566 with six inputs. Output terminals Q5 - QQ are connected to respective inputs A-D of the BCD/decimal decoder 561. Outputs 0-7 of this decoder are connected to separate terminals of an eight-position switch whose contact arm also

is connected to an input for the NOG port 566 with six inputs.' The output terminal Qg of the counter 558 is connected to input A of the BCD/decimal decoder 562, while the inputs B-D of this decoder are connected to ground or low level. Outputs 0-3 for the BCD/decimal decoder are connected to a separate terminal for a re-

switch with four positions 573, whose contact arm is connected to one of the inputs for the NOG port 566 with six inputs. The output Q^q of the counter 558 is connected to an input for an inverting end

NOG port 564 (schematically shown only as an inverter), as well as to a

of the terminals for a switch 574 with two positions. The output of the inverting NOG gate 564 is connected to the second terminal of the switch 574. The contact arm of the switch 574 is connected to another input of the six-input NOG gate 566. Finally, the output Q1^ of the counter 558 is connected to the inputs

for an inverting NOG gate 565 (also only shown as a simple inverter) as well as to a terminal for a switch 575. The output of the inverting NOG gate 565 is connected to the other terminal for the two-position switch 575. The switch arm for the switch 575 is connected to a sixth input for the NOG port 566 with six inputs.

The output terminal for said NOG port 566 is connected to the clock terminal of the J-K multivibrator 567. The terminals J and K of this multivibrator 567 are connected respectively to low and high signal levels and the multivibrator output is taken from the Q terminal, which is connected to an input for the NOG port 577.

The output Q 12 of the counter 558 is connected to a main stop circuit 562 (fig. 6b) in the form of a multivibrator.

In operation, the various switches 570 - 575 are set to correspond to a predetermined set of operating parameters for the tachometer.

In the embodiment shown, e.g. the switch 570 the clock sensitivity parameter, which can be set corresponding to one of the output terminals 0, 1, 2, or 3 of the BCD/decimal decoder 559.

In a similar way, the switches 571, 572 and 573 can be connected

one of the corresponding terminals for the BCD/decimal decoders 560, 561 and 562 for appropriate setting of amplitude, pulse rate and stimulation-free period for the pacemaker, as desired. Toggle switches 574 and 575 can be set to determine the desired pulse width and operating mode for the clock generator. When each of the output terminals Q, - exhibits a state corresponding to the selected decimal number (0-3 for switch 570, 0-3 for switch 571, 0-7 for switch 572, 0-3 for switch 562, on or off for switch 574 and on or off for the switch 575, all inputs to the NOG gate 566 will be at a high signal level, so that a low signal level is created on the output side of the NOG gate 566. When clock pulses on

the output terminal Qp of the oscillator 536 is transferred to the output line 556 through the NOG gates 577, 578 and 579, at the same time the corresponding decimal number of pulses will be produced on the output line 556. When the next clock pulse occurs, the output states Q1 - will not coincide with the selected parameters which is determined by the positions of the respective switches 570 - 575. The output from the NOG gate 566 will therefore change from a low to a high state, so that a low signal state is produced on the Q terminal of the multivibrator 567. The low signal state that is applied to the NOG gate 577 prevents further transfer of clock pulses from

the output Qg of the oscillator 576. The number of pulses emitted by the line 556 therefore corresponds to a particular combination or set of desired operating parameters for the clock generator.

When the counter 558 reaches the counting step which produces a high signal state on the output Q12', the monostable multivibrator 532 (fig. 6b) is triggered to produce a feedback signal on its Q output, this signal being emitted to the reset terminal of the input circuit 528. (fig. 6b) . In the event of the aforementioned

reset signal, the state of the output Q of the multivibrator 528 changes from high to low signal level, so that further work of the oscillator 536 (fig. 6b) is blocked. The monostable multivibrator 532 (Fig. 6b) is connected to be triggered by a positively directed pulse, thereby producing a pulse of the width determined by the values of the capacitance 580 and the resistance 581, which are respectively connected between the terminals C and RC as well as to a high level, such as shown. The output Q is connected to the negative trigger terminal to produce a non-triggerable state after said triggering of a positively directed pulse edge.

In fig. 6D, it is shown that the opening code and the parameter code are output in sequence over line 556 to a pair of darlington transistors 583 and 584 for amplification and output to a generator coil 586 for an electromagnetic field. The voltage applied to the coil 586/ is regulated by a voltage regulator circuit 587, as well as the external components belonging to this circuit. In operation, the field generator coil 586 is thus placed close to the body of a wearer of the clock transmitter 10. Upon actuation of the activation switch 507 (Fig. 6a), the established opening code and the subsequent parameter code are generated and these codes are emitted in sequence to the coil 586, which thereby generates an electromagnetic field monster in accordance with this pulse train. The electromagnetic field thus produced is detected by the REED switch 215 Fig. 1 and 3A) for controlling the tachometer 10

in the manner described above.

To ensure that the control unit 500 works satisfactorily, is

an n-p-n transistor 589 connected between a positive voltage terminal 590 (which can be derived from the voltage regulator circuit 587, as shown) and ground. A light-emitting diode 592 and a collector resistor 593 are connected in series between the positive line 590 and the collector of the transistor 589. The emitter of the transistor 589 is connected to a ground potential, and the base of the transistor 589 is connected to the output Q of the multivibrator 528. Thus, when the output Q for the multivibrator 528 changes from a low to a high signal level, the junction between the base and the emitter of the transistor 589 is thus biased in the forward direction, thereby allowing current to flow through the light-emitting diode 592, with the aim of producing a visual indication of the circuit's operation.

The circuits described above can be made with the following special components. However, the components listed in the list below are only suggested as an example, as other components can also be used, as will be understood by those skilled in the art.

INTEGRATED_CIRCUITS_jRCA types2

Ports and inverters (RCA-tvper2

TRANSISTORS

DIODES

OPPONENT

CAPACITIES_

Although the invention has been illustrated by careful description of an exemplary embodiment, it will be understood that the described embodiment is only to be considered as an example, and that numerous changes and modifications by combination and arrangement of components can take place without the inventor

whose frame is exceeded, as it is defined in the subsequent

end patent claim.

Claims (4)

1. Implantable digital cardiac stimulator (10) adapted for supplying stimulating pulses to a heart contact electro- believed in accordance with selectable operating parameters which are determined by remote signals supplied from outside, said remote signals comprising a first signal low section indicating a predetermined access code, followed by a data section which determines said operating parameters of the stimulator, and the heart stimulator comprises: - a pulse generator (21) for generating said stimulating pulses and which is in connection with said cardiac contact electrode (11), - equipment (151) for receiving said remote signals and generating corresponding digital signals, - a recognition circuit (172) for said access code and arranged to emit a control signal upon receipt of a predetermined such code, - storage equipment (182, 184) for receiving and storing said parameter-determining data section, - a gate device (170) for receiving the parameter-determining data section, but arranged to only pass through this data section to the storage equipment ( 182, 184) upon receipt of said control signal from the recognition circuit (172), as well as - control means (15-17, 30-35, 41-45, 50) to control the stimulator's operating parameters in accordance with the stored data section in the storage device (182, 184), characterized in that said recognition circuit (172) is arranged to only recognize a distinctive pre-determined access code with both high and low logic states, as well as exclusively by such recognition to issue said control signal to the gate device (170) in order to open it for data transfer to the storage equipment (182, 184). 2. Heart stimulator as stated in claim 1, characterized in that it further comprises transmission means (152, 156) which connect said receiving equipment (151) for the remote signals and the storage equipment (182, 184) and is arranged to allow the introduction of said parameter-determining data section in the storage equipment only after the relevant data section has been received in its entirety by the receiving equipment. 3. Heart stimulator as stated in claim 1, characterized in that the data section of the remote signals comprises a train of electromagnetic pulses, and said storage equipment (182, 184) comprises organs (291) for counting these pulses to produce output signals which indicate the transmitted information of the pulses, while a memory device (295) is arranged for storing said output signals from the counter means for controlling the stimulator's operating parameters. 4. Heart stimulator as specified in claims 1-3, characterized in that said control means for controlling the stimulator's operating parameters include: - first regulator equipment (38, 43) connected to the storage equipment (182, 184) and assigned a part of the parameter-determining data section to time setting of a selected stimulation-free interval determined by said part of the parameter-determining data section, - other regulator equipment (15, 16) connected to the storage equipment (182, 184) and assigned to a part of the parameter-determining data section for timing a selected stimulation interval11 determined by said part of the parameter-determining data section, - detector equipment (32, 35) connected to the storage equipment (182, 184) and arranged to react to an assigned part of the parameter-determining data section for setting the sensitivity when sensing heart signals on the heart contact electrode as well as renewed timing of said stimulation-free interval at further to react to a heart esignal detected at said electrode, and - generator equipment (41) connected to the first regulator equipment (38, 43) and arranged to react to said detected heart signal with renewed timing of a stimulation interval only in the event that said stimulation-free interval has expired.