CH616791A5 - - Google Patents

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Publication number
CH616791A5
CH616791A5 CH804777A CH804777A CH616791A5 CH 616791 A5 CH616791 A5 CH 616791A5 CH 804777 A CH804777 A CH 804777A CH 804777 A CH804777 A CH 804777A CH 616791 A5 CH616791 A5 CH 616791A5
Authority
CH
Switzerland
Prior art keywords
synchronization
frame
loop
extension
data
Prior art date
Application number
CH804777A
Other languages
German (de)
English (en)
Inventor
Abraham M Gindi
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH616791A5 publication Critical patent/CH616791A5/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
    • H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/422—Synchronisation for ring networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Small-Scale Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CH804777A 1976-08-11 1977-06-30 CH616791A5 (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/713,453 US4042783A (en) 1976-08-11 1976-08-11 Method and apparatus for byte and frame synchronization on a loop system coupling a CPU channel to bulk storage devices

Publications (1)

Publication Number Publication Date
CH616791A5 true CH616791A5 (enExample) 1980-04-15

Family

ID=24866205

Family Applications (1)

Application Number Title Priority Date Filing Date
CH804777A CH616791A5 (enExample) 1976-08-11 1977-06-30

Country Status (6)

Country Link
US (1) US4042783A (enExample)
JP (1) JPS5320830A (enExample)
CH (1) CH616791A5 (enExample)
DE (1) DE2728010A1 (enExample)
ES (1) ES461505A1 (enExample)
GB (1) GB1566320A (enExample)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4195351A (en) * 1978-01-27 1980-03-25 International Business Machines Corporation Loop configured data transmission system
US4486852A (en) * 1978-06-05 1984-12-04 Fmc Corporation Synchronous time-shared data bus system
IT1118355B (it) * 1979-02-15 1986-02-24 Cselt Centro Studi Lab Telecom Sistema di interconnessione tra processori
ZA82860B (en) 1981-02-18 1982-12-29 Int Computers Ltd Data transmitting systems
EP0060307B1 (en) * 1981-03-12 1985-07-17 International Business Machines Corporation Method for connecting or disconnecting selected stations in a ring communication system, and ring communication system including selectively connectable stations
US4627070A (en) * 1981-09-16 1986-12-02 Fmc Corporation Asynchronous data bus system
FR2526249A1 (fr) * 1982-04-30 1983-11-04 Labo Electronique Physique Procede et dispositif de calage temporel automatique de stations dans un multiplex temporel pour bus optique et systeme de transmission et de traitement de donnees comprenant un tel dispositif
US4495617A (en) * 1982-09-09 1985-01-22 A.B. Dick Company Signal generation and synchronizing circuit for a decentralized ring network
US4614944A (en) * 1982-09-30 1986-09-30 Teleplex Corporation Telemetry system for distributed equipment controls and equipment monitors
JPS5979655A (ja) * 1982-10-27 1984-05-08 Toshiba Corp デ−タ伝送システム
CA1201784A (en) * 1982-12-03 1986-03-11 Hiroshi Shimizu Loop network system controlled by a simple clock station
ATE29098T1 (de) * 1982-12-28 1987-09-15 Ibm Zrz-koppelfeld unter verwendung einer geschlossenen schleifenverbindung.
US4677614A (en) * 1983-02-15 1987-06-30 Emc Controls, Inc. Data communication system and method and communication controller and method therefor, having a data/clock synchronizer and method
US4536876A (en) * 1984-02-10 1985-08-20 Prime Computer, Inc. Self initializing phase locked loop ring communications system
JPS615959U (ja) * 1984-06-15 1986-01-14 東京マグネツト応用製品株式会社 マグネツト利用の解錠装置におけるセンサ−装置
AT382253B (de) * 1984-06-22 1987-02-10 Austria Mikrosysteme Int Lose gekoppeltes verteiltes computersystem
US4779087A (en) * 1985-02-13 1988-10-18 Fujitsu Limited Loop transmission system with frame synchronization control
EP0239662B1 (en) * 1986-04-03 1993-03-17 Otis Elevator Company Two-way ring communication system for elevator group control
US5461631A (en) * 1992-12-15 1995-10-24 International Business Machines Corporation Method for bit resynchronization of code-constrained sequences
ES2070739B1 (es) * 1993-04-30 1997-06-01 Alcatel Standard Electrica Dispositivo de conversion de interfaces.
US5987038A (en) * 1996-12-23 1999-11-16 Texas Instruments Incorporated Sync detect circuit
US6088414A (en) * 1997-12-18 2000-07-11 Alcatel Usa Sourcing, L.P. Method of frequency and phase locking in a plurality of temporal frames
US7570724B1 (en) * 1999-10-14 2009-08-04 Pluris, Inc. Method of link word synchronization
US6760772B2 (en) 2000-12-15 2004-07-06 Qualcomm, Inc. Generating and implementing a communication protocol and interface for high data rate signal transfer
US8812706B1 (en) 2001-09-06 2014-08-19 Qualcomm Incorporated Method and apparatus for compensating for mismatched delays in signals of a mobile display interface (MDDI) system
US7073001B1 (en) * 2002-04-03 2006-07-04 Applied Micro Circuits Corporation Fault-tolerant digital communications channel having synchronized unidirectional links
CN105406947A (zh) 2003-06-02 2016-03-16 高通股份有限公司 生成并实施一用于更高数据率的讯号协议和接口
EP1661351A2 (en) 2003-08-13 2006-05-31 Qualcomm, Incorporated A signal interface for higher data rates
CN1879383A (zh) 2003-09-10 2006-12-13 高通股份有限公司 高数据速率接口
CN102801615A (zh) 2003-10-15 2012-11-28 高通股份有限公司 高数据速率接口
WO2005043862A1 (en) 2003-10-29 2005-05-12 Qualcomm Incorporated High data rate interface
CN101729205A (zh) 2003-11-12 2010-06-09 高通股份有限公司 具有改进链路控制的高数据速率接口
KR20060096161A (ko) 2003-11-25 2006-09-07 콸콤 인코포레이티드 향상된 링크 동기화를 제공하는 고속 데이터 레이트인터페이스
CN102497368A (zh) 2003-12-08 2012-06-13 高通股份有限公司 具有改进链路同步的高数据速率接口
JP2007528681A (ja) 2004-03-10 2007-10-11 クゥアルコム・インコーポレイテッド 高データレートインタフェース装置及び方法
EP1735986B1 (en) 2004-03-17 2013-05-22 Qualcomm, Incorporated High data rate interface apparatus and method
AU2005227500B2 (en) 2004-03-24 2008-12-04 Qualcomm Incorporated High data rate interface apparatus and method
CN1993948A (zh) 2004-06-04 2007-07-04 高通股份有限公司 高数据速率接口设备和方法
US8650304B2 (en) 2004-06-04 2014-02-11 Qualcomm Incorporated Determining a pre skew and post skew calibration data rate in a mobile display digital interface (MDDI) communication system
CN101103569B (zh) * 2004-11-24 2012-05-23 高通股份有限公司 用于传递数据的数字数据接口装置和方法
EP1825623A4 (en) * 2004-11-24 2011-08-24 Qualcomm Inc MESSAGE FORMAT OF AN INTERFACE DEVICE FOR DIGITAL DATA
US8699330B2 (en) 2004-11-24 2014-04-15 Qualcomm Incorporated Systems and methods for digital data transmission rate control
US8539119B2 (en) 2004-11-24 2013-09-17 Qualcomm Incorporated Methods and apparatus for exchanging messages having a digital data interface device message format
US8692838B2 (en) 2004-11-24 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer
US8667363B2 (en) 2004-11-24 2014-03-04 Qualcomm Incorporated Systems and methods for implementing cyclic redundancy checks
US8723705B2 (en) 2004-11-24 2014-05-13 Qualcomm Incorporated Low output skew double data rate serial encoder
US8873584B2 (en) 2004-11-24 2014-10-28 Qualcomm Incorporated Digital data interface device
US8730069B2 (en) 2005-11-23 2014-05-20 Qualcomm Incorporated Double data rate serial encoder
US8692839B2 (en) 2005-11-23 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3919483A (en) * 1973-12-26 1975-11-11 Ibm Parallel multiplexed loop interface for data transfer and control between data processing systems and subsystems
US3906153A (en) * 1973-12-26 1975-09-16 Ibm Remote synchronous loop operation over half-duplex communications link
US3919484A (en) * 1974-03-01 1975-11-11 Rca Corp Loop controller for a loop data communications system
US3967060A (en) * 1974-07-19 1976-06-29 Bell Telephone Laboratories, Incorporated Fast reframing arrangement for digital transmission systems

Also Published As

Publication number Publication date
ES461505A1 (es) 1978-05-16
US4042783A (en) 1977-08-16
JPS5320830A (en) 1978-02-25
DE2728010A1 (de) 1978-02-16
GB1566320A (en) 1980-04-30

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