IT1118355B - Sistema di interconnessione tra processori - Google Patents

Sistema di interconnessione tra processori

Info

Publication number
IT1118355B
IT1118355B IT67323/79A IT6732379A IT1118355B IT 1118355 B IT1118355 B IT 1118355B IT 67323/79 A IT67323/79 A IT 67323/79A IT 6732379 A IT6732379 A IT 6732379A IT 1118355 B IT1118355 B IT 1118355B
Authority
IT
Italy
Prior art keywords
processors
interconnection system
interconnection
Prior art date
Application number
IT67323/79A
Other languages
English (en)
Other versions
IT7967323A0 (it
Inventor
Gerardo Girardi
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Priority to IT67323/79A priority Critical patent/IT1118355B/it
Publication of IT7967323A0 publication Critical patent/IT7967323A0/it
Priority to JP1158980A priority patent/JPS55110336A/ja
Priority to EP80100665A priority patent/EP0014926A1/en
Priority to US06/121,445 priority patent/US4334305A/en
Application granted granted Critical
Publication of IT1118355B publication Critical patent/IT1118355B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/433—Loop networks with decentralised control with asynchronous transmission, e.g. token ring, register insertion
IT67323/79A 1979-02-15 1979-02-15 Sistema di interconnessione tra processori IT1118355B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT67323/79A IT1118355B (it) 1979-02-15 1979-02-15 Sistema di interconnessione tra processori
JP1158980A JPS55110336A (en) 1979-02-15 1980-02-04 System for connecting processors each other
EP80100665A EP0014926A1 (en) 1979-02-15 1980-02-11 Interprocessor connection system
US06/121,445 US4334305A (en) 1979-02-15 1980-02-14 Data-handling system with operatively interconnected processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT67323/79A IT1118355B (it) 1979-02-15 1979-02-15 Sistema di interconnessione tra processori

Publications (2)

Publication Number Publication Date
IT7967323A0 IT7967323A0 (it) 1979-02-15
IT1118355B true IT1118355B (it) 1986-02-24

Family

ID=11301442

Family Applications (1)

Application Number Title Priority Date Filing Date
IT67323/79A IT1118355B (it) 1979-02-15 1979-02-15 Sistema di interconnessione tra processori

Country Status (4)

Country Link
US (1) US4334305A (it)
EP (1) EP0014926A1 (it)
JP (1) JPS55110336A (it)
IT (1) IT1118355B (it)

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US4872125A (en) * 1987-06-26 1989-10-03 Daisy Systems Corporation Multiple processor accelerator for logic simulation
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US5282201A (en) * 1987-12-22 1994-01-25 Kendall Square Research Corporation Dynamic packet routing network
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US7707351B2 (en) * 2002-10-31 2010-04-27 Ring Technology Enterprises Of Texas, Llc Methods and systems for an identifier-based memory section
US7415565B2 (en) 2002-10-31 2008-08-19 Ring Technology Enterprises, Llc Methods and systems for a storage system with a program-controlled switch for routing data
US6879526B2 (en) * 2002-10-31 2005-04-12 Ring Technology Enterprises Llc Methods and apparatus for improved memory access
US7609574B2 (en) * 2005-09-28 2009-10-27 Intel Corporation Method, apparatus and system for global shared memory using serial optical memory
US7609575B2 (en) * 2005-09-28 2009-10-27 Intel Corporation Method, apparatus and system for N-dimensional sparse memory using serial optical memory
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FR2315725A1 (fr) * 1975-06-27 1977-01-21 Radiotechnique Compelec Procede d'exploitation de donnees dans un reseau a configuration en boucle, et reseau pour la mise en oeuvre du procede
US4042783A (en) * 1976-08-11 1977-08-16 International Business Machines Corporation Method and apparatus for byte and frame synchronization on a loop system coupling a CPU channel to bulk storage devices
US4071706A (en) * 1976-09-13 1978-01-31 Rca Corporation Data packets distribution loop
US4071824A (en) * 1976-10-04 1978-01-31 General Electric Company Shrouded jaws for hook-on type instruments
IT1108459B (it) * 1978-10-11 1985-12-09 Cselt Centro Studi Lab Telecom Sistema di comunicazione a commutazione di pacchetto

Also Published As

Publication number Publication date
US4334305A (en) 1982-06-08
JPS55110336A (en) 1980-08-25
EP0014926A1 (en) 1980-09-03
IT7967323A0 (it) 1979-02-15

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