CH596612A5 - - Google Patents

Info

Publication number
CH596612A5
CH596612A5 CH713875A CH713875A CH596612A5 CH 596612 A5 CH596612 A5 CH 596612A5 CH 713875 A CH713875 A CH 713875A CH 713875 A CH713875 A CH 713875A CH 596612 A5 CH596612 A5 CH 596612A5
Authority
CH
Switzerland
Application number
CH713875A
Inventor
Silvano Giorcelli
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Publication of CH596612A5 publication Critical patent/CH596612A5/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1633—Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/1407—Checkpointing the instruction stream

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Hardware Redundancy (AREA)
CH713875A 1974-06-03 1975-06-03 CH596612A5 (xx)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT68735/74A IT1014277B (it) 1974-06-03 1974-06-03 Sistema di controllo di elaboratori di processo operanti in parallelo

Publications (1)

Publication Number Publication Date
CH596612A5 true CH596612A5 (xx) 1978-03-15

Family

ID=11310420

Family Applications (1)

Application Number Title Priority Date Filing Date
CH713875A CH596612A5 (xx) 1974-06-03 1975-06-03

Country Status (4)

Country Link
US (1) US4030074A (xx)
CH (1) CH596612A5 (xx)
GB (1) GB1511553A (xx)
IT (1) IT1014277B (xx)

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DE2701924C3 (de) * 1977-01-19 1987-07-30 Standard Elektrik Lorenz Ag, 7000 Stuttgart Steuereinrichtung für spurgebundene Fahrzeuge
DE2701925C3 (de) * 1977-01-19 1981-10-15 Standard Elektrik Lorenz Ag, 7000 Stuttgart Fahrzeugsteuerung mit zwei Bordrechnern
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DE2729362C2 (de) * 1977-06-29 1982-07-08 Siemens AG, 1000 Berlin und 8000 München Digitale Datenverarbeitungsanordnung, insbesondere für die Eisenbahnsicherungstechnik, mit in zwei Kanälen dieselben Informationen verarbeitenden Schaltwerken
IT1111606B (it) * 1978-03-03 1986-01-13 Cselt Centro Studi Lab Telecom Sistema elaborativo modulare multiconfigurabile integrato con un sistema di preelaborazione
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DE2939935A1 (de) * 1979-09-28 1981-04-09 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Sichere datenverarbeitungseinrichtung
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IT1151351B (it) * 1982-01-19 1986-12-17 Italtel Spa Disposizione circuitale atta a realizzare lo scambio di dati tra una coppia di elaboratori operanti secondo il principio master-slave
US4698785A (en) * 1983-12-02 1987-10-06 Desmond John P Method and apparatus for detecting control system data processing errors
JPS61212653A (ja) * 1985-03-18 1986-09-20 Honda Motor Co Ltd 内燃エンジンの電子制御装置
DE3518105A1 (de) * 1985-05-21 1986-11-27 Alfred Teves Gmbh, 6000 Frankfurt Verfahren und schaltungsanordnung zur unterdrueckung von kurzzeitigen stoerungen
US4751639A (en) 1985-06-24 1988-06-14 Ncr Corporation Virtual command rollback in a fault tolerant data processing system
US4703481A (en) * 1985-08-16 1987-10-27 Hewlett-Packard Company Method and apparatus for fault recovery within a computing system
EP0228559A1 (de) * 1985-12-17 1987-07-15 BBC Brown Boveri AG Fehlertolerante Mehrrechneranordnung
DE3639055C2 (de) * 1986-11-14 1998-02-05 Bosch Gmbh Robert Verfahren zur Betriebsüberwachung und Fehlerkorrektur von Rechnern eines Mehrrechnersystems und Mehrrechnersystem
DE3642851A1 (de) * 1986-12-16 1988-06-30 Bbc Brown Boveri & Cie Fehlertolerantes rechensystem und verfahren zum erkennen, lokalisieren und eliminieren von fehlerhaften einheiten in einem solchen system
US5185877A (en) * 1987-09-04 1993-02-09 Digital Equipment Corporation Protocol for transfer of DMA data
US4907228A (en) * 1987-09-04 1990-03-06 Digital Equipment Corporation Dual-rail processor with error checking at single rail interfaces
EP0306244B1 (en) * 1987-09-04 1995-06-21 Digital Equipment Corporation Fault tolerant computer system with fault isolation
EP0306211A3 (en) * 1987-09-04 1990-09-26 Digital Equipment Corporation Synchronized twin computer system
US4916704A (en) * 1987-09-04 1990-04-10 Digital Equipment Corporation Interface of non-fault tolerant components to fault tolerant system
CA2003338A1 (en) * 1987-11-09 1990-06-09 Richard W. Cutts, Jr. Synchronization of fault-tolerant computer system having multiple processors
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5065312A (en) * 1989-08-01 1991-11-12 Digital Equipment Corporation Method of converting unique data to system data
US5068851A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Apparatus and method for documenting faults in computing modules
US5163138A (en) * 1989-08-01 1992-11-10 Digital Equipment Corporation Protocol for read write transfers via switching logic by transmitting and retransmitting an address
US5153881A (en) * 1989-08-01 1992-10-06 Digital Equipment Corporation Method of handling errors in software
US5068780A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones
EP0415545B1 (en) * 1989-08-01 1996-06-19 Digital Equipment Corporation Method of handling errors in software
US5251227A (en) * 1989-08-01 1993-10-05 Digital Equipment Corporation Targeted resets in a data processor including a trace memory to store transactions
US5048022A (en) * 1989-08-01 1991-09-10 Digital Equipment Corporation Memory device with transfer of ECC signals on time division multiplexed bidirectional lines
EP0481128B1 (en) * 1990-10-16 1998-01-14 Koninklijke Philips Electronics N.V. Data processor system based on an (N, k) symbol code having symbol error correctibility and plural error mendability
US5313625A (en) * 1991-07-30 1994-05-17 Honeywell Inc. Fault recoverable computer system
US5838894A (en) 1992-12-17 1998-11-17 Tandem Computers Incorporated Logical, fail-functional, dual central processor units formed from three processor units
US5751932A (en) * 1992-12-17 1998-05-12 Tandem Computers Incorporated Fail-fast, fail-functional, fault-tolerant multiprocessor system
JP3283659B2 (ja) * 1993-10-07 2002-05-20 富士通株式会社 Ｆｉｆｏメモリの誤動作検出方法及び装置
US5630056A (en) * 1994-09-20 1997-05-13 Stratus Computer, Inc. Digital data processing methods and apparatus for fault detection and fault tolerance
DE19511842A1 (de) * 1995-03-31 1996-10-02 Teves Gmbh Alfred Verfahren und Schaltungsanordnung zur Überwachung einer Datenverarbeitungsschaltung
AU1270497A (en) * 1995-12-18 1997-07-14 Elsag International N.V. Processor independent error checking arrangement
US5953742A (en) * 1996-07-01 1999-09-14 Sun Microsystems, Inc. Memory management in fault tolerant computer systems utilizing a first and second recording mechanism and a reintegration mechanism
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
US6820213B1 (en) 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6691225B1 (en) 2000-04-14 2004-02-10 Stratus Technologies Bermuda Ltd. Method and apparatus for deterministically booting a computer system having redundant components
US7065672B2 (en) 2001-03-28 2006-06-20 Stratus Technologies Bermuda Ltd. Apparatus and methods for fault-tolerant computing using a switching fabric
US6928583B2 (en) * 2001-04-11 2005-08-09 Stratus Technologies Bermuda Ltd. Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep
US20040193763A1 (en) * 2003-03-28 2004-09-30 Fujitsu Limited Inter-bus communication interface device and data security device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1084147A (xx) * 1952-03-31 1955-01-17
SE313849B (xx) * 1966-03-25 1969-08-25 Ericsson Telefon Ab L M
US3409879A (en) * 1966-03-30 1968-11-05 Bell Telephone Labor Inc Computer organization employing plural operand storage
US3533082A (en) * 1968-01-15 1970-10-06 Ibm Instruction retry apparatus including means for restoring the original contents of altered source operands
US3668644A (en) * 1970-02-09 1972-06-06 Burroughs Corp Failsafe memory system
US3786430A (en) * 1971-11-15 1974-01-15 Ibm Data processing system including a small auxiliary processor for overcoming the effects of faulty hardware

Also Published As

Publication number Publication date
GB1511553A (en) 1978-05-24
IT1014277B (it) 1977-04-20
US4030074A (en) 1977-06-14

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Legal Events

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PL Patent ceased