CH592366A5 - - Google Patents

Info

Publication number
CH592366A5
CH592366A5 CH743775A CH743775A CH592366A5 CH 592366 A5 CH592366 A5 CH 592366A5 CH 743775 A CH743775 A CH 743775A CH 743775 A CH743775 A CH 743775A CH 592366 A5 CH592366 A5 CH 592366A5
Authority
CH
Switzerland
Application number
CH743775A
Original Assignee
Ebauches Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebauches Sa filed Critical Ebauches Sa
Priority to CH743775A priority Critical patent/CH592366A5/xx
Priority to DE2547323A priority patent/DE2547323C3/de
Priority to US05/691,242 priority patent/US4080512A/en
Publication of CH592366A5 publication Critical patent/CH592366A5/xx

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
CH743775A 1975-06-05 1975-06-05 CH592366A5 (enExample)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CH743775A CH592366A5 (enExample) 1975-06-05 1975-06-05
DE2547323A DE2547323C3 (de) 1975-06-05 1975-10-22 Trägerplatte für wenigstens eine integrierte Halbleitershaltung
US05/691,242 US4080512A (en) 1975-06-05 1976-06-01 Substrate for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH743775A CH592366A5 (enExample) 1975-06-05 1975-06-05

Publications (1)

Publication Number Publication Date
CH592366A5 true CH592366A5 (enExample) 1977-10-31

Family

ID=4325116

Family Applications (1)

Application Number Title Priority Date Filing Date
CH743775A CH592366A5 (enExample) 1975-06-05 1975-06-05

Country Status (3)

Country Link
US (1) US4080512A (enExample)
CH (1) CH592366A5 (enExample)
DE (1) DE2547323C3 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5555541A (en) * 1978-10-20 1980-04-23 Hitachi Ltd Semiconductor element
DE3027410A1 (de) * 1980-07-19 1982-02-18 Schering Ag, 1000 Berlin Und 4619 Bergkamen Verfahren zur eingabe von informationen an galvanisieranlagen, sowie zugehoerige ware und vorrichtung
GB2111215A (en) * 1981-10-31 1983-06-29 Alastair Sibbald Electrochemical sensor assembly
US4641043A (en) * 1985-09-12 1987-02-03 Honeywell Inc. Printed wiring board means with isolated voltage source means
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
JPH07111971B2 (ja) * 1989-10-11 1995-11-29 三菱電機株式会社 集積回路装置の製造方法
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5168345A (en) * 1990-08-15 1992-12-01 Lsi Logic Corporation Semiconductor device having a universal die size inner lead layout
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
KR0156622B1 (ko) * 1995-04-27 1998-10-15 문정환 반도체 패키지,리드프레임 및 제조방법
US6212077B1 (en) 1999-01-25 2001-04-03 International Business Machines Corporation Built-in inspection template for a printed circuit
JP7183964B2 (ja) * 2019-06-11 2022-12-06 株式会社デンソー 半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3374533A (en) * 1965-05-26 1968-03-26 Sprague Electric Co Semiconductor mounting and assembly method
US3405224A (en) * 1966-04-20 1968-10-08 Nippon Electric Co Sealed enclosure for electronic device
US3628095A (en) * 1970-12-02 1971-12-14 Sperry Rand Corp Power distribution bus arrangement for printed circuit board applications

Also Published As

Publication number Publication date
DE2547323B2 (de) 1980-07-10
DE2547323A1 (de) 1976-12-16
US4080512A (en) 1978-03-21
DE2547323C3 (de) 1981-05-27

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Legal Events

Date Code Title Description
PL Patent ceased
PL Patent ceased