CH493936A - Semiconductor arrangement and method for manufacturing the semiconductor arrangement - Google Patents
Semiconductor arrangement and method for manufacturing the semiconductor arrangementInfo
- Publication number
- CH493936A CH493936A CH1514368A CH1514368A CH493936A CH 493936 A CH493936 A CH 493936A CH 1514368 A CH1514368 A CH 1514368A CH 1514368 A CH1514368 A CH 1514368A CH 493936 A CH493936 A CH 493936A
- Authority
- CH
- Switzerland
- Prior art keywords
- semiconductor arrangement
- manufacturing
- semiconductor
- arrangement
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US67522567A | 1967-10-13 | 1967-10-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
CH493936A true CH493936A (en) | 1970-07-15 |
Family
ID=24709560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH1514368A CH493936A (en) | 1967-10-13 | 1968-10-10 | Semiconductor arrangement and method for manufacturing the semiconductor arrangement |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPS5334472B1 (en) |
CH (1) | CH493936A (en) |
DE (2) | DE1803025B2 (en) |
FR (1) | FR1587465A (en) |
GB (1) | GB1244013A (en) |
NL (1) | NL158323C (en) |
SE (1) | SE402503B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2081248A1 (en) * | 1970-03-23 | 1971-12-03 | Sescosem | Silicon intergrated circuits - with high parasitic mist threshold voltage by localized diffusion |
JPS5193874A (en) * | 1975-02-15 | 1976-08-17 | Handotaisochino seizohoho | |
US4557036A (en) * | 1982-03-31 | 1985-12-10 | Nippon Telegraph & Telephone Public Corp. | Semiconductor device and process for manufacturing the same |
US4638400A (en) * | 1985-10-24 | 1987-01-20 | General Electric Company | Refractory metal capacitor structures, particularly for analog integrated circuit devices |
US6495442B1 (en) | 2000-10-18 | 2002-12-17 | Magic Corporation | Post passivation interconnection schemes on top of the IC chips |
-
1968
- 1968-09-27 GB GB4611768A patent/GB1244013A/en not_active Expired
- 1968-10-07 NL NL6814320A patent/NL158323C/en not_active IP Right Cessation
- 1968-10-08 JP JP7343468A patent/JPS5334472B1/ja active Pending
- 1968-10-10 CH CH1514368A patent/CH493936A/en not_active IP Right Cessation
- 1968-10-11 FR FR1587465D patent/FR1587465A/fr not_active Expired
- 1968-10-14 DE DE19681803025 patent/DE1803025B2/en not_active Ceased
- 1968-10-14 DE DE19686802214 patent/DE6802214U/en not_active Expired
- 1968-10-14 SE SE1383768A patent/SE402503B/en unknown
Also Published As
Publication number | Publication date |
---|---|
FR1587465A (en) | 1970-03-20 |
NL6814320A (en) | 1969-04-15 |
DE1803025A1 (en) | 1969-09-04 |
SE402503B (en) | 1978-07-03 |
NL158323C (en) | 1982-02-16 |
NL158323B (en) | 1978-10-16 |
DE1803025B2 (en) | 1972-06-15 |
JPS5334472B1 (en) | 1978-09-20 |
DE6802214U (en) | 1972-04-06 |
GB1244013A (en) | 1971-08-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PL | Patent ceased |