CH450554A - Verfahren zur Herstellung einer Halbleiteranordnung mit einer Mesa - Google Patents
Verfahren zur Herstellung einer Halbleiteranordnung mit einer MesaInfo
- Publication number
- CH450554A CH450554A CH1021765A CH1021765A CH450554A CH 450554 A CH450554 A CH 450554A CH 1021765 A CH1021765 A CH 1021765A CH 1021765 A CH1021765 A CH 1021765A CH 450554 A CH450554 A CH 450554A
- Authority
- CH
- Switzerland
- Prior art keywords
- mesa
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/043—Dual dielectric
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/049—Equivalence and options
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/145—Shaped junctions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/912—Displacing pn junction
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/92—Controlling diffusion profile by oxidation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE1964S0092168 DE1439417B2 (de) | 1964-07-21 | 1964-07-21 | Verfahren zum herstellen einer halbleiteranordnung |
Publications (1)
Publication Number | Publication Date |
---|---|
CH450554A true CH450554A (de) | 1968-01-31 |
Family
ID=7517035
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH1021765A CH450554A (de) | 1964-07-21 | 1965-07-21 | Verfahren zur Herstellung einer Halbleiteranordnung mit einer Mesa |
Country Status (9)
Country | Link |
---|---|
US (1) | US3463681A (de) |
AT (1) | AT260308B (de) |
BE (1) | BE667183A (de) |
CH (1) | CH450554A (de) |
DE (1) | DE1439417B2 (de) |
FI (1) | FI44431B (de) |
GB (1) | GB1110321A (de) |
NL (1) | NL6508744A (de) |
SE (1) | SE312178B (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3460009A (en) * | 1967-12-29 | 1969-08-05 | Westinghouse Electric Corp | Constant gain power transistor |
US3912556A (en) * | 1971-10-27 | 1975-10-14 | Motorola Inc | Method of fabricating a scannable light emitting diode array |
NL185484C (nl) * | 1975-04-28 | 1990-04-17 | Philips Nv | Halfgeleiderinrichting met een halfgeleiderlichaam bevattende tenminste een transistor. |
JPS5346285A (en) * | 1976-10-08 | 1978-04-25 | Hitachi Ltd | Mesa type high breakdown voltage semiconductor device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2890395A (en) * | 1957-10-31 | 1959-06-09 | Jay W Lathrop | Semiconductor construction |
US2899344A (en) * | 1958-04-30 | 1959-08-11 | Rinse in | |
US2930722A (en) * | 1959-02-03 | 1960-03-29 | Bell Telephone Labor Inc | Method of treating silicon |
US3040218A (en) * | 1959-03-10 | 1962-06-19 | Hoffman Electronics Corp | Constant current devices |
US3189799A (en) * | 1961-06-14 | 1965-06-15 | Microwave Ass | Semiconductor devices and method of fabricating them |
US3093507A (en) * | 1961-10-06 | 1963-06-11 | Bell Telephone Labor Inc | Process for coating with silicon dioxide |
US3241010A (en) * | 1962-03-23 | 1966-03-15 | Texas Instruments Inc | Semiconductor junction passivation |
US3294600A (en) * | 1962-11-26 | 1966-12-27 | Nippon Electric Co | Method of manufacture of semiconductor elements |
-
1964
- 1964-07-21 DE DE1964S0092168 patent/DE1439417B2/de active Granted
-
1965
- 1965-07-07 NL NL6508744A patent/NL6508744A/xx unknown
- 1965-07-14 US US471831A patent/US3463681A/en not_active Expired - Lifetime
- 1965-07-19 SE SE9508/65A patent/SE312178B/xx unknown
- 1965-07-20 FI FI1736/65A patent/FI44431B/fi active
- 1965-07-20 AT AT668065A patent/AT260308B/de active
- 1965-07-20 GB GB30765/65A patent/GB1110321A/en not_active Expired
- 1965-07-20 BE BE667183A patent/BE667183A/xx unknown
- 1965-07-21 CH CH1021765A patent/CH450554A/de unknown
Also Published As
Publication number | Publication date |
---|---|
BE667183A (de) | 1966-01-20 |
NL6508744A (de) | 1966-01-24 |
SE312178B (de) | 1969-07-07 |
AT260308B (de) | 1968-02-26 |
DE1439417A1 (de) | 1969-03-06 |
DE1439417B2 (de) | 1976-09-23 |
US3463681A (en) | 1969-08-26 |
GB1110321A (en) | 1968-04-18 |
FI44431B (de) | 1971-08-02 |
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