CA966085A - Method of manufacturing etched patterns in thin layers having defined edge profiles - Google Patents
Method of manufacturing etched patterns in thin layers having defined edge profilesInfo
- Publication number
- CA966085A CA966085A CA138,894A CA138894A CA966085A CA 966085 A CA966085 A CA 966085A CA 138894 A CA138894 A CA 138894A CA 966085 A CA966085 A CA 966085A
- Authority
- CA
- Canada
- Prior art keywords
- thin layers
- edge profiles
- defined edge
- etched patterns
- manufacturing etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/08—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by electric discharge, e.g. by spark erosion
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2117199A DE2117199C3 (de) | 1971-04-08 | 1971-04-08 | Verfahren zur Herstellung geätzter Muster in dünnen Schichten mit definierten Kantenprofilen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA966085A true CA966085A (en) | 1975-04-15 |
Family
ID=5804229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA138,894A Expired CA966085A (en) | 1971-04-08 | 1972-04-05 | Method of manufacturing etched patterns in thin layers having defined edge profiles |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US3839177A (enExample) |
| JP (1) | JPS5123265B1 (enExample) |
| CA (1) | CA966085A (enExample) |
| DE (1) | DE2117199C3 (enExample) |
| FR (1) | FR2132745B1 (enExample) |
| GB (1) | GB1383848A (enExample) |
| IT (1) | IT960866B (enExample) |
| NL (1) | NL7204499A (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7213625A (enExample) * | 1972-10-07 | 1974-04-09 | ||
| GB1485015A (en) * | 1974-10-29 | 1977-09-08 | Mullard Ltd | Semi-conductor device manufacture |
| US4123663A (en) * | 1975-01-22 | 1978-10-31 | Tokyo Shibaura Electric Co., Ltd. | Gas-etching device |
| NL7607298A (nl) * | 1976-07-02 | 1978-01-04 | Philips Nv | Werkwijze voor het vervaardigen van een inrichting en inrichting vervaardigd volgens de werkwijze. |
| JPS5812234B2 (ja) * | 1976-12-24 | 1983-03-07 | 一實 奥田 | 表示入りダイヤモンドの製造方法 |
| NL8303316A (nl) * | 1983-09-28 | 1985-04-16 | Philips Nv | Werkwijze voor het vervaardigen van een inrichting voor het uitzenden van licht. |
| US4543320A (en) * | 1983-11-08 | 1985-09-24 | Energy Conversion Devices, Inc. | Method of making a high performance, small area thin film transistor |
| EP0187882B1 (de) * | 1985-01-17 | 1989-04-05 | Ibm Deutschland Gmbh | Verfahren zur Herstellung von Kontakten mit niedrigem Übergangswiderstand |
| DE10135872A1 (de) * | 2001-07-24 | 2003-02-27 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung einer Linse |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3410774A (en) * | 1965-10-23 | 1968-11-12 | Ibm | Method and apparatus for reverse sputtering selected electrically exposed areas of a cathodically biased workpiece |
| US3474021A (en) * | 1966-01-12 | 1969-10-21 | Ibm | Method of forming openings using sequential sputtering and chemical etching |
| US3479269A (en) * | 1967-01-04 | 1969-11-18 | Bell Telephone Labor Inc | Method for sputter etching using a high frequency negative pulse train |
| US3483108A (en) * | 1967-05-29 | 1969-12-09 | Gen Electric | Method of chemically etching a non-conductive material using an electrolytically controlled mask |
| US3585121A (en) * | 1967-11-17 | 1971-06-15 | Nat Res Dev | Diffraction gratings |
| US3676317A (en) * | 1970-10-23 | 1972-07-11 | Stromberg Datagraphix Inc | Sputter etching process |
| US3733258A (en) * | 1971-02-03 | 1973-05-15 | Rca Corp | Sputter-etching technique for recording holograms or other fine-detail relief patterns in hard durable materials |
-
1971
- 1971-04-08 DE DE2117199A patent/DE2117199C3/de not_active Expired
-
1972
- 1972-04-05 IT IT89547/72A patent/IT960866B/it active
- 1972-04-05 NL NL7204499A patent/NL7204499A/xx unknown
- 1972-04-05 CA CA138,894A patent/CA966085A/en not_active Expired
- 1972-04-05 US US00241243A patent/US3839177A/en not_active Expired - Lifetime
- 1972-04-05 JP JP47033607A patent/JPS5123265B1/ja active Pending
- 1972-04-05 GB GB1567372A patent/GB1383848A/en not_active Expired
- 1972-04-07 FR FR7212244A patent/FR2132745B1/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2117199A1 (de) | 1972-10-12 |
| DE2117199C3 (de) | 1974-08-22 |
| JPS5123265B1 (enExample) | 1976-07-15 |
| DE2117199B2 (de) | 1974-01-24 |
| US3839177A (en) | 1974-10-01 |
| FR2132745A1 (enExample) | 1972-11-24 |
| NL7204499A (enExample) | 1972-10-10 |
| IT960866B (it) | 1973-11-30 |
| GB1383848A (en) | 1974-02-12 |
| FR2132745B1 (enExample) | 1976-06-11 |
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