CA935939A - Instruction translation control with extended address prefix decoding - Google Patents

Instruction translation control with extended address prefix decoding

Info

Publication number
CA935939A
CA935939A CA094948A CA94948A CA935939A CA 935939 A CA935939 A CA 935939A CA 094948 A CA094948 A CA 094948A CA 94948 A CA94948 A CA 94948A CA 935939 A CA935939 A CA 935939A
Authority
CA
Canada
Prior art keywords
address prefix
translation control
extended address
instruction translation
prefix decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA094948A
Other languages
English (en)
Other versions
CA94948S (en
Inventor
John E. Mekota, Jr.
M. Hudson David
G. Rankin Thomas
E. Champagne Jean
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Application granted granted Critical
Publication of CA935939A publication Critical patent/CA935939A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
CA094948A 1969-11-12 1970-10-06 Instruction translation control with extended address prefix decoding Expired CA935939A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US87590269A 1969-11-12 1969-11-12

Publications (1)

Publication Number Publication Date
CA935939A true CA935939A (en) 1973-10-23

Family

ID=25366578

Family Applications (1)

Application Number Title Priority Date Filing Date
CA094948A Expired CA935939A (en) 1969-11-12 1970-10-06 Instruction translation control with extended address prefix decoding

Country Status (4)

Country Link
US (1) US3657705A (de)
CA (1) CA935939A (de)
DE (1) DE2055784A1 (de)
GB (1) GB1320241A (de)

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US4740911A (en) * 1984-10-12 1988-04-26 Elxsi International Dynamically controlled interleaving
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JP2902402B2 (ja) * 1987-09-30 1999-06-07 三菱電機株式会社 データ処理装置
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US5231637A (en) * 1988-01-27 1993-07-27 Oki Electric Industry Co., Ltd. Apparatus for testing a PLA by measuring a current consumed by the PLO when activated with known codes
JPH01204147A (ja) * 1988-02-09 1989-08-16 Toshiba Corp アドレス修飾回路
US5594908A (en) * 1989-12-27 1997-01-14 Hyatt; Gilbert P. Computer system having a serial keyboard, a serial display, and a dynamic memory with memory refresh
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US5423013A (en) * 1991-09-04 1995-06-06 International Business Machines Corporation System for addressing a very large memory with real or virtual addresses using address mode registers
WO1993019416A1 (en) * 1992-03-25 1993-09-30 Zilog, Inc. Fast instruction decoding in a pipeline processor
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US6014735A (en) * 1998-03-31 2000-01-11 Intel Corporation Instruction set extension using prefixes
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US7529912B2 (en) * 2002-02-12 2009-05-05 Via Technologies, Inc. Apparatus and method for instruction-level specification of floating point format
US7315921B2 (en) 2002-02-19 2008-01-01 Ip-First, Llc Apparatus and method for selective memory attribute control
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7546446B2 (en) * 2002-03-08 2009-06-09 Ip-First, Llc Selective interrupt suppression
US7395412B2 (en) * 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7185180B2 (en) * 2002-04-02 2007-02-27 Ip-First, Llc Apparatus and method for selective control of condition code write back
US7380103B2 (en) * 2002-04-02 2008-05-27 Ip-First, Llc Apparatus and method for selective control of results write back
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7373483B2 (en) * 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
US7155598B2 (en) * 2002-04-02 2006-12-26 Ip-First, Llc Apparatus and method for conditional instruction execution
US7380109B2 (en) * 2002-04-15 2008-05-27 Ip-First, Llc Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor
US6957321B2 (en) * 2002-06-19 2005-10-18 Intel Corporation Instruction set extension using operand bearing NOP instructions
US7917734B2 (en) * 2003-06-30 2011-03-29 Intel Corporation Determining length of instruction with multiple byte escape code based on information from other than opcode byte
US8738843B2 (en) * 2010-12-20 2014-05-27 Lsi Corporation Data manipulation during memory backup
GB2486739B (en) * 2010-12-24 2018-09-19 Qualcomm Technologies Int Ltd Instruction execution

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DE1190706B (de) * 1963-07-17 1965-04-08 Telefunken Patent In zwei abwechselnden Zyklen arbeitende programmgesteuerte elektronische digitale Rechenmaschine
US3340513A (en) * 1964-08-28 1967-09-05 Gen Precision Inc Instruction and operand processing
US3365703A (en) * 1964-10-07 1968-01-23 Bell Telephone Labor Inc Data processor with successive utilizations of an indexing result
US3345619A (en) * 1964-10-21 1967-10-03 Sperry Rand Corp Data processing system
US3380025A (en) * 1964-12-04 1968-04-23 Ibm Microprogrammed addressing control system for a digital computer
US3400380A (en) * 1966-03-25 1968-09-03 Burroughs Corp Digital computer having an address controller operation

Also Published As

Publication number Publication date
US3657705A (en) 1972-04-18
GB1320241A (en) 1973-06-13
DE2055784A1 (de) 1971-05-19

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