CA935928A - Partitioning logic operations in a generalized matrix system - Google Patents

Partitioning logic operations in a generalized matrix system

Info

Publication number
CA935928A
CA935928A CA100064A CA100064A CA935928A CA 935928 A CA935928 A CA 935928A CA 100064 A CA100064 A CA 100064A CA 100064 A CA100064 A CA 100064A CA 935928 A CA935928 A CA 935928A
Authority
CA
Canada
Prior art keywords
logic operations
matrix system
partitioning logic
generalized matrix
generalized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA100064A
Other languages
English (en)
Other versions
CA100064S (en
Inventor
Fleisher Harold
D. Winkler Vaughn
Weinberger Arnold
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA935928A publication Critical patent/CA935928A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
CA100064A 1969-12-30 1970-12-08 Partitioning logic operations in a generalized matrix system Expired CA935928A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US88902469A 1969-12-30 1969-12-30

Publications (1)

Publication Number Publication Date
CA935928A true CA935928A (en) 1973-10-23

Family

ID=25394372

Family Applications (1)

Application Number Title Priority Date Filing Date
CA100064A Expired CA935928A (en) 1969-12-30 1970-12-08 Partitioning logic operations in a generalized matrix system

Country Status (7)

Country Link
US (1) US3593317A (ja)
JP (1) JPS5040903B1 (ja)
CA (1) CA935928A (ja)
CH (1) CH512110A (ja)
DE (1) DE2063199C3 (ja)
FR (1) FR2072117B1 (ja)
NL (1) NL171401C (ja)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761902A (en) * 1971-12-30 1973-09-25 Ibm Functional memory using multi-state associative cells
US3760368A (en) * 1972-04-21 1973-09-18 Ibm Vector information shifting array
US3790959A (en) * 1972-06-26 1974-02-05 Burroughs Corp Capacitive read only memory
DE2321200C3 (de) * 1973-04-26 1984-01-26 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur Durchführung logischer, durch Boolesche Gleichungen dargestellter Verknüpfungen
DE2401645C2 (de) * 1974-01-15 1982-09-09 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Vorrichtung zur Abgabe von Steuersignalen an eine Schaltungsanordnung
US3924243A (en) * 1974-08-06 1975-12-02 Ibm Cross-field-partitioning in array logic modules
US4063080A (en) * 1976-06-30 1977-12-13 International Business Machines Corporation Method of propagation delay testing a level sensitive array logic system
US4123669A (en) * 1977-09-08 1978-10-31 International Business Machines Corporation Logical OR circuit for programmed logic arrays
DE2846686C2 (de) * 1978-10-26 1984-07-19 Siemens AG, 1000 Berlin und 8000 München Programmierbares Schaltwerk
US4506341A (en) * 1982-06-10 1985-03-19 International Business Machines Corporation Interlaced programmable logic array having shared elements
US4600846A (en) * 1983-10-06 1986-07-15 Sanders Associates, Inc. Universal logic circuit modules
EP0365733B1 (en) * 1988-10-28 1994-01-05 International Business Machines Corporation Reprogrammable logic fuse based on a 6-device SRAM cell for logic arrays
US5021689A (en) * 1989-01-19 1991-06-04 National Semiconductor Corp. Multiple page programmable logic architecture
US4942319A (en) * 1989-01-19 1990-07-17 National Semiconductor Corp. Multiple page programmable logic architecture
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5055712A (en) * 1990-04-05 1991-10-08 National Semiconductor Corp. Register file with programmable control, decode and/or data manipulation
JP5203594B2 (ja) * 2006-11-07 2013-06-05 株式会社東芝 暗号処理回路及び暗号処理方法
JP4851947B2 (ja) * 2007-01-29 2012-01-11 株式会社東芝 論理回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3212064A (en) * 1961-11-27 1965-10-12 Sperry Rand Corp Matrix having thin magnetic film logical gates for transferring signals from plural input means to plural output means
US3210737A (en) * 1962-01-29 1965-10-05 Sylvania Electric Prod Electronic data processing
US3274556A (en) * 1962-07-10 1966-09-20 Ibm Large scale shifter
US3311896A (en) * 1964-04-03 1967-03-28 Ibm Data shifting apparatus
US3383661A (en) * 1964-09-30 1968-05-14 Bell Telephone Labor Inc Arrangement for generating permutations
GB1101851A (en) * 1965-01-20 1968-01-31 Ncr Co Generalized logic circuitry
US3371320A (en) * 1965-03-12 1968-02-27 Sperry Rand Corp Multipurpose matrix

Also Published As

Publication number Publication date
FR2072117A1 (ja) 1971-09-24
DE2063199A1 (de) 1971-07-08
FR2072117B1 (ja) 1973-02-02
JPS5040903B1 (ja) 1975-12-27
DE2063199B2 (de) 1974-02-28
DE2063199C3 (de) 1974-09-26
NL171401B (nl) 1982-10-18
NL7018172A (ja) 1971-07-02
NL171401C (nl) 1983-03-16
CH512110A (de) 1971-08-31
US3593317A (en) 1971-07-13

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