CA927523A - Method for making transistors including base sheet resistivity determining step - Google Patents

Method for making transistors including base sheet resistivity determining step

Info

Publication number
CA927523A
CA927523A CA123159A CA123159A CA927523A CA 927523 A CA927523 A CA 927523A CA 123159 A CA123159 A CA 123159A CA 123159 A CA123159 A CA 123159A CA 927523 A CA927523 A CA 927523A
Authority
CA
Canada
Prior art keywords
base sheet
determining step
including base
transistors including
sheet resistivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA123159A
Other languages
English (en)
Other versions
CA123159S (en
Inventor
G. Einthoven Willem
S. Jetter Evelyn
Carl F. Wheatley, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Application granted granted Critical
Publication of CA927523A publication Critical patent/CA927523A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2607Circuits therefor
    • G01R31/2637Circuits therefor for testing other individual devices
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2644Adaptations of individual semiconductor devices to facilitate the testing thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004Base region of bipolar transistors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/162Testing steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Bipolar Transistors (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
CA123159A 1971-01-26 1971-09-17 Method for making transistors including base sheet resistivity determining step Expired CA927523A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10978371A 1971-01-26 1971-01-26

Publications (1)

Publication Number Publication Date
CA927523A true CA927523A (en) 1973-05-29

Family

ID=22329546

Family Applications (1)

Application Number Title Priority Date Filing Date
CA123159A Expired CA927523A (en) 1971-01-26 1971-09-17 Method for making transistors including base sheet resistivity determining step

Country Status (11)

Country Link
US (1) US3676229A (de)
JP (1) JPS5145476B1 (de)
AU (1) AU463388B2 (de)
BE (1) BE778430A (de)
CA (1) CA927523A (de)
DE (1) DE2201833C3 (de)
FR (1) FR2123285B1 (de)
GB (1) GB1344395A (de)
NL (1) NL7200985A (de)
SE (1) SE381776B (de)
YU (1) YU41806B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3895977A (en) * 1973-12-20 1975-07-22 Harris Corp Method of fabricating a bipolar transistor
US4079505A (en) * 1974-03-14 1978-03-21 Fujitsu Limited Method for manufacturing a transistor
FR2280203A1 (fr) * 1974-07-26 1976-02-20 Thomson Csf Procede d'ajustement de tension de seuil de transistors a effet de champ
US3999217A (en) * 1975-02-26 1976-12-21 Rca Corporation Semiconductor device having parallel path for current flow
DE2656420A1 (de) * 1976-12-13 1978-06-15 Siemens Ag Transistor mit innerer gegenkopplung
DE2949590A1 (de) * 1979-12-10 1981-06-11 Robert Bosch do Brasil, Campinas Verfahren zur vormessung von hochstromparametern bei leistungstransistoren und hierzu geeigneter leistungstransistor
DE3138340C2 (de) * 1981-09-26 1987-01-29 Telefunken electronic GmbH, 7100 Heilbronn Verfahren zum Herstellen von mehreren planaren Bauelementen
US5217907A (en) * 1992-01-28 1993-06-08 National Semiconductor Corporation Array spreading resistance probe (ASRP) method for profile extraction from semiconductor chips of cellular construction
US5451529A (en) * 1994-07-05 1995-09-19 Taiwan Semiconductor Manufacturing Company Method of making a real time ion implantation metal silicide monitor
US9093335B2 (en) * 2012-11-29 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Calculating carrier concentrations in semiconductor Fins using probed resistance
DE102014211352B4 (de) * 2014-06-13 2021-08-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Schichtsystem und Verfahren zur Bestimmung des spezifischen Widerstandes

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3335340A (en) * 1964-02-24 1967-08-08 Ibm Combined transistor and testing structures and fabrication thereof

Also Published As

Publication number Publication date
SE381776B (sv) 1975-12-15
YU41806B (en) 1988-02-29
YU11572A (en) 1984-02-29
FR2123285A1 (de) 1972-09-08
BE778430A (fr) 1972-05-16
AU3793872A (en) 1973-07-19
DE2201833C3 (de) 1978-06-29
GB1344395A (en) 1974-01-23
FR2123285B1 (de) 1977-04-22
DE2201833A1 (de) 1972-08-24
DE2201833B2 (de) 1977-11-10
US3676229A (en) 1972-07-11
JPS5145476B1 (de) 1976-12-03
AU463388B2 (en) 1975-07-24
NL7200985A (de) 1972-07-28

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