CA2683166A1 - Method and system for reducing triggering latency in universal serial bus data acquisition - Google Patents

Method and system for reducing triggering latency in universal serial bus data acquisition Download PDF

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Publication number
CA2683166A1
CA2683166A1 CA002683166A CA2683166A CA2683166A1 CA 2683166 A1 CA2683166 A1 CA 2683166A1 CA 002683166 A CA002683166 A CA 002683166A CA 2683166 A CA2683166 A CA 2683166A CA 2683166 A1 CA2683166 A1 CA 2683166A1
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CA
Canada
Prior art keywords
usb
devices
time
receipt
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002683166A
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English (en)
French (fr)
Inventor
Peter Foster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chronologic Pty Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2683166A1 publication Critical patent/CA2683166A1/en
Abandoned legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
CA002683166A 2007-05-15 2008-05-12 Method and system for reducing triggering latency in universal serial bus data acquisition Abandoned CA2683166A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US93813607P 2007-05-15 2007-05-15
US60/938,136 2007-05-15
PCT/AU2008/000662 WO2008138052A1 (en) 2007-05-15 2008-05-12 Method and system for reducing triggering latency in universal serial bus data acquisition

Publications (1)

Publication Number Publication Date
CA2683166A1 true CA2683166A1 (en) 2008-11-20

Family

ID=40001589

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002683166A Abandoned CA2683166A1 (en) 2007-05-15 2008-05-12 Method and system for reducing triggering latency in universal serial bus data acquisition

Country Status (8)

Country Link
US (1) US8688874B2 (ja)
EP (1) EP2147382B1 (ja)
JP (1) JP5210377B2 (ja)
CN (1) CN101689209B (ja)
AU (1) AU2008251023B2 (ja)
CA (1) CA2683166A1 (ja)
HK (1) HK1141108A1 (ja)
WO (1) WO2008138052A1 (ja)

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CN108195533B (zh) * 2017-12-14 2019-07-19 北京理工大学 一种精确定位数据采集时刻的系统和方法
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Also Published As

Publication number Publication date
EP2147382A4 (en) 2011-03-23
CN101689209A (zh) 2010-03-31
US8688874B2 (en) 2014-04-01
JP2010527080A (ja) 2010-08-05
JP5210377B2 (ja) 2013-06-12
EP2147382B1 (en) 2012-10-31
AU2008251023B2 (en) 2013-02-07
AU2008251023A1 (en) 2008-11-20
CN101689209B (zh) 2013-02-06
EP2147382A1 (en) 2010-01-27
WO2008138052A1 (en) 2008-11-20
HK1141108A1 (en) 2010-10-29
US20100057955A1 (en) 2010-03-04

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Legal Events

Date Code Title Description
EEER Examination request

Effective date: 20130226

FZDE Discontinued

Effective date: 20160512