CA2458199A1 - Procede permettant la conversion de programmes destines a des architectures reconfigurables - Google Patents

Procede permettant la conversion de programmes destines a des architectures reconfigurables Download PDF

Info

Publication number
CA2458199A1
CA2458199A1 CA002458199A CA2458199A CA2458199A1 CA 2458199 A1 CA2458199 A1 CA 2458199A1 CA 002458199 A CA002458199 A CA 002458199A CA 2458199 A CA2458199 A CA 2458199A CA 2458199 A1 CA2458199 A1 CA 2458199A1
Authority
CA
Canada
Prior art keywords
data
memories
recited
configuration
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002458199A
Other languages
English (en)
Inventor
Martin Vorbach
Frank May
Armin Nueckel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
PACT XPP Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/967,847 external-priority patent/US7210129B2/en
Priority claimed from PCT/EP2002/002398 external-priority patent/WO2002071248A2/fr
Application filed by PACT XPP Technologies AG filed Critical PACT XPP Technologies AG
Publication of CA2458199A1 publication Critical patent/CA2458199A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/447—Target code generation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Stored Programmes (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

La présente invention concerne le traitement de données avec des champs multidimensionnels, et les codes de langage de programmation évolué qu'il est avantageux d'utiliser à cet effet.
CA002458199A 2001-08-16 2002-08-16 Procede permettant la conversion de programmes destines a des architectures reconfigurables Abandoned CA2458199A1 (fr)

Applications Claiming Priority (19)

Application Number Priority Date Filing Date Title
DE10139170 2001-08-16
DE10139170.6 2001-08-16
DE10142903.7 2001-09-03
DE10142903 2001-09-03
DE10144732 2001-09-11
DE10144732.9 2001-09-11
DE10145792 2001-09-17
DE10145792.8 2001-09-17
US09/967,847 2001-09-28
US09/967,847 US7210129B2 (en) 2001-08-16 2001-09-28 Method for translating programs for reconfigurable architectures
DE10154260.7 2001-11-05
DE10154260 2001-11-05
DE10207225.6 2002-02-21
DE10207225 2002-02-21
PCT/EP2002/002398 WO2002071248A2 (fr) 2001-03-05 2002-03-05 Procedes et dispositifs pour mettre en forme et/ou traiter des donnees
EPPCT/EP02/02398 2002-03-05
EPPCT/EP02/09131 2002-08-15
EP0209131 2002-08-15
PCT/EP2002/010065 WO2003017095A2 (fr) 2001-08-16 2002-08-16 Procede permettant la conversion de programmes destines a des architectures reconfigurables

Publications (1)

Publication Number Publication Date
CA2458199A1 true CA2458199A1 (fr) 2003-02-27

Family

ID=41210636

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002458199A Abandoned CA2458199A1 (fr) 2001-08-16 2002-08-16 Procede permettant la conversion de programmes destines a des architectures reconfigurables

Country Status (4)

Country Link
JP (1) JP2005508029A (fr)
AU (1) AU2002340879A1 (fr)
CA (1) CA2458199A1 (fr)
WO (1) WO2003017095A2 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
AT501479B8 (de) * 2003-12-17 2007-02-15 On Demand Informationstechnolo Digitale rechnereinrichtung
DE102005005073B4 (de) * 2004-02-13 2009-05-07 Siemens Ag Rechnereinrichtung mit rekonfigurierbarer Architektur zur parallelen Berechnung beliebiger Algorithmen
JP5141151B2 (ja) * 2007-09-20 2013-02-13 富士通セミコンダクター株式会社 動的再構成回路およびループ処理制御方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic

Also Published As

Publication number Publication date
WO2003017095A3 (fr) 2004-10-28
WO2003017095A2 (fr) 2003-02-27
AU2002340879A1 (en) 2003-03-03
JP2005508029A (ja) 2005-03-24

Similar Documents

Publication Publication Date Title
US8869121B2 (en) Method for the translation of programs for reconfigurable architectures
US7657877B2 (en) Method for processing data
US7210129B2 (en) Method for translating programs for reconfigurable architectures
US10031733B2 (en) Method for processing data
Callahan et al. Instruction-level parallelism for reconfigurable computing
US20150074352A1 (en) Multiprocessor Having Segmented Cache Memory
US20030046607A1 (en) Method for debugging reconfigurable architectures
US20090113404A1 (en) Optimum code generation method and compiler device for multiprocessor
JP2003505753A (ja) セル構造におけるシーケンス分割方法
US20170364338A1 (en) Tool-level and hardware-level code optimization and respective hardware modification
CA2458199A1 (fr) Procede permettant la conversion de programmes destines a des architectures reconfigurables
Zimmermann et al. An approach to machine-independent parallel programming
US8549466B2 (en) Tiered register allocation
Keßler et al. Integrating synchronous and asynchronous paradigms: The Fork95 parallel programming language
US20110161977A1 (en) Method and device for data processing
US20140143509A1 (en) Method and device for data processing
Mignolet et al. Embedded multiprocessor systems-on-chip programming
Haug et al. Reconfigurable hardware as shared resource in multipurpose computers
Brossard et al. A model for programming data-intensive applications on fpgas: A genomics case study
Su et al. Array prefetching for irregular array accesses in titanium
Andersson et al. Automatic local memory architecture generation for data reuse in custom data paths
Saghir et al. A comparison of traditional and VLIW DSP architecture for compiled DSP applications
Drieseberg et al. C to Cellular Automata and Execution on CPU, GPU and FPGA.
Willis et al. Use of embedded scheduling to compile VHDL for effective parallel simulation
Scipione Toward portable HPC applications with SYCL: a molecular docking case study

Legal Events

Date Code Title Description
FZDE Dead