CA2402257A1 - Enhanced turbo product codes - Google Patents
Enhanced turbo product codes Download PDFInfo
- Publication number
- CA2402257A1 CA2402257A1 CA002402257A CA2402257A CA2402257A1 CA 2402257 A1 CA2402257 A1 CA 2402257A1 CA 002402257 A CA002402257 A CA 002402257A CA 2402257 A CA2402257 A CA 2402257A CA 2402257 A1 CA2402257 A1 CA 2402257A1
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- CA
- Canada
- Prior art keywords
- block
- encoded
- encoder
- parity
- data
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
- H03M13/296—Particular turbo code structure
- H03M13/2963—Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2909—Product codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2918—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes with error correction codes in three or more dimensions, e.g. 3-dimensional product code where the bits are arranged in a cube
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2921—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes wherein error correction coding involves a diagonal direction
Abstract
A hyper encoder module encodes a block of data having a plurality of sub-blocks. Each sub-block includes a plurality of systematic block code codewords. A parity sub-block is added to the block.
The parity sub-block is a first sub-block rotated by a predetermined number of bits. Each subsequent sub-block in the n-dimensional block is rotated by an appropriate number of bits and bit-wise XORed. An encoder method and apparatus which includes the hyper encoder module receives the block of data. A row of the block is immediately output and encoded by a first module according to a first encoding scheme. A column is encoded by a second module according to a second encoding scheme. A second set of encoded data is generated, iteratively updated and output by the second module. The hyper encoder module hyper-diagonally encodes the information bits as described above and then output.
The parity sub-block is a first sub-block rotated by a predetermined number of bits. Each subsequent sub-block in the n-dimensional block is rotated by an appropriate number of bits and bit-wise XORed. An encoder method and apparatus which includes the hyper encoder module receives the block of data. A row of the block is immediately output and encoded by a first module according to a first encoding scheme. A column is encoded by a second module according to a second encoding scheme. A second set of encoded data is generated, iteratively updated and output by the second module. The hyper encoder module hyper-diagonally encodes the information bits as described above and then output.
Claims (40)
1. A method of encoding a block of data having n dimensions, wherein the block contains a plurality of systematic block code codewords, the method comprising the steps of:
a. performing a parity calculation along a hyper diagonal in the block, wherein a parity result for the parity calculation is generated; and b. adding the parity result to the block of data.
a. performing a parity calculation along a hyper diagonal in the block, wherein a parity result for the parity calculation is generated; and b. adding the parity result to the block of data.
2. The method according to claim 1 further comprising the step of storing the parity result in a parity array, wherein the parity array is added to the block of data as a separate array.
3. The method according to claim 2 further comprising the step of rotating the parity array such that the parity result stared in the parity array is substantially aligned with the hyper diagonal along which the parity result was calculated.
4. The method according to claim 2 further comprising the step of initializing the parity array such that the parity bits are set to zero before the step of performing the parity calculation along the hyper diagonal is executed.
5. The method according to claim 1 further comprising the step of outputting the encoded block of data when the parity result is aligned substantially with the hyper diagonal.
6. The method according to claim 1 wherein the block of data is three dimensional.
7. The method according to claim 6 wherein the parity result for the parity calculation is stored in a parity plane, wherein the parity plane is added to the block of data as a separate plane.
8. A method of encoding a n-dimensional block of data having a plurality of (n-1) dimensional sub-blocks, wherein each sub-block includes a plurality of systematic block code codewords, wherein a parity sub-block is added to the block of data, the parity sub-block having a plurality of parity bits, the method comprising the steps of:
a. causing the parity sub-block to be equal to a first sub-block rotated by a predetermined number of bits; and b. for each subsequent sub-block parallel to the first sub-block in the n-dimensional block, bit-wise XORing that parallel sub-block with the parity sub-block, wherein the parity sub-block is rotated by an appropriate number of bits.
a. causing the parity sub-block to be equal to a first sub-block rotated by a predetermined number of bits; and b. for each subsequent sub-block parallel to the first sub-block in the n-dimensional block, bit-wise XORing that parallel sub-block with the parity sub-block, wherein the parity sub-block is rotated by an appropriate number of bits.
9. The method according to claim 8 further comprising the step of initializing the parity sub-block such that each parity bit is zero, wherein the step of initializing occurs before the parity sub-block is caused to be equal to the first plane.
10. The method according to claim 8 further comprising the step of outputting the encoded block of data.
11. A method of encoding a block of data having n-dimensions received from an input source, the block containing a plurality of information bits, the method comprising the steps of:
a. receiving a row of the block and immediately outputting the row;
b. encoding the information bits in the row, wherein a first set of encoded data is generated according to a first encoding scheme;
c. outputting the first set of encoded data;
d. encoding the information bits in a column according to a second encoding scheme, wherein a second set of encoded data is generated and iteratively updated according to the information bits in the row;
e. hyper-diagonally encoding the information bits in the block according to a parity encoding scheme, wherein a hyper set of encoded data is generated according to the information bits in the row and column and the first and second sets of encoded data;
f. outputting the updated second set of encoded data after all the information bits and all subsequent first sets of encoded data are outputted; and g. outputting the hyper set of encoded data.
a. receiving a row of the block and immediately outputting the row;
b. encoding the information bits in the row, wherein a first set of encoded data is generated according to a first encoding scheme;
c. outputting the first set of encoded data;
d. encoding the information bits in a column according to a second encoding scheme, wherein a second set of encoded data is generated and iteratively updated according to the information bits in the row;
e. hyper-diagonally encoding the information bits in the block according to a parity encoding scheme, wherein a hyper set of encoded data is generated according to the information bits in the row and column and the first and second sets of encoded data;
f. outputting the updated second set of encoded data after all the information bits and all subsequent first sets of encoded data are outputted; and g. outputting the hyper set of encoded data.
12. The method according to claim 11 further comprising the step of encoding the second set of encoded data according to the first encoding scheme on a row by row basis such that all information bits received are encoded.
13. The method according to claim 11 further comprising the step of encoding the second set of encoded data according to the second encoding scheme on a row by row basis such that all information bits received are encoded.
14. The method according to claim 11 wherein the block of data is three dimensional, the block of data including a plane of encoded bits, wherein the plane is orthogonal to the row and the column.
15. The method according to claim 14 further comprising the steps of:
a. encoding the information bits in the plane according to a third encoding scheme, wherein a third set of encoded data is generated and iteratively updated corresponding to the information bits in the row; and b. outputting the third set encoded data after all subsequent second sets of encoded data are outputted.
a. encoding the information bits in the plane according to a third encoding scheme, wherein a third set of encoded data is generated and iteratively updated corresponding to the information bits in the row; and b. outputting the third set encoded data after all subsequent second sets of encoded data are outputted.
16. The method according to claim 14 wherein the hyper parity array is a hyper parity plane.
17 17. The method according to claim 11 wherein the first set of encoded data is stored in a row encode storage array, wherein the row encode storage array includes a plurality of row array bits.
18. The method according to claim 17 further comprising the step of resetting the row encode storage array such that all row array bits are set to zero, wherein the step of resetting is executed after the first set of encoded data is outputted.
19. The method according to claim 11 wherein the second set of encoded data is stored in a column encode storage array.
20. The method according to claim 11 wherein the hyper set of encoded data is stored in a hyper parity array, wherein the hyper parity array includes a plurality of parity array bits.
21. The method according to claim 20 wherein the step of hyper-diagonally encoding further comprises:
a. updating the hyper parity array by iteratively encoding the parity array for the information bits and the first set and the second set of encoded data for each row; and b. rotating the hyper parity array by a predetermined number of bits.
a. updating the hyper parity array by iteratively encoding the parity array for the information bits and the first set and the second set of encoded data for each row; and b. rotating the hyper parity array by a predetermined number of bits.
22. The method according to claim 20 further comprising the step of initializing the hyper parity array such that all parity array bits are set to zero, wherein the step of initializing is executed before the any information bits are encoded.
23. An encoder comprising: a datapath module for encoding a block of data having a plurality of systematic block code codewords, wherein each codeword includes a plurality of information bits and a plurality of error correction bits, wherein the datapath module hyper-diagonally encodes a string of the block code codewords and performs a parity calculation on the string, whereby a parity result for each string is generated.
24. The encoder according to claim 23 wherein the parity result for each string is stored in a parity array.
25. The encoder according to claim 23 further comprising an input module for receiving the block of data.
26. The encoder according to claim 23 further comprising an output module for outputting the encoded block of data.
27. The encoder according to claim 23 wherein the datapath module further comprises:
a. a first encoder module for encoding a plurality of rows from the block of data, wherein the first encoder module adds the error correction bits to the rows; and b. a second encoder module for encoding a plurality of columns from the block of data, wherein the second encoder module adds the error correction bits to the columns such that an encoded block of data is formed.
a. a first encoder module for encoding a plurality of rows from the block of data, wherein the first encoder module adds the error correction bits to the rows; and b. a second encoder module for encoding a plurality of columns from the block of data, wherein the second encoder module adds the error correction bits to the columns such that an encoded block of data is formed.
28. The encoder according to claim 27 further comprising: an output multiplexer coupled to all the encoder modules for outputting the encoded block of data.
29. The encoder according to claim 27 wherein the datapath module further comprises a third encoder module for encoding a plurality of planes from the block of data, wherein the third encoder adds the error correction bits to the planes.
30. An encoder for encoding a block of data having a plurality of information bits, wherein the encoder outputs the information bits immediately after receiving the information bits, the encoder comprising:
a. a first encoder module for encoding the information bits in a row of the block, wherein the first encoder generates a set of encoded row bits;
b. a second encoder module for encoding the information bits in a column of the block, wherein the second encoder module generates a set of encoded column bits according to the information bits in each row, wherein the second encoder updates the encoded column bits for each row encoded by the first encoder; and c. a hyper encoder module for hyper-diagonally encoding all information bits and all encoded bits diagonally along the block, wherein the hyper encoder generates a set of parity results, whereby each parity result corresponds to a diagonal of the encoded bits.
a. a first encoder module for encoding the information bits in a row of the block, wherein the first encoder generates a set of encoded row bits;
b. a second encoder module for encoding the information bits in a column of the block, wherein the second encoder module generates a set of encoded column bits according to the information bits in each row, wherein the second encoder updates the encoded column bits for each row encoded by the first encoder; and c. a hyper encoder module for hyper-diagonally encoding all information bits and all encoded bits diagonally along the block, wherein the hyper encoder generates a set of parity results, whereby each parity result corresponds to a diagonal of the encoded bits.
31. The encoder according to claim 30 wherein the hyper encoder rotates the parity array such that each parity result is aligned with the corresponding diagonal.
32. The encoder according to claim 30 further comprising a third encoder module for encoding the information bits in a plane of the block, wherein the third encoder module generates a set of encoded plane bits according to the information bits in each row and column, wherein the third encoder updates the encoded plane bits according to each set of encoded row and column bits.
33. The encoder according to claim 30 wherein the first encoder module outputs the set of encoded row bits.
34. The encoder according to claim 33 wherein the second encoder module outputs the set of encoded column bits after all sets of encoded row bits are output.
35. The encoder according to claim 34 wherein the hyper encoder module outputs the set parity results after all encoded row bits and encoded column bits are outputted.
36. An encoder for encoding a block of data into an encoded block of data, wherein the block of data having a plurality of information bits arranged in a plurality of rows and columns, the encoder comprising:
a. means for receiving the block of data, wherein the information bits received are immediately output by an output means;
b. first means for encoding each row according to a first encoding scheme, wherein the first means generates a row encoding result for each row encoded by the first encoding scheme;
c. second means for encoding each column according to a second encoding scheme, wherein the second means generates a column encoding result for each column encoded by the second encoded scheme, wherein the column encoding result is iteratively updated for each row encoded by the first means; and d. means for hyper-diagonally encoding along the encoded block of data, the means for hyper-diagonally encoding generating a hyper parity result for each corresponding diagonal in the encoded block of data.
a. means for receiving the block of data, wherein the information bits received are immediately output by an output means;
b. first means for encoding each row according to a first encoding scheme, wherein the first means generates a row encoding result for each row encoded by the first encoding scheme;
c. second means for encoding each column according to a second encoding scheme, wherein the second means generates a column encoding result for each column encoded by the second encoded scheme, wherein the column encoding result is iteratively updated for each row encoded by the first means; and d. means for hyper-diagonally encoding along the encoded block of data, the means for hyper-diagonally encoding generating a hyper parity result for each corresponding diagonal in the encoded block of data.
37. An encoder for encoding a block of data into an encoded block of data, the block of data having a plurality of information bits, wherein the encoder outputs the information bits immediately after receiving the information bits, the encoder comprising:
a. a first encoder module for encoding the information bits in a row of the block, wherein the first encoder generates a set of encoded row bits; and b. a second encoder module for encoding the information bits in a column of the block, wherein the second encoder module generates a set of encoded column bits according to the information bits in each row, wherein the second encoder updates the encoded column bits for each row encoded by the first encoder.
a. a first encoder module for encoding the information bits in a row of the block, wherein the first encoder generates a set of encoded row bits; and b. a second encoder module for encoding the information bits in a column of the block, wherein the second encoder module generates a set of encoded column bits according to the information bits in each row, wherein the second encoder updates the encoded column bits for each row encoded by the first encoder.
38. The encoder according to claim 37 further comprising a hyper encoder module for hyper-diagonally encoding along the encoded block of data, wherein the hyper encoder generates a set of parity results, each parity result corresponding to each diagonal encoded.
39. The encoder according to claim 38 wherein the hyper encoder module adds the set of parity results to the encoded block of data as a parity array.
40. The encoder according to claim 37 further comprising a third encoder module for encoding the information bits in a plane of the block, wherein the third encoder module generates a set of encoded plane bits according to the information bits in each row and column, wherein the third encoder updates the encoded plane bits for each row encoded by the first encoder and each column encoded by the second encoder.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US18934500P | 2000-03-14 | 2000-03-14 | |
| US60/189,345 | 2000-03-14 | ||
| PCT/US2001/008101 WO2001069797A2 (en) | 2000-03-14 | 2001-03-14 | Enhanced turbo product codes |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2402257A1 true CA2402257A1 (en) | 2001-09-20 |
| CA2402257C CA2402257C (en) | 2010-04-13 |
Family
ID=22696908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2402257A Expired - Fee Related CA2402257C (en) | 2000-03-14 | 2001-03-14 | Enhanced turbo product codes |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1273095A2 (en) |
| JP (1) | JP2003527029A (en) |
| AU (1) | AU2001250837A1 (en) |
| CA (1) | CA2402257C (en) |
| WO (1) | WO2001069797A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117650870A (en) * | 2023-12-06 | 2024-03-05 | 北京荷智科技有限公司 | Communication method, system, equipment and medium based on longitudinal coding error correction |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5024819A (en) * | 1973-07-07 | 1975-03-17 | ||
| JPS61147619A (en) * | 1984-12-21 | 1986-07-05 | Sony Corp | Error correction system |
| US4796260A (en) * | 1987-03-30 | 1989-01-03 | Scs Telecom, Inc. | Schilling-Manela forward error correction and detection code method and apparatus |
| EP0519669A3 (en) * | 1991-06-21 | 1994-07-06 | Ibm | Encoding and rebuilding data for a dasd array |
| JP2905368B2 (en) * | 1993-08-10 | 1999-06-14 | 富士通株式会社 | Error detection and correction method |
-
2001
- 2001-03-14 JP JP2001567139A patent/JP2003527029A/en active Pending
- 2001-03-14 EP EP01924156A patent/EP1273095A2/en not_active Withdrawn
- 2001-03-14 AU AU2001250837A patent/AU2001250837A1/en not_active Abandoned
- 2001-03-14 CA CA2402257A patent/CA2402257C/en not_active Expired - Fee Related
- 2001-03-14 WO PCT/US2001/008101 patent/WO2001069797A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001069797A3 (en) | 2002-02-28 |
| AU2001250837A1 (en) | 2001-09-24 |
| JP2003527029A (en) | 2003-09-09 |
| CA2402257C (en) | 2010-04-13 |
| EP1273095A2 (en) | 2003-01-08 |
| WO2001069797A2 (en) | 2001-09-20 |
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| Date | Code | Title | Description |
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| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20190314 |