CA2395645A1 - Processeur bimodal - Google Patents

Processeur bimodal Download PDF

Info

Publication number
CA2395645A1
CA2395645A1 CA002395645A CA2395645A CA2395645A1 CA 2395645 A1 CA2395645 A1 CA 2395645A1 CA 002395645 A CA002395645 A CA 002395645A CA 2395645 A CA2395645 A CA 2395645A CA 2395645 A1 CA2395645 A1 CA 2395645A1
Authority
CA
Canada
Prior art keywords
processor
memory
mode
circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002395645A
Other languages
English (en)
Inventor
Brant Candelore
Eric J. Sprunk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2395645A1 publication Critical patent/CA2395645A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2105—Dual mode as a secondary aspect

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Storage Device Security (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

Circuit de traitement multimodal, tel qu'un processeur bimodal (5), fonctionnant selon au moins un premier et un deuxième modes en fonction d'un commutateur (10). Quand un mode est actif, un transfert de données s'effectue entre le processeur et une mémoire respective. Ceci permet d'exécuter au niveau du processeur des instructions provenant de la mémoire et de mémoriser les résultats dans la mémoire respective. Une première et une deuxième mémoires (14, 54) peuvent, par exemple, être associées au premier et au deuxième modes (10, 50) respectifs. Ces mémoires sont séparées et aucun transfert de données ne peut s'effectuer directement entre les mémoires ou par l'intermédiaire du processeur. Le premier mode (10) peut être un mode sécurisé servant à exécuter des opérations de traitement sécurisées, telles qu'un accès conditionnel à des services de programmation de télévision au niveau d'un terminal d'abonné placé sur la télévision. Le deuxième mode (50) peut être un mode non sécurisé, afin, par exemple, d'exécuter toute autre application au niveau du terminal, par exemple, un guide de programme, des achats informatisés, etc. Dans un mode de réalisation, un bus de données sert à effectuer le transfert de données multiplexé dans le temps entre le processeur et les mémoires respectives. Un autre mode de réalisation concerne la commutation de registres internes individuels et d'éléments externes, tels que des verrous d'adresses et de données.
CA002395645A 1999-12-23 2000-12-19 Processeur bimodal Abandoned CA2395645A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US47175499A 1999-12-23 1999-12-23
US09/471,754 1999-12-23
PCT/US2000/034458 WO2001046800A2 (fr) 1999-12-23 2000-12-19 Processeur bimodal

Publications (1)

Publication Number Publication Date
CA2395645A1 true CA2395645A1 (fr) 2001-06-28

Family

ID=23872866

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002395645A Abandoned CA2395645A1 (fr) 1999-12-23 2000-12-19 Processeur bimodal

Country Status (9)

Country Link
EP (1) EP1240583A2 (fr)
JP (1) JP2003518287A (fr)
KR (1) KR20020091061A (fr)
CN (1) CN1425157A (fr)
AU (1) AU2278601A (fr)
CA (1) CA2395645A1 (fr)
MX (1) MXPA02006214A (fr)
TW (1) TW541466B (fr)
WO (1) WO2001046800A2 (fr)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1331539B1 (fr) * 2002-01-16 2016-09-28 Texas Instruments France Mode protégé pour procésseurs permettre l'utilisation d'unités de gestion de mémoire et d'interruptions
AU2003278342A1 (en) * 2002-11-18 2004-06-15 Arm Limited Security mode switching via an exception vector
GB2396712B (en) 2002-11-18 2005-12-07 Advanced Risc Mach Ltd Handling multiple interrupts in a data processing system utilising multiple operating systems
US9158574B2 (en) 2002-11-18 2015-10-13 Arm Limited Handling interrupts in data processing
GB0226906D0 (en) * 2002-11-18 2002-12-24 Advanced Risc Mach Ltd Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain
US7370210B2 (en) 2002-11-18 2008-05-06 Arm Limited Apparatus and method for managing processor configuration data
GB2396451B (en) 2002-11-18 2005-12-07 Advanced Risc Mach Ltd Delivering data processing requests to a suspended operating system
GB0226874D0 (en) 2002-11-18 2002-12-24 Advanced Risc Mach Ltd Switching between secure and non-secure processing modes
AU2003276399A1 (en) * 2002-11-18 2004-06-15 Arm Limited Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain
JP4423206B2 (ja) * 2002-11-18 2010-03-03 エイアールエム リミテッド 安全モードと非安全モードとを切り換えるプロセッサ
US7539853B2 (en) 2002-11-18 2009-05-26 Arm Limited Handling interrupts in data processing of data in which only a portion of a function has been processed
US7322042B2 (en) 2003-02-07 2008-01-22 Broadon Communications Corp. Secure and backward-compatible processor and secure software execution thereon
US20100017627A1 (en) 2003-02-07 2010-01-21 Broadon Communications Corp. Ensuring authenticity in a closed content distribution system
JP4317212B2 (ja) 2003-03-20 2009-08-19 アーム・リミテッド 集積回路の処理段における系統的及び確率的誤り検出及び復旧
KR100955285B1 (ko) 2003-03-20 2010-04-30 에이알엠 리미티드 급속 및 저속 데이터 판독 메카니즘을 갖는 메모리 시스템
US8650470B2 (en) 2003-03-20 2014-02-11 Arm Limited Error recovery within integrated circuit
US8185812B2 (en) 2003-03-20 2012-05-22 Arm Limited Single event upset error detection within an integrated circuit
US7278080B2 (en) 2003-03-20 2007-10-02 Arm Limited Error detection and recovery within processing stages of an integrated circuit
KR101037006B1 (ko) * 2003-11-28 2011-05-25 파나소닉 주식회사 데이터 처리장치
KR100677327B1 (ko) * 2004-06-16 2007-02-02 엘지전자 주식회사 이중 운영체제를 가진 이동통신 단말기
FR2872933B1 (fr) * 2004-07-06 2008-01-25 Trusted Logic Sa Procede de partage de temps d'un processeur
KR100710263B1 (ko) * 2005-01-27 2007-04-20 엘지전자 주식회사 멀티모뎀을 구비한 단말기를 이용한 다중작업 처리 방법
FR2884628A1 (fr) * 2005-04-18 2006-10-20 St Microelectronics Sa Procede de traitement d'interruptions non securisees par un processeur operant dans le mode securise, processeur associe.
WO2006120367A1 (fr) * 2005-05-11 2006-11-16 Arm Limited Appareil et procede de traitement de donnees employant plusieurs ensembles de registres
CN101064886B (zh) * 2006-04-28 2012-12-12 朗迅科技公司 无线设备和通过无线设备传送数据的方法
KR100709385B1 (ko) * 2006-07-19 2007-04-24 주식회사 케이 썸 씨앤 에프 컴퓨터 시스템
US7882318B2 (en) * 2006-09-29 2011-02-01 Intel Corporation Tamper protection of software agents operating in a vitual technology environment methods and apparatuses
WO2009031573A1 (fr) * 2007-09-07 2009-03-12 Nec Corporation Appareil de traitement d'informations, procédé de transition d'état de processeur, appareil de commande de transition d'état de processeur, et processeur
US8332660B2 (en) * 2008-01-02 2012-12-11 Arm Limited Providing secure services to a non-secure application
US8522354B2 (en) * 2008-05-24 2013-08-27 Via Technologies, Inc. Microprocessor apparatus for secure on-die real-time clock
US8756391B2 (en) * 2009-05-22 2014-06-17 Raytheon Company Multi-level security computing system
CN101707664B (zh) * 2009-10-30 2013-03-06 深圳创维数字技术股份有限公司 一种机顶盒安全运行方法
CN103631785B (zh) * 2012-08-21 2017-12-29 联想(北京)有限公司 一种电子设备及应用于电子设备的模式切换方法
CN103559460B (zh) * 2013-11-06 2016-06-08 深圳国微技术有限公司 一种条件接收卡cam及数据处理方法
CN104268027B (zh) * 2014-09-22 2017-09-29 北京经纬恒润科技有限公司 嵌入式实时操作系统的故障处理方法和装置
GB2543096A (en) 2015-10-09 2017-04-12 Secure Thingz Ltd Data Processing Device
CN105701420B (zh) * 2016-02-23 2019-05-14 深圳市金立通信设备有限公司 一种用户数据的管理方法及终端
JP7280600B2 (ja) * 2019-04-23 2023-05-24 株式会社エルイーテック プロセッサ
US11569994B2 (en) * 2021-06-24 2023-01-31 Intel Corporation Accelerating multiple post-quantum cryptograhy key encapsulation mechanisms

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0715241B1 (fr) * 1994-10-27 2004-01-14 Mitsubishi Corporation Appareil pour système de gestion de droits d'auteur de données

Also Published As

Publication number Publication date
EP1240583A2 (fr) 2002-09-18
AU2278601A (en) 2001-07-03
WO2001046800A3 (fr) 2002-07-25
TW541466B (en) 2003-07-11
MXPA02006214A (es) 2003-01-28
JP2003518287A (ja) 2003-06-03
CN1425157A (zh) 2003-06-18
KR20020091061A (ko) 2002-12-05
WO2001046800A2 (fr) 2001-06-28

Similar Documents

Publication Publication Date Title
CA2395645A1 (fr) Processeur bimodal
US6587937B1 (en) Multiple virtual machine system with efficient cache memory design
US7603540B2 (en) Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration
US9459874B2 (en) Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
US6356960B1 (en) Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port
US7797496B2 (en) Multiprocessor system having a shared tightly coupled memory and method for communication between a plurality of processors
US6314515B1 (en) Resetting multiple processors in a computer system
US4779187A (en) Method and operating system for executing programs in a multi-mode microprocessor
CN100578456C (zh) 信息处理装置、进程控制方法
US8850098B2 (en) Direct memory access (DMA) address translation between peer input/output (I/O) devices
US20180246826A1 (en) Aggregation of interrupts using event queues
US8332614B2 (en) System, method and computer program product for providing a programmable quiesce filtering register
US9396142B2 (en) Virtualizing input/output interrupts
JP2009296195A (ja) 複数のｃｐｕコアを備えたｆｐｇａを用いた暗号装置
GB2404266A (en) Simultaneous multi-thread processing
EP0840223B1 (fr) Micro-ordinateur capable d'accéder à une mémoire externe
JPH05257808A (ja) マイクロプロセッサ及びその動作変換方法
US6697931B1 (en) System and method for communicating information to and from a single chip computer system through an external communication port with translation circuitry
US20010007114A1 (en) Control apparatus and control method
EP0840221A1 (fr) Micro-ordinateur à bus de paquets
Attanasio Virtual Control Storage-curity measures in VM/370
Sukhwani et al. Extensible on-chip peripherals
EP1673693B1 (fr) Systèmes d'exploitation
GB2286067A (en) A processor system
GB2454817A (en) Interrupt handling in a logically partitioned system by changing the interrupt status values in an array for only one partition at a time.

Legal Events

Date Code Title Description
EEER Examination request
FZDE Discontinued
FZDE Discontinued

Effective date: 20071219