CA2387110C

CA2387110C - Packet video signal inverse transport processor memory address circuitry

Info

Publication number: CA2387110C
Application number: CA002387110A
Authority: CA
Inventors: Kevin Elliott Bridgewater; Michael Scott Deiss
Original assignee: Thomson Consumer Electronics Inc
Current assignee: Technicolor USA Inc
Priority date: 1994-04-22
Filing date: 1995-04-06
Publication date: 2008-02-19
Anticipated expiration: 2015-04-06
Also published as: CA2387110A1

Abstract

An inverse transport processor system for a TDM packet signal TV receiver includes apparatus for selectively extracting desired payloads of program component data and coupling this data to a common buffer memory data input port. A microprocessor associated with the system also couples data to the common buffer memory data input port. The respective component payloads and data generated by the microprocessor are stored in respective blocks of the common buffer memory in response to associated memory address which are applied to a memory address input port by an address multiplexer. A decryption device is included to decrypt payload data according to packet specific decryption keys. In addition a detector is included to detect payloads including entitlement data. Payloads containing entitlement data are directed via the common buffer memory to a smart card which generates the packet specific decryption keys. A memory data output port is coupled to a bus interconnected with the respective program component processors. Responsive to data requests from the respective program component processors, and data write requests from the component payload source, memory access for read and write functions is arbitrated so that no incoming program data is lost, and all component processors are serviced.

Claims

1. Apparatus in an audio/video signal transport processor for processing signal including time division multiplexed packets of program components with respective packets including a payload of component data and a header with a component identifier, SCID, and wherein respective payloads of predetermined components are extracted from respective packets and stored in buffer memory, said apparatus including direct memory access circuits, responsive to detected said identifiers for generating mutually exclusive direct memory access address sequences to write payloads of component data in mutually exclusive blocks of said buffer memory.

2. The apparatus set forth in claim 1, further including:
control apparatus programmed to generate a plurality of N-bit start and end pointers for application to said direct memory access circuits to define said mutually exclusive blocks of buffer memory (N an integer).

3. The apparatus set forth in claim 2, wherein said direct memory access circuits include:
first and second pluralities of registers for storing said plurality of N-bit start pointers and N-bit end pointers respectively; and means for forming write addresses from said N-bit start pointers including an accumulator for incrementing successive write addresses by one unit.

4. The apparatus set forth in claim 1, 'further including circuitry including a comparator for preventing respective ones of the direct memory access circuits from generating addresses outside of the direct memory access circuit's associated mutually exclusive memory block.

5. The apparatus set forth in claim 1, further including a multiplexer for multiplexing addresses from said direct memory access circuits to an address port of said buffer memory.

6. Apparatus in a signal transport processor for processing signal including time division multiplexed packets of program components, wherein respective packets include a payload of program component data and a header including a program component identifier, SCID, and wherein payloads of respective components are stored in mutually exclusive portions of buffer memory, circuitry for addressing said buffer memory comprising;

a source of time division multiplexed packets;

an SCID detector, responsive to respective component identifiers in packet headers for detecting packets having predetermined program components;

a plurality of direct memory access circuits;

control apparatus programmed to condition respective ones of said direct memory access circuits to write payloads of received packets into appropriate said mutually exclusive portions of buffer memory responsive to detected said identifiers.

7. The apparatus set fourth in claim 6 wherein respective ones of said plurality of direct memory access circuits comprises:
a register for storing a start pointer provided by said control apparatus; and a further register for storing a value related to the last address of a respective exclusive portion of said buffer memory.

8. The apparatus set fourth in claim 7 wherein respective ones of said plurality of direct memory access circuits further include a register for storing a current write address and said plurality of direct memory access circuits further include a common incrementing circuit for incrementing respective memory addresses stored in respective said registers for storing a current write address.

9. The apparatus set forth in claim 8 wherein respective ones of said plurality of, direct memory access circuits further comprises a still further register for storing a current read address.

10. The apparatus set forth in claim 9 wherein said plurality of direct memory access circuits includes a further common incrementing circuit for incrementing respective memory addresses stored in respective said registers for storing a current read address.

11. Apparatus in an audio/video signal transport processor for processing signal including time division multiplexed packets of program components with respective packets including a payload of component data and a header with a component identifier, SCID, and wherein respective payloads of predetermined components are extracted from respective packets and stored in buffer memory, said apparatus including multiple allocated direct memory access circuits, responsive to detected said identifiers for generating memory addresses to write payloads of component data in mutually exclusive blocks of said buffer memory.

12. The apparatus set forth in claim 11 further including:

control apparatus programmed to generate a plurality of N-bit start and end pointers for application to said multiple allocated direct memory access circuits to define said mutually exclusive blocks of buffer memory (N an integer).

13. The apparatus set forth in claim 12 wherein said multiple allocated direct memory access circuits includes:

first and second like pluralities of registers for storing said plurality of N-bit start pointers and N-bit end pointers respectively; and means for forming write addresses from said N-bit start pointers including an accumulator for incrementing successive write addresses by one unit.

14. The apparatus set forth in claim 11 further including circuitry including a comparator for preventing respective ones of the multiple allocated direct memory access circuits from generating addresses outside of its associated mutually exclusive memory block.

15. The apparatus set forth in claim 11 further including a multiplexer for multiplexing addresses from said multiple allocated direct memory access circuits to an address port of said buffer memory.