KR970056373A - Cell assembly unit of ATM-MSS - Google Patents

Cell assembly unit of ATM-MSS Download PDF

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Publication number
KR970056373A
KR970056373A KR1019950052874A KR19950052874A KR970056373A KR 970056373 A KR970056373 A KR 970056373A KR 1019950052874 A KR1019950052874 A KR 1019950052874A KR 19950052874 A KR19950052874 A KR 19950052874A KR 970056373 A KR970056373 A KR 970056373A
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KR
South Korea
Prior art keywords
memory
cell assembly
information
address
signal
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KR1019950052874A
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Korean (ko)
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KR0166199B1 (en
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정영기
성승희
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유기범
대우통신 주식회사
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Priority to KR1019950052874A priority Critical patent/KR0166199B1/en
Publication of KR970056373A publication Critical patent/KR970056373A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/107—ATM switching elements using shared medium
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9057—Arrangements for supporting packet reassembly or resequencing

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

본 발명은 ATM-MSS의 셀조립 장치에 관한 것으로, 본 발명의 장치는 CPU에 의해 제1메모리(10)를 억세스하기 위해 제어신호 및 어드레스신호를 생성하여 제1인터페이스부(20); CPU에 제2메모리(30)를 억세스하도록 제어신호 및 어드레스신호를 생성하는 제2인터페이스부(40); 전송부(50)로부터 ATM셀을 입력받아 헤더를 추출하여 상기 제2메모리(30)로부터 읽어온 어드레스정보에 의해 유료부하를 상기 제1메모리(10)에 저장하고 상기 추출된 헤더 및 시작 번지, 바이트개수 정보를 상기 제2메모리(30)에 저장시키는 셀조립 프로세서(60); 상기 셀조립 프로세서(60)가 제1,2메모리(10,30)를 억세스하도록 제어하고, 상기 셀조립 프로세서(60)와 CPU가 동시에 상기1,2메모리(10,30)를 억세스하고자 할 때 중재역할을 하는 제1,2중재부(70,80)로 구성되어 있어, 각 노드 관리 모듈로부터 입력된 셀 정보를 조립하여 패킷으로 묶어 전송함으로써 외부의 장치로 전송할 수 있다는 데 그 효과가 있다.The present invention relates to a cell assembly apparatus of an ATM-MSS, the apparatus of the present invention generates a control signal and an address signal for accessing the first memory (10) by the CPU, the first interface unit 20; A second interface unit 40 generating a control signal and an address signal to access the second memory 30 to the CPU; After receiving the ATM cell from the transmitter 50, the header is extracted, the payload is stored in the first memory 10 by the address information read from the second memory 30, and the extracted header and start address, A cell assembly processor (60) which stores byte count information in the second memory (30); When the cell assembly processor 60 controls the first and second memories 10 and 30 to be accessed, and the cell assembly processor 60 and the CPU want to access the first and second memories 10 and 30 simultaneously. The first and second arbitration units 70 and 80 act as arbitrations, and the cell information input from each node management module can be assembled into a packet and transmitted to an external device.

Description

ATM-Mss의 셀 조립 장치ATM-Mss Cell Assembly Unit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 ATM-MSS의 셀 조립 장치의 블록도.3 is a block diagram of a cell assembly apparatus for ATM-MSS according to the present invention.

제4도는 ATM 셀의 구조를 도시한 포맷도이다.4 is a format diagram showing the structure of an ATM cell.

Claims (1)

패킷 정보를 저장하기 위한 제 1 메모리(10)와 ; CPU의 제어에 의해 상기 제 1 메모리(10)로부터 패킷 정보를 읽어올 수 있도록 제어 신호 및 어드레스 신호를 생성하여 제 1 인터페이스부(20); 어드레스 정보 및 헤더, 시작 번지, 바이트 개수 정보를 저장하기 위한 제 2 메모리(30); CPU의 제어에 의해 상기 어드레스 정보 및 헤더, 시작 번지, 바이트 개수 정보를 상기 제 2 메모리(30)에 저장 또는 읽어올 수 있도록 제어 신호 및 어드레스 신호를 생성하는 제 2 인터페이스부(40) ; 53 바이트의 ATM 셀을 전송받는 전송부(50) ; 상기 전송부(50)로부터 53 바이트의 ATM 셀을 입력받아 5 바이트의 헤더를 추출하여 상기 제 2 메모리(30)로부터 읽어온 어드레스 정보에 의해 48 바이트의 유료 부하를 상기 제 1 메모리(10)에 저장하는 동시에 상기 추출된 헤더 및 정보가 저장되어 있는 상기 제 1 메모리(10)의 시작 번지 및 조립된 바이트의 개수 정보를 상기 제 2 메모리(30)에 저장시킴으로써 CPU가 셀 조립 상황을 파악할 수 있도록 하는 셀 조립 프로세서(60); 상기 셀 조립 프로세서(60)가 패킷 정보를 상기 제 1 메모리(10)에 저장할 수 있도록 제어 신호를 출력하고, 상기 셀 조립 프로세서(60)와 CPU가 동시에 상기 제 1 메모리(10)의 억세스 요구를 하면 신호 충돌을 방지하기 위해 중재 신호를 출력하는 제 1 중재부(70); 및 상기 셀 조립 프로세서(60)가 상기 제 2 메모리(30)로부터 어드레스 정보를 읽어올 수 있도록 제어 신호를 출력하는 동시에 헤더및 시작 번지, 바이트 개수 정보를 상기 제 2 메모리(30)에 저장할 수 있도록 제어 신호를 출력하고, 상기 셀 조립 프로세서(60)와 CPU가 동시에 상기 제 2 메모리(30)의 억세스 요구를 하면 신호 충돌을 방지하기 위해 중재 신호를 출력하는제 2 중재부(80)로 구성되어 있는 것을 특징으로 하는 ATM-MSS의 셀 조립 장치.A first memory 10 for storing packet information; A first interface unit 20 generating a control signal and an address signal to read packet information from the first memory 10 under control of a CPU; A second memory 30 for storing address information and header, start address, and byte count information; A second interface unit (40) for generating a control signal and an address signal to store or read the address information, header, start address, and byte number information in the second memory (30) under control of a CPU; A transmission unit 50 for receiving a 53-byte ATM cell; A 53-byte ATM cell is received from the transmission unit 50, a 5-byte header is extracted, and a payload of 48 bytes is transferred to the first memory 10 by the address information read from the second memory 30. At the same time, the start address of the first memory 10 in which the extracted header and the information are stored and the number of assembled bytes are stored in the second memory 30 so that the CPU can determine the cell assembly situation. A cell assembly processor 60; The cell assembly processor 60 outputs a control signal to store packet information in the first memory 10, and the cell assembly processor 60 and the CPU simultaneously request access to the first memory 10. A first arbitration unit 70 outputting an arbitration signal to prevent a signal collision; And outputting a control signal to allow the cell assembly processor 60 to read address information from the second memory 30 and to store header, start address, and byte number information in the second memory 30. A second arbitration unit 80 which outputs a control signal and outputs an arbitration signal to prevent a signal collision when the cell assembly processor 60 and the CPU simultaneously request access of the second memory 30; Cell assembly apparatus of ATM-MSS, characterized in that there is. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052874A 1995-12-20 1995-12-20 Cell reassembly apparatus in atm mss KR0166199B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950052874A KR0166199B1 (en) 1995-12-20 1995-12-20 Cell reassembly apparatus in atm mss

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Application Number Priority Date Filing Date Title
KR1019950052874A KR0166199B1 (en) 1995-12-20 1995-12-20 Cell reassembly apparatus in atm mss

Publications (2)

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KR970056373A true KR970056373A (en) 1997-07-31
KR0166199B1 KR0166199B1 (en) 1999-02-01

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