CA2349031A1 - Method of fabricating mode-size converter with three dimensional tapered with high processing tolerance - Google Patents
Method of fabricating mode-size converter with three dimensional tapered with high processing tolerance Download PDFInfo
- Publication number
- CA2349031A1 CA2349031A1 CA 2349031 CA2349031A CA2349031A1 CA 2349031 A1 CA2349031 A1 CA 2349031A1 CA 2349031 CA2349031 CA 2349031 CA 2349031 A CA2349031 A CA 2349031A CA 2349031 A1 CA2349031 A1 CA 2349031A1
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- CA
- Canada
- Prior art keywords
- layer
- taper
- waveguide
- mode
- size converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title description 10
- 230000003287 optical effect Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000835 fiber Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/1228—Tapered waveguides, e.g. integrated spot-size transformers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Optical Integrated Circuits (AREA)
Abstract
A three-dimensional taper geometry is employed in passive and active waveguide components. The structure as two portions with tapering in both the lateral and vertical direction.
Description
Method of fabricating mode size converter with three dimensional taper with high processing tolerance Background of the Invention Field of the Invention This invention relates to the field of photonics, and in particular to a method of fabricating a mode size converter with a three dimensional taper.
2. Description of Related Art Optical modes in waveguides with small dimensions, particularly waveguides with high refractive index contrast, are mismatched to the optical modes in fibers commonly used in fiber optic communications. Proper means need to be employed to improve the waveguide to fiber coupling. One method for accomplishing such is tapered waveguides (or often referred to as mode-size converter, mode-size transformer}. A properly designed tapered waveguide supports a mode of comparable size as in fibers at one end, and transform the mode adibatically (with minimum optical loss) to an appropriate size at the other end as required by other waveguide optical components.
The above-described problem exists for both passive and active waveguide components. Much work has been done in the past to address the mismatch between optical modes in lasers and fibers. Several types of geometries have been proposed previously, with different degrees of success. Lateral tapers have tapered waveguide width, usually done through layout design. Vertical tapers have similar changes but in the direction perpendicular to the waveguide surface.
Two-portion taper with the SAME MATERIAL has also been proposed. The upper portion tapers to a 'POINT', and the lower portion tapers to a smaller width suitable for a single mode waveguide. The mode is substantially transferred from the upper portion at the large end to the lower portion at the small end.
There are two aspects of limitations to the present designs. One is the geometry itself, the other is the method for making such.
Lateral or vertical taper only addresses the mode mismatch in one direction.
The previously proposed two-portion taper only tapers in the lateral direction.
Mode matching is facilitated in both directions. In order to force the mode down to the lower waveguide, the upper waveguide needs to be tapered gradually to a very narrow width. Any light remaining in the upper portion represents optical loss.
Minimizing the width only is not sufficiently effective.
In known fabrication methods, two portion tapers of the same material required very uniform etching process with smooth etched surface and precisely controlled etch depth, in order not to degrade the performance of the lower portion waveguides and other associated waveguide components. To achieve a 'point' termination in the upper portion (approximately 0.1 mm wide), high-resolution pattern definition methods, such as electro-beam lithography, are required. These kinds of methods are expensive and not suitable for volume production.
Summary of the Invention In accordance with the principles of the invention a three-dimensional taper geometry is employed. The inventive structure as tvvo portions with tapering in both the lateral and vertical direction.
Tapering in the vertical direction only needs to be introduced near the termination point. Reduced size in both directions will efficiently force the optical mode into the lower waveguide. This geometry is generally effective, in a variety of material systems such as III-V compounds and silicon-on insulator (SOI).
Brief Description of the Drawings The invention will now be described in more detail, by way of example, only with reference to the accompanying drawings, in which:-Figure 1 shows a two-portion three dimensional taper structure in accordance with the invention;
Figure 2 shows a process sequence of one proposed method for obtaining vertical taper near the termination end of the upper waveguide;
Figure 3 is a cross-sectional illustration of a two-layer taper structure; and Figure 4 is a top view schematic illustrating how a blunt termination can be sharpened through the oxidation of silicon.
Detailed Description of the Invention One method for achieving upper vertical taper is described as follows, in an example of SOI-based structure (Fig. 2).
The structure is first patterned with a thin Layer of metal, a layer of sacrificial material, and finally the thick layer of silicon. By necessity, the metal is under tensile stress and the sacrificial layer has to etch substantially faster than the silicon. Silicon dioxide is a candidate for such sacrificial layer. The layered wedge is then placed in a chemical etching environment. The sacrificial Layer and Si are etched both vertically and laterally into the wedge. Since the sacrificial layer etches faster than the silicon, the metal mask would quickly become undercut. As it is gradually freed, the metal would lift upwards under its own tensile stress, exposing more of the sacrificial layer and the underlying silicon to the etch reactants. This process would continue down the length of the taper, with the silicon beneath the metal etching on a vertical slant a;s it is progressively exposed, forming a vertical taper near the termination end.
Although the concept of a two-Layer taper structure is generally applicable, it is described in the following through an example of SO~I-based structure (Fig.
The above-described problem exists for both passive and active waveguide components. Much work has been done in the past to address the mismatch between optical modes in lasers and fibers. Several types of geometries have been proposed previously, with different degrees of success. Lateral tapers have tapered waveguide width, usually done through layout design. Vertical tapers have similar changes but in the direction perpendicular to the waveguide surface.
Two-portion taper with the SAME MATERIAL has also been proposed. The upper portion tapers to a 'POINT', and the lower portion tapers to a smaller width suitable for a single mode waveguide. The mode is substantially transferred from the upper portion at the large end to the lower portion at the small end.
There are two aspects of limitations to the present designs. One is the geometry itself, the other is the method for making such.
Lateral or vertical taper only addresses the mode mismatch in one direction.
The previously proposed two-portion taper only tapers in the lateral direction.
Mode matching is facilitated in both directions. In order to force the mode down to the lower waveguide, the upper waveguide needs to be tapered gradually to a very narrow width. Any light remaining in the upper portion represents optical loss.
Minimizing the width only is not sufficiently effective.
In known fabrication methods, two portion tapers of the same material required very uniform etching process with smooth etched surface and precisely controlled etch depth, in order not to degrade the performance of the lower portion waveguides and other associated waveguide components. To achieve a 'point' termination in the upper portion (approximately 0.1 mm wide), high-resolution pattern definition methods, such as electro-beam lithography, are required. These kinds of methods are expensive and not suitable for volume production.
Summary of the Invention In accordance with the principles of the invention a three-dimensional taper geometry is employed. The inventive structure as tvvo portions with tapering in both the lateral and vertical direction.
Tapering in the vertical direction only needs to be introduced near the termination point. Reduced size in both directions will efficiently force the optical mode into the lower waveguide. This geometry is generally effective, in a variety of material systems such as III-V compounds and silicon-on insulator (SOI).
Brief Description of the Drawings The invention will now be described in more detail, by way of example, only with reference to the accompanying drawings, in which:-Figure 1 shows a two-portion three dimensional taper structure in accordance with the invention;
Figure 2 shows a process sequence of one proposed method for obtaining vertical taper near the termination end of the upper waveguide;
Figure 3 is a cross-sectional illustration of a two-layer taper structure; and Figure 4 is a top view schematic illustrating how a blunt termination can be sharpened through the oxidation of silicon.
Detailed Description of the Invention One method for achieving upper vertical taper is described as follows, in an example of SOI-based structure (Fig. 2).
The structure is first patterned with a thin Layer of metal, a layer of sacrificial material, and finally the thick layer of silicon. By necessity, the metal is under tensile stress and the sacrificial layer has to etch substantially faster than the silicon. Silicon dioxide is a candidate for such sacrificial layer. The layered wedge is then placed in a chemical etching environment. The sacrificial Layer and Si are etched both vertically and laterally into the wedge. Since the sacrificial layer etches faster than the silicon, the metal mask would quickly become undercut. As it is gradually freed, the metal would lift upwards under its own tensile stress, exposing more of the sacrificial layer and the underlying silicon to the etch reactants. This process would continue down the length of the taper, with the silicon beneath the metal etching on a vertical slant a;s it is progressively exposed, forming a vertical taper near the termination end.
Although the concept of a two-Layer taper structure is generally applicable, it is described in the following through an example of SO~I-based structure (Fig.
3). A
lower waveguide is first formed in the single crystalline Si layer on a SOI
substrate (called lower waveguide layer). The surface is covered with a thin etch-stop layer, and in this case it may be chosen as a dielectric layer (Si dioxide or nitride).
Epitaxially grown SiOe layer is another possibility. Irt the selected etch chemistry, the upper Layer would etch much faster than the etch-stop layer. The etch stop layer is designed to be sufficiently thin, so it is effectively 'invisible' to the optical modes. Finally the surface is covered by a thick optically transparent layer (called upper waveguide layer), and in this case it may be amorphous silicon (a-Si) or poly-crystalline silicon (poly-Si). The upper taper is :Formed in the upper layer by etching down to the dielectric etch-stop layer. SF6 based chemistry may be used, which has high etch selectivity between silicon and oxide/nitride. Small variations in the etch rate of the upper layer or surface roughness will not be transferred into the lower layer. Process tolerance is therefore greatly improved. Since the required taper length is relatively short (on the order of 200 ~xn), slightly increased absorption in the a-Si or poly-Si materials is acceptable.
Oxidation for point termination: To achieve well define 'point' termination in the upper waveguide of a two-portion taper structure, high resolution (such as electron-beam) lithography has been used traditionally. This is not suitable for volume production. We propose to form a two-portion taper with optical lithography (Fig. 4), which is readily available in semiconductor manufacturing and easily has a resolution near/below 1 ~,m. Then the structure is put to undergo thermal oxidation, which consumes Si from all exposed surfaces. Oxidation process for moderate to large oxide thickness is diffusion controlled.
Oxidation rate decreases with the thickness of the oxide present: on the surface. The width of the upper waveguide near termination point is designed to reduce gently, to ensure that after a certain thickness of oxide is formed, the oxidation primarily takes place from the two sides, as indicated in Fig. 4. The oxide thickness can be so chosen that the termination forms a 'point'. This metlhod is fully compatible with VLSI manufacturing. The different oxidation rates between various crystal planes (e.g. the oxidation rate for (111) planes can be up to 50% higher than that for (100) planes) may also facilitate the formation of a 3-dimensional taper near the termination end.
Three-dimensional geometry provides more efficient coupling from the upper to the lower waveguide than previous designs. Two-layer taper with a sandwiched thin, optically 'invisible' etch-stop layer has relaxed constraints on processing controls. Oxidation for point termination eliminates t:he needs for high-resolution lithography, and makes the taper fabrication compatible with VLSI
manufacturing.
lower waveguide is first formed in the single crystalline Si layer on a SOI
substrate (called lower waveguide layer). The surface is covered with a thin etch-stop layer, and in this case it may be chosen as a dielectric layer (Si dioxide or nitride).
Epitaxially grown SiOe layer is another possibility. Irt the selected etch chemistry, the upper Layer would etch much faster than the etch-stop layer. The etch stop layer is designed to be sufficiently thin, so it is effectively 'invisible' to the optical modes. Finally the surface is covered by a thick optically transparent layer (called upper waveguide layer), and in this case it may be amorphous silicon (a-Si) or poly-crystalline silicon (poly-Si). The upper taper is :Formed in the upper layer by etching down to the dielectric etch-stop layer. SF6 based chemistry may be used, which has high etch selectivity between silicon and oxide/nitride. Small variations in the etch rate of the upper layer or surface roughness will not be transferred into the lower layer. Process tolerance is therefore greatly improved. Since the required taper length is relatively short (on the order of 200 ~xn), slightly increased absorption in the a-Si or poly-Si materials is acceptable.
Oxidation for point termination: To achieve well define 'point' termination in the upper waveguide of a two-portion taper structure, high resolution (such as electron-beam) lithography has been used traditionally. This is not suitable for volume production. We propose to form a two-portion taper with optical lithography (Fig. 4), which is readily available in semiconductor manufacturing and easily has a resolution near/below 1 ~,m. Then the structure is put to undergo thermal oxidation, which consumes Si from all exposed surfaces. Oxidation process for moderate to large oxide thickness is diffusion controlled.
Oxidation rate decreases with the thickness of the oxide present: on the surface. The width of the upper waveguide near termination point is designed to reduce gently, to ensure that after a certain thickness of oxide is formed, the oxidation primarily takes place from the two sides, as indicated in Fig. 4. The oxide thickness can be so chosen that the termination forms a 'point'. This metlhod is fully compatible with VLSI manufacturing. The different oxidation rates between various crystal planes (e.g. the oxidation rate for (111) planes can be up to 50% higher than that for (100) planes) may also facilitate the formation of a 3-dimensional taper near the termination end.
Three-dimensional geometry provides more efficient coupling from the upper to the lower waveguide than previous designs. Two-layer taper with a sandwiched thin, optically 'invisible' etch-stop layer has relaxed constraints on processing controls. Oxidation for point termination eliminates t:he needs for high-resolution lithography, and makes the taper fabrication compatible with VLSI
manufacturing.
Claims (4)
1. An optical component employing a three-dimensional taper geometry.
2. An optical component as claimed in claim 2, wherein said taper geometry includes two portions with tapering in both the lateral and vertical direction.
3. An optical component as claimed in claim 2, wherein said component is a passive waveguide.
4. An optical component as claimed in claim 2, wherein said component is an active waveguide.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2349031 CA2349031A1 (en) | 2001-05-28 | 2001-05-28 | Method of fabricating mode-size converter with three dimensional tapered with high processing tolerance |
| PCT/CA2002/000780 WO2002097489A2 (en) | 2001-05-28 | 2002-05-28 | Method of fabricating mode-size converter with three-dimensional taper |
| AU2002302262A AU2002302262A1 (en) | 2001-05-28 | 2002-05-28 | Method of fabricating mode-size converter with three-dimensional taper |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2349031 CA2349031A1 (en) | 2001-05-28 | 2001-05-28 | Method of fabricating mode-size converter with three dimensional tapered with high processing tolerance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2349031A1 true CA2349031A1 (en) | 2002-11-28 |
Family
ID=4169125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2349031 Abandoned CA2349031A1 (en) | 2001-05-28 | 2001-05-28 | Method of fabricating mode-size converter with three dimensional tapered with high processing tolerance |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU2002302262A1 (en) |
| CA (1) | CA2349031A1 (en) |
| WO (1) | WO2002097489A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150086153A1 (en) * | 2013-09-20 | 2015-03-26 | Oki Electric Industry Co., Ltd. | Optical device having a stepwise or tapered light input/output part and manufacturing method therefor |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004008203A1 (en) * | 2002-07-11 | 2004-01-22 | Redfern Integrated Optics Pty Ltd | Planar waveguide with tapered region |
| US9268089B2 (en) * | 2011-04-21 | 2016-02-23 | Octrolix Bv | Layer having a non-linear taper and method of fabrication |
| US9310555B2 (en) | 2014-05-16 | 2016-04-12 | Tyco Electronics Corporation | Mode size converters and methods of fabricating the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4938841A (en) * | 1989-10-31 | 1990-07-03 | Bell Communications Research, Inc. | Two-level lithographic mask for producing tapered depth |
| US5574742A (en) * | 1994-05-31 | 1996-11-12 | Lucent Technologies Inc. | Tapered beam expander waveguide integrated with a diode laser |
-
2001
- 2001-05-28 CA CA 2349031 patent/CA2349031A1/en not_active Abandoned
-
2002
- 2002-05-28 AU AU2002302262A patent/AU2002302262A1/en not_active Abandoned
- 2002-05-28 WO PCT/CA2002/000780 patent/WO2002097489A2/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150086153A1 (en) * | 2013-09-20 | 2015-03-26 | Oki Electric Industry Co., Ltd. | Optical device having a stepwise or tapered light input/output part and manufacturing method therefor |
| US9335475B2 (en) * | 2013-09-20 | 2016-05-10 | Oki Electric Industry Co., Ltd. | Method of manufacturing an optical device having a stepwise or tapered light input/output part |
| US20160223748A1 (en) * | 2013-09-20 | 2016-08-04 | Oki Electric Industry Co., Ltd. | Optical device having a stepwise or tapered light input/output part and manufacturing method therefor |
| US9869815B2 (en) | 2013-09-20 | 2018-01-16 | Oki Electric Industry Co., Ltd. | Optical device having a stepwise or tapered light input/output part and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002097489A3 (en) | 2003-11-20 |
| AU2002302262A1 (en) | 2002-12-09 |
| WO2002097489A2 (en) | 2002-12-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |