CA2345443C - Approach for routing an integrated circuit - Google Patents

Approach for routing an integrated circuit Download PDF

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Publication number
CA2345443C
CA2345443C CA002345443A CA2345443A CA2345443C CA 2345443 C CA2345443 C CA 2345443C CA 002345443 A CA002345443 A CA 002345443A CA 2345443 A CA2345443 A CA 2345443A CA 2345443 C CA2345443 C CA 2345443C
Authority
CA
Canada
Prior art keywords
integrated circuit
routing
routing path
layout
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002345443A
Other languages
English (en)
French (fr)
Other versions
CA2345443A1 (en
Inventor
David C. Chapman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2345443A1 publication Critical patent/CA2345443A1/en
Application granted granted Critical
Publication of CA2345443C publication Critical patent/CA2345443C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CA002345443A 1998-10-19 1999-10-19 Approach for routing an integrated circuit Expired - Fee Related CA2345443C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10487298P 1998-10-19 1998-10-19
US60/104,872 1998-10-19
US13953299P 1999-06-16 1999-06-16
US60/139,532 1999-06-16
PCT/US1999/024454 WO2000023920A1 (en) 1998-10-19 1999-10-19 Approach for routing an integrated circuit

Publications (2)

Publication Number Publication Date
CA2345443A1 CA2345443A1 (en) 2000-04-27
CA2345443C true CA2345443C (en) 2009-09-15

Family

ID=26802032

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002345443A Expired - Fee Related CA2345443C (en) 1998-10-19 1999-10-19 Approach for routing an integrated circuit

Country Status (8)

Country Link
EP (1) EP1131749A1 (ko)
JP (1) JP2002528795A (ko)
KR (1) KR100910421B1 (ko)
AU (1) AU1124500A (ko)
CA (1) CA2345443C (ko)
IL (1) IL142305A0 (ko)
TW (1) TW495686B (ko)
WO (1) WO2000023920A1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7882251B2 (en) 2003-08-13 2011-02-01 Microsoft Corporation Routing hints
US8266294B2 (en) 2003-08-13 2012-09-11 Microsoft Corporation Routing hints
JP2005115785A (ja) * 2003-10-09 2005-04-28 Nec Electronics Corp 半導体装置の配線方法、半導体装置の製造方法及び半導体装置
KR100674934B1 (ko) * 2005-01-06 2007-01-26 삼성전자주식회사 온 칩 버스(Ｏｎ Ｃｈｉｐ Ｂｕｓ)에서 최적화된타일-스위치(ｔｉｌｅ－ｓｗｉｔｃｈ)맵핑(ｍａｐｐｉｎｇ) 구조를 결정하는 방법 및 그 방법을기록한 컴퓨터로 읽을 수 있는 기록 매체
US7376927B2 (en) * 2005-06-13 2008-05-20 Advanced Micro Devices, Inc. Manhattan routing with minimized distance to destination points
EP1907957A4 (en) 2005-06-29 2013-03-20 Otrsotech Ltd Liability Company INVESTMENT METHODS AND SYSTEMS
US7752588B2 (en) 2005-06-29 2010-07-06 Subhasis Bose Timing driven force directed placement flow
US7681170B2 (en) 2006-02-09 2010-03-16 Qualcomm Incorporated Method and apparatus for insertion of filling forms within a design layout
US8332793B2 (en) 2006-05-18 2012-12-11 Otrsotech, Llc Methods and systems for placement and routing
US7840927B1 (en) 2006-12-08 2010-11-23 Harold Wallace Dozier Mutable cells for use in integrated circuits
TWI403914B (zh) * 2010-03-08 2013-08-01 Mstar Semiconductor Inc 防止壅塞配置裝置及方法
CN111159830B (zh) * 2019-11-30 2024-06-07 浙江华云信息科技有限公司 一种基于特征形状的正交线段拐点合并的线路布局方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258920A (en) * 1989-12-26 1993-11-02 General Electric Company Locally orientation specific routing system
US5450331A (en) * 1992-01-24 1995-09-12 Vlsi Technology, Inc. Method for verifying circuit layout design
JPH06196563A (ja) * 1992-09-29 1994-07-15 Internatl Business Mach Corp <Ibm> Ｖｌｓｉの配線設計に対するコンピュータ実施可能な過密領域配線方法
US5550748A (en) * 1994-03-22 1996-08-27 Cadence Design Systems, Inc. Region search for delay routing and signal net matching
JP3335250B2 (ja) * 1994-05-27 2002-10-15 株式会社東芝 半導体集積回路の配線方法

Also Published As

Publication number Publication date
WO2000023920A1 (en) 2000-04-27
EP1131749A1 (en) 2001-09-12
TW495686B (en) 2002-07-21
KR100910421B1 (ko) 2009-08-04
WO2000023920A9 (en) 2000-09-14
JP2002528795A (ja) 2002-09-03
KR20010087374A (ko) 2001-09-15
CA2345443A1 (en) 2000-04-27
AU1124500A (en) 2000-05-08
IL142305A0 (en) 2002-03-10

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