CA2257996A1 - Procede et dispositif permettant de compiler un circuit dans une sequence de circuits a l'interieur d'un reseau prediffuse programmable - Google Patents

Procede et dispositif permettant de compiler un circuit dans une sequence de circuits a l'interieur d'un reseau prediffuse programmable Download PDF

Info

Publication number
CA2257996A1
CA2257996A1 CA002257996A CA2257996A CA2257996A1 CA 2257996 A1 CA2257996 A1 CA 2257996A1 CA 002257996 A CA002257996 A CA 002257996A CA 2257996 A CA2257996 A CA 2257996A CA 2257996 A1 CA2257996 A1 CA 2257996A1
Authority
CA
Canada
Prior art keywords
circuits
circuit
logic gates
subplurality
pga
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002257996A
Other languages
English (en)
Inventor
Mark R. Cummings
John L. Watson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Morphics Technology Inc
Original Assignee
Mark R. Cummings
John L. Watson
Envia, Inc.
Morphics Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mark R. Cummings, John L. Watson, Envia, Inc., Morphics Technology, Inc. filed Critical Mark R. Cummings
Publication of CA2257996A1 publication Critical patent/CA2257996A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Logic Circuits (AREA)
  • Transceivers (AREA)
CA002257996A 1996-06-10 1997-06-10 Procede et dispositif permettant de compiler un circuit dans une sequence de circuits a l'interieur d'un reseau prediffuse programmable Abandoned CA2257996A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1810396P 1996-06-10 1996-06-10
US60/018,103 1996-06-10

Publications (1)

Publication Number Publication Date
CA2257996A1 true CA2257996A1 (fr) 1997-12-18

Family

ID=21786259

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002257996A Abandoned CA2257996A1 (fr) 1996-06-10 1997-06-10 Procede et dispositif permettant de compiler un circuit dans une sequence de circuits a l'interieur d'un reseau prediffuse programmable

Country Status (6)

Country Link
EP (1) EP0980555A1 (fr)
JP (1) JP4446492B2 (fr)
KR (1) KR20000016513A (fr)
AU (1) AU3794197A (fr)
CA (1) CA2257996A1 (fr)
WO (1) WO1997048062A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10195203B3 (de) * 2000-01-28 2014-01-02 Infineon Technologies Ag Verfahren zur Erzeugung einer Konfiguration für ein konfigurierbares Kommunikationsgerät sowie elektronisches Gerät und computerlesbares Medium

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US5023775A (en) * 1985-02-14 1991-06-11 Intel Corporation Software programmable logic array utilizing "and" and "or" gates
US4918440A (en) * 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
US5644497A (en) * 1988-03-15 1997-07-01 Hyman; Edward Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential logic array
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5189628A (en) * 1991-03-11 1993-02-23 National Semiconductor Corporation System and method for partitioning PLA product terms into distinct logical groups
US5603043A (en) * 1992-11-05 1997-02-11 Giga Operations Corporation System for compiling algorithmic language source code for implementation in programmable hardware
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
CA2126265A1 (fr) * 1993-09-27 1995-03-28 Michael Robert Cantone Systeme de synthese d'implantation de circuits prediffuses programmables sur place, a partir de description de circuits de haut niveau

Also Published As

Publication number Publication date
JP2000512461A (ja) 2000-09-19
EP0980555A1 (fr) 2000-02-23
JP4446492B2 (ja) 2010-04-07
KR20000016513A (ko) 2000-03-25
AU3794197A (en) 1998-01-07
WO1997048062A1 (fr) 1997-12-18

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