CA2251737A1 - Silicon carbide cmos and method of fabrication - Google Patents
Silicon carbide cmos and method of fabricationInfo
- Publication number
- CA2251737A1 CA2251737A1 CA002251737A CA2251737A CA2251737A1 CA 2251737 A1 CA2251737 A1 CA 2251737A1 CA 002251737 A CA002251737 A CA 002251737A CA 2251737 A CA2251737 A CA 2251737A CA 2251737 A1 CA2251737 A1 CA 2251737A1
- Authority
- CA
- Canada
- Prior art keywords
- silicon carbide
- layer
- well region
- fabrication
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A monolithic CMOS integrated device formed in silicon carbide and method of fabricating same. The CMOS integrated device includes a layer of silicon carbide of a first conductivity type with a well region of a second conductivity type formed in the layer of silicon carbide. A MOS field effect transistor is formed in the well region and a complementary MOS field effect transistor is formed in the silicon carbide layer. The method of fabrication of CMOS silicon carbide includes formation of an opposite conductivity well region in a silicon carbide layer by ion implantation. Source and drain contacts are also formed by selective ion implantation in the silicon carbide layer and the well region. A gate dielectric layer is formed by deposition and re-oxidation. A gate electrode is formed on the gate dielectric such that a channel region is formed between the source and the drain when a bias is applied to the gate electrode. Source drain and body contacts are preferably formed of the same material in a single fabrication step.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/631,926 US6344663B1 (en) | 1992-06-05 | 1996-04-15 | Silicon carbide CMOS devices |
| US08/631,926 | 1996-04-15 | ||
| PCT/US1997/006156 WO1997039485A1 (en) | 1996-04-15 | 1997-04-14 | Silicon carbide cmos and method of fabrication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2251737A1 true CA2251737A1 (en) | 1997-10-23 |
| CA2251737C CA2251737C (en) | 2006-02-14 |
Family
ID=35892350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002251737A Expired - Fee Related CA2251737C (en) | 1996-04-15 | 1997-04-14 | Silicon carbide cmos and method of fabrication |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2251737C (en) |
-
1997
- 1997-04-14 CA CA002251737A patent/CA2251737C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2251737C (en) | 2006-02-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| AU2667597A (en) | Silicon carbide cmos and method of fabrication | |
| KR100315843B1 (en) | Device design for enhanced avalanche soi cmos | |
| GB2286723A (en) | A mos transistor having a composite gate electrode and method of fabrication | |
| EP2264771A3 (en) | MOS thin film transistor and method of fabricating same | |
| EP0820096A3 (en) | Semiconductor device and method for fabricating the same | |
| TW332924B (en) | Semiconductor | |
| TW327240B (en) | Semiconductor device and process for producing the same | |
| SG145563A1 (en) | Method to form a self-aligned cmos inverter using vertical device integration | |
| EP0271247A3 (en) | A mos field effect transistor and a process for fabricating the same | |
| EP0738011A3 (en) | High voltage integrated circuit, high voltage junction terminating structure, and high voltage MIS transistor | |
| EP0402784A3 (en) | Method of manufacturing a CMOS semiconductor device | |
| US5021356A (en) | Method of making MOSFET depletion device | |
| MY123211A (en) | Self-aligned dynamic threshold cmos device | |
| GB2346481A (en) | Field effect transistor | |
| EP0694963A3 (en) | Improvements in BiCMOS semiconductor devices and method therefor | |
| JP3282375B2 (en) | Complementary insulated gate field effect transistor | |
| EP0849804A3 (en) | Improvements in or relating to field effect transistors | |
| EP0361121A3 (en) | Semiconductor ic device with improved element isolating scheme | |
| CA2251737A1 (en) | Silicon carbide cmos and method of fabrication | |
| EP0414400A3 (en) | Mosfet depletion device | |
| EP0656660A3 (en) | BiCMOS process for supporting merged devices | |
| US6110767A (en) | Reversed MOS | |
| WO1996030940A3 (en) | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH BiCMOS CIRCUIT | |
| JPH11330264A (en) | Semiconductor integrated circuit device and its manufacture | |
| WO1987007084A1 (en) | Fabrication of mos-transistors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20130415 |