CA2203787A1 - Multiplexer of digital information packets, especially for digital television - Google Patents

Abstract

A device with a packetising module (C1) including a sensing circuit (22) for sensing synchronisation words in the input stream; a storage unit (23) receiving a series of input stream bytes that have been presented to the sensing circuit (22); means (32) enabling transfer to a packet memory (PM1);
and a processor (26) for determining the headers of packets put together from the input stream on the basis of the synchronisation words sensed by the sensing circuit (22), writing the headers into the packet memory (Pmi), and controlling the transfer means (32) so that the length of the header of one packet can be determined while the bytes of a previous packet are being transferred from the storage unit (23) to the packet memory (PM1).

Description

CA 02203787 1997-04-2~

MnLTIPLEXER OF DIGITAL INFORM~TION PACKETS, ESPECIALLY FOR DIGITAL TELEVISION

The present invention relates to a device for producing a time multiplex of digital information packets, comprising several packetizing modules each receiving a digital input stream, several packet memories each receiving packets emanating from a respective packetizing module, and multiplexing means selecting the packet memories from which the packets of the multiplex are to be extracted and succes-sively transferring said packets to an output of the device.
The invention relates more particularly to the field of digital television. It applies especially within the framework of the MPEG2 system standard defined in draft international standard ISO/IEC 13818-1 from the International Standardization Organization dated June 10 1994 (Information Technology - Generic Coding of Moving Pictures and Associated Audio/Recommendation H.222.0). This document ISO/IEC 13818-1 should be referred to for all information regarding the structure of the packets in question in the present application.
The MPEG2 system standard defines two types of multiplexed digital streams: transport streams (TS) and program streams (PS). A "program" is defined as a set of time-correlated elementary streams, i.e. each of which carries information to be restored with respect to a common CA 02203787 1997-04-2~

time base. A program stream PS transmits a single program in the form of packets of relatively large and possibly variable length. The streams PS are envisaged for transmission channels which introduce few errors. They are typically used for storing information on disk. The transport streams are made up of packets belonging to one or more programs, and are used for transmission in environments which may introduce errors. The transport packets (TP~ have a fixed length of 188 bytes and each comprise a TP header of at least 4 bytes.
These multiplexed streams are constructed from packetized elementary streams (PES). The raw elementary streams (ES) emanating directly from the video or audio coding are firstly put into the form of PES packets of variable length. The PES streams are then repartitioned in order to constitute the packets TS or PS to be multiplexed.
Currently, certain coders output elementary streams at the ES level, and others at the PES level. The elementary streams can also be made up of data other than audio or video, for example data detailing program-specific information (PSI), data relating to conditional access to a program (ECM or EMM) ...
The role of an MPEG2 multiplexer is to receive these various elementary streams, form the packets TS or PS, and then perform the time multiplexing of these packets.
A device according to the invention can also be what is called a remultiplexer. A remultiplexer is a device for CA 02203787 1997-04-2~

producing a multiplex such as defined in the introduction, in which one at least of the input streams has already been multiplexed upstream , in the PS or TS format. A
remultiplexer can be used for example in order to extract packets related to one program from a transport stream and to produce as output another transport stream or program stream containing only this program, in order to extract the packets relating to one or more programs from one or more transport streams so as to construct another transport stream, or else in order to convert a program stream into a transport stream with a view to transmitting it in a lossy environment.
Each elementary stream input requires a processor for the packetization, which makes the packets constructed available to the multiplexing module by way of an exchange buffer. Each processor must in fact potentially carry out two packetizing steps, possibly entailing the need for a processor for each step in the case of large bit rates:
- the first step consists in converting the raw elementary stream into a packetized elementary stream PES;
- the second step consists in reconverting the PES
packets into transport packets.
Each of the two packetizing steps entails the analysis of the input stream so as to determine certain specific words (elementary synchronization words for the PES
layer, or PES synchronization words for the transport layer), so as to carry out the partition into packets at the CA 02203787 1997-04-2~

appropriate places and to reflect in the headers of the transport packets the possible presence of these synchronization words.
A purpose of the present invention -s to propose a device such as defined in the introduction, which makes it possible to process various types of input streams in an efficient manner.
In a device according to the invention, a packet-izing module comprises:
- an input buffer receiving the input stream;
- a detection circuit linked to the output of the input buffer so as to detect synchronization words of the input stream;
- a storage unit successively receiving the bytes of the input stream which have been presented to the detection clrcult;
- transfer means for transferring bytes from the storage unit to a packet memory; and - a processor for determining the headers of the packets constructed from the input stream on the basis of the synchronization words detected by the detection circuit, writing these headers to the packet memory and controlling the transfer means.
The storage unit is organized in first-in, first-out mode so as to contain at each instant K-k bytes of input stream, K denoting the number of bytes of a packet of the output multiplex and k denoting the minimum number of bytes CA 02203787 1997-04-2~

of the packet headers, and so that the transfer of a byte from the storage unit to the packet memory is accompanied by the transfer of another byte from the detection circuit to the storage unit, so that all the bytes of the input stream which may be introduced into a packet are presented to the detection circuit before the writing of this packet to the packet memory commences.
The synchronization words to be detected can be programmed into the detection circuit so as to adapt the packetizing module to various types of input stream. In the case of a raw elementary stream ES, the two packetizing layers (PES and TP) are constructed in a single pass by the processor. A complete packetizing module in respect of an ES
stream may therefore include a single processor only. The packetizing process may moreover be very fast since the determination of the header of a packet by the processor is carried out while the previous packet is being transferred from the storage unit.
Other features and advantages of the present invention will emerge from the description below of a preferred but non-limiting example embodiment, with reference to the appended drawings in which:
- Figure 1 is an overall schematic diagram of a first embodiment of the invention;
- Figure 2 is a schematic àiagram cf a packetizing module usable in the device of Figure 1;
- Figures 3 to 5 are charts illustrating the CA 02203787 1997-04-2~

operation of packetizing modules according to Figure 2;
- Figure 6 is a diagram of a multiplexing module usable in the device of Figure 1;
- Figures 7 and 8 are graphs illustrating an example of the computing of priorities in a multiplexing module;
- Figure 9 is a diagram of an election circuit usable in the multiplexing module of Figure 6; and - Figure 10 is an overall schematic diagram of a second embodiment of the invention.
The device represented in Figure 1 is described below in its application to the production of an output multiplex OS having the format of a transport stream TS in the sense of the MPEG2 standard. It will be understood that the device could also be applied to produce another type of multiplex, in particular a program stream PS in the sense of the MPEG2 standard.
The device includes n packetizing modules C1, ....
Cn each receiving an input stream IS1, ..., ISn. The n input streams carry a total of m elementary streams. In the case of a multiplexer whose input streams are all made up of elementary streams emanating respectively from coders or data sources, we have n = m. In the example represented in Figure 1, the stream IS2 is already multiplexed (transport stream TS for example), and the device is designed to take into account two elementary streams included within this multiplexed stream.
The packetizing modules C1, ..., Cn deliver CA 02203787 1997-04-2~

transport packets TP from each of the elementary streams which they receive. These transport packets are stored in dual-port buffer memories PM1, ..., PMm. Each packet memory PMi receives packets from a packetizing module. The packetizing modules C2 processing already multiplexed streams can feed several packet memories PM2, PM3. In this latter case, the packet memories PM2, PM3 can conveniently consist of two different addressing areas of the same memory plane.
Each packet memory PMi is associated with a parameter memory ZMi, also of dual-port type. Each time a packetizing module writes an information packet to a packet memory PMi, it furthermore writes a parameter set associated with this packet into the corresponding parameter memory ZMi. For reading, the packet memories PM1, ..., PMm are linked to a common packet bus 10, and the parameter memories ZM1, ..., ZMm are linked to a common parameter bus 12. These two buses are linked to a multiplexing module 14 whose role is to select the memories PMi from which the packets of the output multiplex OS are to be extracted and to transfer the packets in question successively to the output of the device.
The packetizing modules Cj analyze in real time the elementary streams which they receive and supply the transport packets to the buffer memories PMi. The real-time analysis of an elementary stream and the dual packetizing (PES and TP layers) may require large computational power, CA 02203787 1997-04-2~

especially for video streams which may attain bit rates of 15 Mbit/s in standard resolution, or more than 100 Mbit/s in high resolution. The packetizing module C1 illustrated in Figure 2 allows these severe demands to be met.
This module C1 comprises an input buffer 20 receiving the input stream IS1. At the output of the buffer 20, the bytes of the input stream pass through a detection circuit 22 before being transmitted to a storage unit 23 of first-in, first-out (FIFO) type. The output of the unit 23 is linked to the data input of the packet memory PM1.
The detection circuit 22 is embodied in the form of a user programmable gate array (FPGA). It consists of a shift register 24 with four stages of one byte, through which pass the bytes of the input stream before reaching the storage unit 23, and of detection logic 25 which receives the four bytes present in the stages of the register 24. The logic 25 is programmed as a function of the states to be detected in the input stream. The logic 25 detects these states of the input stream and informs a microprocessor 26 thereof. The processor 26 can access the parameter memory ZM1 through its address and data buses 28, 29. The buses 28, 29 are also linked to the packet memory PM1 by way of a three-state gate 31.
The storage unit 23 is managed so as at any instant to contain 184 bytes of the input -~tream, and so that each byte leaving this unit prompts the entry of another byte.
The unit 23 could therefore be embodied simply in the form CA 02203787 1997-04-2~

of a shift register with 184 stages of one byte. If shift registers of this size are not available, several of them may be cascaded, or else a random access memory may be used, its read and write addresses being generated in such a way as to keep a constant gap between them corresponding to a capacity of 184 bytes.
Depending on the states detected by the logic 25, the processor 26 supplies a transfer sequencer 32 with control parameters so as to perform the transfers of the bytes of the input stream from the storage unit 23 to the packet memory PM1. These control parameters comprise a start address for the writing of the data of a packet to the memory PM1, and the number of bytes to be transferred starting from this address. The sequencer 32 comprises an address counter which is initialized to the value of the start address supplied by the processor, and which is incremented with each byte transferred until the specified number of bytes has been transferred. This counter supplies the addresses for writing the bytes to the memory PM1. If the storage unit 23 is in the form of a random access memory, the sequencer 32 also supplies the read address of the byte to be transferred in such a way as to comply with the first-in, first-out protocol in this memory. The sequencer delivers a signal SC which clocks the transfers from and to the unit 23, the shifts in the register 24 of the detection circuit, and the readings of bytes from the input buffer 20.

In the example represented in Figure 2, the input stream IS1 is an elementary stream (ES or PES) which is to be packetized. The detection logic 25 is programmed to detect synchronization words in the input stream. Depending on the states detected by the logic 25, the processor 26 determines the length and the contents of the header to be placed at the beginning of the next transport packet to be registered into the memory PM1. This header is determined in accordance with the specifications of the MPEG2 standard, the processor 26 executing a header formation program such as described in the document IS0/IEC 13818-1. The length L
of the header can vary between k = 4 bytes and K = 188 bytes. Thus, the capacity of K - k = 184 bytes of the storage unit 23 guarantees that the totality of the bytes of the input stream which can be introduced into a transport packet have been analyzed by the detection circuit 22 before this packet commences to be transferred from the storage unit 23 to the packet memory PM1.
Figure 3 illustrates the construction of transport packets TP by the packetizing module in the case of a raw elementary stream ES emanating from an audio coder. In accordance with the MPEG2 standard, the audio ES stream consists of frames of constant length each commencing with a frame header 35A. The header 35A contains a synchronization word of 12 bits which equals FFF in hexadecimal. The detection logic 25 of a packetizing module processing an audio ES stream is therefore programmed to CA 02203787 1997-04-2~

detect this synchronization word FFF. A PES stream constructed from such an ES stream can comprise a PES header 36 immediately before each ES header 35A. However, the present packetizing module, when it processes an audio ES
5 stream, does not explicitly involve the PES contingency, but on the contrary constructs transport packets TP directly. In the case shown in Figure 3, so long as the logic 25 does not detect the synchronization word FFF in the lnput stream, the processor 26 computes a header 37a of L = 4 bytes, and orders the transfer of 188 - L = 184 bytes from the storage unit 23 to the memory PM1 in order to build a transport packet TP. When the logic 25 detects a synchronization word during the transfer of a packet to the memory PM1, the processor 26 computes the length L of the header 37b of the following packet in such a way as to pad out a transport packet of 188 bytes with the bytes of the elementary stream up to the synchronization word detected. To produce a header of length L greater than 4 bytes, the processor 26 intro-duces stream management parameters or stuffing bytes into the adaptation field of the header, as specified by the MPEG2 system standard. The packet which will follow the transport packet thus constructed will not include any byte of the input stream, but merely a TP header 37c and a PES
header 36. It may thus be considered that the processor 26 has determined a composite header 37c-36 of L = 188 bytes and has ordered the transfer of K - L = 0 bytes from the unit 23 in respect of this packet. The PES header 36 is CA 02203787 1997-04-2~

computed in accordance with the MPEG2 system standard, and the length of the TP header 37c will be adapted by means of the adaptation field as for the previous packet.
Figure 4 is a chart similar to that of Figure 3 in the case of a video type ES stream. According to the MPEG2 standard, a video type ES stream comprises three types of headers: sequence headers 35S containing a synchronization word of 4 bytes equal to OOOOOlB3 in hexadecimal, picture group headers 35G containing a synchronization word of 4 bytes equal to OOOOOlB8 in hexadecimal, and picture headers 35P containing a synchronization word of 4 bytes equal to 00000100 in hexadecimal. The structure of the video ES
stream is such that a sequence header 35S is always immediately followed by a picture group header 35G or by a picture header 35P, and that a picture group header 35G is always followed by a picture header 35P. The length of the video data relating to a picture, following each picture header 35P, is variable. A PES stream constructed from such a video ES stream can contain a PES header 36 before each sequence header 35S, before each group header 35G which is not immediately preceded by a sequence header 35S, and before each picture header 35P which is not immediately preceded by a group header 35G. However, the present packetizing module, when it processes a video ES stream, does not produce the corresponding PES stream explicitly, but rather TP transport packets directly. The insertion of the PES and TP headers is performed in essence in the same CA 02203787 1997-04-2~

way as in the audio case described with reference to Figure 3, the detection logic 25 being programmed to detect the synchronization words of the headers 35S, 35G and 35P.
However, the processor 26 does not insert a PES header 36 before all the picture headers 35P, but merely before those which are not immediately preceded by a picture group header 35G or by a sequence header 35S. Likewise, the processor 26 does not insert a PES header before all the picture group headers 35G, but merely before those which are not preceded immediately by a sequence header 35S. These various conditions may readily be identified on the basis of the synchronization words detected by the logic 25.
Figure 5 is a chart similar to those of Figures 3 and 4 in the case of an input stream of audio or video PES
type. The PES header 36 present in each packet of the PES
stream contains a synchronization word of 4 bytes, the first three of which are equal to 000001 in hexadecimal and the fourth of which is a stream identification byte. This identification byte being known in advance for a given PES
stream to be processed by the packetizing module, the logic 25 can be programmed to detect the synchronization words of 4 bytes of the PES stream. Partitioning into transport packets TP is then performed by the processor 26 in the same way as in the case of Figures 3 and 4, on the basis of the PES headers 36. The processor 26 does not take into account the ES headers 35 which are processed like data of the elementary stream. As in the cases of Figures 3 and 4, the CA 02203787 1997-04-2~

processor 26 can be programmed so that a TP packet containing a PES header 36 does not contain data of the elementary stream. The processor 26 then needs to know the length L' of the PES header in order to construct a packet containing only a TP header 37c of length L = K - L' bytes, followed by the PES header 36. This length L' can be read from the PES header itself by means of the detection circuit 22: if the seventh byte starting from the beginning of the PES header does not commence with the two bits '10', the PES
header has a length of L' = 6 bytes; otherwise the length L' is read from the ninth byte starting from the beginning of the PES header (see document IS0/IEC 13818-1).
The advantage of constructing the transport packets containing a PES header 36, placing merely a TP header 37a-c and said PES header 36 in these packets, is to allow scrambling of all the transport packets containing data of the elementary stream ES, the PES header not requiring to be scrambled.
The processor 26 writes, by way of the gate 31, the headers 37a-c and/or 36 at the appropriate positions in the packet memory PM1 in such a way as to comply with the structure, represented in Figure 3, 4 or 5, of the packets TP. This writing can take place before the transfer of the 188 - L bytes of the input stream belonging to the packet in question. It can also be performed later so long as the packet in question is still present in the memory PM1, especially in the case in which the TP header of a packet is CA 02203787 1997-04-2~

required to contain parameters depending on packets subsequently reaching the packetizing modules (for example picture partitioning parameters in the case of a video ES
stream).
5When the input stream is a multiplexed transport stream, the detection logic 25 is programmed to detect the synchronization byte indicating the beginning of a transport packet. This synchronization byte is equal to 47 in hexadecimal. The processor 26 logs the time of input of the 10packet when the synchronization byte is detected. By analyzing the following bytes of the TP header by way of the detection circuit 22, the processor 26 can read the 13 identification bits of the packet (PID field) and determine whether it contains optional temporal fields of the PCR or 15LTW type. The presence of the PCR or LTW fields is indicated by bits of specified position in the TP header (see document ISO/IEC 13818-1). The position of the PCR field is fixed, but that of the LTW field can vary so that the position of this field is also indicated, if appropriate, to the 20processor 26 by the circuit 22.
Knowing the identification parameter PID of the packet, which characterizes the elementary stream from which it emanates, the processor 26 can perform a filtering operation so as to transfer to the packet memory only the 25packets of the elementary streams to be retained in the output multiplex. To eliminate a packet, the processor orders the transfer sequencer 32 to write the packet to the packet memory at a garbage address where it will never be read.
In the case in which the packetizing module is associated with several packet memories PM2, PM3, these memories are grouped together in the same addressing space, and the write addresses generated by the transfer sequencer 32 are determined on the basis of the identification parameter PID supplied to the processor 26 by the detection circuit 22 in such a way as to obtain first-in, first-out operation in each of the packet memories PM2, PM3. The elementary streams to be retained in a multiplexed input stream can thus be steered to various packet memories.
The packetizing module represented in Figure 2 has great flexibility. It is readily adaptable to a great variety of input streams, through straightforward pro-gramming of the detection logic 25 and of the processor 26.
This module is therefore particularly suitable for a modular architecture of the device. In the case of an input stream of ES type, it makes it possible simultaneously to carry out the two phases of forming packets (PES and TP) by means of a single processor, the PES header being regarded as an extension of the TP header. It is also suitable for input streams of the TS or PS type, in remultiplexing applications.
The building of a packet is carried out in parallel with the transfer of the data of the previous packet to the memory PMi, this making it possible to process sizeable CA 02203787 1997-04-2~

input bit rates. The transfer is entrusted to a separate sequencer, this making it possible to free the single processor of the packetizing module for the other processing operations to be performed.
Another task executed by the processor 26 is the computation of the parameters associated with the packets and their writing to the parameter memory ZMi. These parameters comprise election parameters allowing the multiplexing module 14 to select the packet memories for the transfer of the packets to the output of the device. Thus, some of the tasks which are customarily incumbent on the multiplexing module are transported to the packetizing modules. The extra burden on the processor 26 is however sufficiently slight as to have no signlficant impact on the choice of this processor which is in any case necessary for packetization.
In order to approach an optimal time distribution at output, it is necessary to know:
- the packets which are able to exit immediately and the maximum delay which may be allocated to them, - the packets which will be able to exit soon and the time by which their transmission may be brought forward.
One solution for affording the multiplexing module 14 an insight regarding this broadcast information is to require the packetizing modules to associate three election parameters with each packet writter. to the buffer memory PMi, each parameter corresponding to a time expressed with CA 02203787 1997-04-2~

respect to a time base common to the packetizing and multiplexing modules. These three parameters are the minimum time Tmin, the maximum time Tmax and the ideal time Tideal of transmission of the packet with which they are associated.
Each processor 26 managing an elementary stream therefore defines a time window for the transmission of each packet created, and is free to adapt the width of this window to the nature of the stream which it manages.
Furthermore, to aid the multiplexing module 14 in its task and to allow it to generate a quality stream, it defines an ideal position of the packet in its window. Management of the parameters Tmin, Tmax and ~ideal is specific for each type of input stream.
In the case in which the input stream is an elementary stream (ES, PES or data), the minimum time of transmission Tmin is computed by adding a latency time T1 to the time of input Te of the data of the packet to the input buffer 20 of the packetizing module, and the difference Tmax - Tmin between the maximum time and the minimum time of transmission is computed as a function of the type of elementary stream and of the bit rate of this stream. If the source of the elementary stream has a regular bit rate, the input time Te is deduced in a simple manner by the processor 26 from the time of transit of the data through the detection circuit 22. If the source of the elementary stream has a spasmodic bit rate, the input time can be retrieved from a bit rate cue received from the upstream coder or read from the stream. The latency time T1 is a programmable time intended to delay the transmission of certain streams with respect to others. The width of the window Tmax - Tmin is taken smaller for temporal streams, especially video streams, than for streams having no very precise retransmission constraint, such as EMM conditional access data streams. The difference Tmax - Tmin is moreover a decreasing function of the bit rate of the elementary stream.
In the case of a multiplexed input stream of the transport stream type, the minimum time Tmin of retrans-mission of a packet is computed as a function of the time of input Te of the packet to the module and of a latency time T1 as in the previous case, and moreover as a function of the strategy which the previous multiplexer had adopted.
This strategy is indicated in the LTW fields of the TP
headers of the stream or in the descriptor fields, these fields being readable by the processor 26 by way of the detection circuit 22. The minimum time computed Tmin is for example delayed, with respect to Te + T1, by the time corresponding to the window offset (LTW_offset) read from the stream. In the case of a multiplexed input stream, the maximum time of retransmission Tmax is computed as a function of the type of stream. For most elementary streams of a transport stream, the difference Tmax -Tmin is taken equal to 4 ms. However, for certain particular cases, this difference may be increased in order to lighten the constraints of the multiplexing module.
The ideal time of transmission of a packet is obtained as a function of the multiplexing strategy adopted for the elementary stream containing this packet. This time Tideal can be defined by an offset with respect to the minimum time Tmin, this offset being fixed or else proportional to the width Tmax - Tmin of the transmission window. An "early" strategy corresponds to a time Tideal which is relatively close to the minimum time Tmin. Such a strategy favors the coder or the multiplexer located upstream, which can have an output buffer memory of reduced size. A "late" strategy corresponds to a time Tideal which is relatively distant from the minimum time Tmin. Such a strategy favors the decoder or the remultiplexer located downstream in the sense that its input buffer memory can be of reduced size. There is a complete range between the "early" and "late" strategies.
In a typical embodiment, the election parameters stored in the parameter memories ZMi are the ideal transmission time Tideal coded on 20 bits, the difference Tideal - Tmin coded on 15 bits, and the difference Tmax -Tideal coded on 15 bits, each expressed with respect to a 90 kHz reference clock. These parameters are stored at an address tied to the address of the associated packet in the memory ~Mi.
The parameters associated with a packet and stored CA 02203787 1997-04-2~

in the parameter memories ZMi furthermore comprise modification parameters allowing the multiplexing module 14 to update the header of the packet as a function of its time of transmission when necessary. These modification parameters comprise for example:
- bits indicating the presence or absence, detected by the logic 25, of a PCR-type field or of an LTW-type field, which can only be updated when the exact output time of the packet is known, requiring very precise time references. In the case of a PCR-type field whose position is fixed with respect to the beginning of the packet, one bit suffices to indicate whether such a field is present in the packet. In the case of an LTW-type field, whose position can vary, the modification parameters furthermore indicate the position of this field in the packet;
- size of the data part (payload) of the packet.
This information is useful in the case in which the multiplexing module 14 furthermore carries out scrambling of the packet;
- packet identification parameter PID. This information, useful in remultiplexing applications, allows the multiplexing module 14 to ascertain whether it is required to change this parameter (the case in which the same identification parameter PID is allocated to several elementary streams contained in the input streams).
An architecture of the multiplexing module 14 is represented in the diagram of Figure 6. This module CA 02203787 1997-04-2~

comprises on the one hand a microprocessor 40 and an election circuit 42 which process the data contained in the parameter memories ZMi, and on the other hand a transfer sequencer 44 which controls the transfers of packets from the packet memories PMi to the output buffer 46 of the device. It will be understood that the multiplexing module 14 could comprise yet other elements, for example in order to scramble the packets transferred before writing them to the output buffer.
The multiplexing module 14 furthermore comprises an additional packet memory PM0 and an associated parameter memory ZM0. The memory PM0 contains information packets specific to the programs carried by the output multiplex (PSI), which specify among other things the identification parameters PID of the streams of each program (see chapter 2.4.4 of the document ISO/IEC 13818-1). These packets PSI
are written to the memory PM0 by a source (not represented) also belonging to the multiplexing module 14. Election parameters associated with these packetsi Tmin, Tmax, Tideal, are also written to the memory ZM0 by this source.
The time constraints of the PSI packets not being very severe, the time window of transmission of these packets may be taken relatively wide.
From the viewpoint of the multiplexing module 14, the packet memories PM0, PM1, ..., PMm are regarded as a single addressing space. Likewise, the parameter memories ZM0, ZM1, ..., ZMm are regarded in respect of reading as a CA 02203787 1997-04-2~

single addressing space. Figure 6 shows the data bus lOD and the address bus lOA included within the packet bus 10. These two buses lOA, lOD are linked respectively to the address and data inputs of each of the packet memories PMi. The addresses on the bus lOA are generated by the transfer sequencer 44 under the supervision of the processor 40. The data bus lOD is also linked to the input of the output buffer 46 where the writing of the data is controlled by the sequencer 44.
Figure 6 also shows the data bus 12D and the address bus 12A which are supervised by the processor 40 and are included in the parameter bus 12. These two buses 12A, 12D
are linked respectively to the address and data inputs of each of the parameter memories ZMi. The packet bus 10 and parameter bus 12 are linked together by a three-state gate 48 allowing the processor 40 to ta.ke comma.n.d of the packet bus 10. To order the sequencer 44 to trar.sfer a transport packet of 188 bytes to the output buffer, the processor 40 presents a start address on the address bus 12A. This start address is transmitted to the bus lOA by the gate 48, and the address counter of the sequencer 44 is initialized to the value of this start address, and is then incremented until the 188 bytes of the packet are transferred.
The address buses lOA, 12A are wice enough for the packet memories PMi and parameter memories ZMi to be seen as a single addressing space by the processor 40. Address buses of 24 bits are suitable for a multiplexer or remultiplexer of large capacity (m <128 for example). To enhance output speed, the data buses lOD, 12D can be 16-bit buses transferring two bytes simultaneously.
The sequencer 44 is separated from the processor 40 so as to allow the processor 40 and the circuit 42 to perform the processing operations relating to the transmis-sion of a packet in the multiplex while the previous packet of the multiplex is being transferred under the control of the sequencer. This allows the multiplexing module 14 to adapt to the large transmission bit rate required by the MPEG2 standard.
The processing operations performed before the transfer of a packet comprise:
- selection of the packet memory PMi from which this packet will be read and determination of the start address to be supplied to the sequencer 44 to ensure the transfer of this packet;
- analysis of the modification parameters relating to the elected packet and possible modification of the corresponding fields.
A signal CK for clocking the output multiplex is received by the processor 40 from the equipment located downstream of the device. The processor 40 computes the time Ts of transmission of the next packet on the basis of this signal CK.
The choice of the packet memory from which the next packet will be extracted is made on the basis of this CA 02203787 1997-04-2~

transmission time Ts and the election parameters Tmin, Tmax, Tideal present in the first positions of the parameter memories ZMi, that is to say election parameters associated with the first packets waiting in each of the packet memories PMi.
Annex 1 presented at the end of the present description gives an example of an election algorithm in the C language usable to select the packet memories from which to extract the packets of the multiplex. In the notation of annex 1, nb_sources corresponds to the number of packet memories attachable to the packet bus 10 (nb_sources = m +
1 when the totality of the capacity of the multiplexing module 14 is used), valid_TP_flag[] is a table of length nb_sources which consists of boolean variables such that valid_TP_flag[current_channel] is true if a packet memory PMi is actually attached to the position current_channel and if this packet memory contains at least one packet awaiting transfer, the tables Tmin[], Tmax[] and Tideal[] contain the election parameters of the first packets waiting in each packet memory, current_priority is a priority coefficient computed for the first packet waiting in the memory PM(current_channel), and elected_TP_priority is the priority coefficient maximized by the election algorithm, corresponding to the elected packet contained in the memory PM(elected_TP_channel).
A priority coefficient of -1 is allocated to a stuffing packet stored, for example, in the memory PM0 at an CA 02203787 1997-04-2~

address to which is allocated a memory number equal to -1.
This stuffing packet is selected by default if no packet memory contains a packet having attained its minimum transmission time Tmin. No packet may normally be transmitted after its maximum time Tmax, given that the device is sized so that the sum of the bit rates of the input streams is less than the bit rate of the output stream.
Figures 7 and 8 show the variations in the priority coefficient of a packet having a given transmission window [Tmin, Tmax] versus the transmission time Ts in the case of an "early" strategy (Figure 7) and in the case of a "late"
strategy (Figure 8). It may be seen that for a given transmission time and identical windows, the election algorithm favors the streams for which an "early" strategy has been defined.
The election algorithm presented in annex 1 can be implemented by the processor 40 while the previous packet of the multiplex is being transferred. In this case, the processor 40 has to perform reads from the parameter memories ZMi and then execute the algorithm. These tasks require a not-insignificant processor time. This is why, in applications at high bit rate, the use of a separate election circuit 42, as illustrated in Figure 6, is preferred. A hard-wired circuit 42 makes it possible to perform election faster than a processor, and relieves the processor 40 of the corresponding computations.

CA 02203787 1997-04-2~

The multiplexing module 14 comprises a dual-port memory 50 linked to the parameter bus 12 so as to supply the parameters which are useful to the election circuit 42. The election parameters Tideal, Tmax - Tideal and Tideal - Tmin associated with the first packet waiting in each packet memory PMi are read by the processor 40 from the corresponding parameter memory ZMi and are written to the memory 50 at an address ADD equal to the packet memory number. Also written to the memory 50 by the processor 40 are bits BM corresponding to the boolean varlables valid_TP_flag defined previously: BM = 0 if no packet memory is attached to the position corresponding to the address ADD
or if the packet memory attached to the position corres-ponding to the address ADD contains no waiting packet at the relevant instant.
Figure 9 is a diagram of a hard-wired election circuit. This circuit 42 comprises a register 52 to which the value of the next transmission time Ts is written by the processor 40. A sequencer 54 supervises the operations performed by the circuit 42 in response to an election command EC received from the processor 40. The sequencer 54 commences by initializing to the value -1 (stuffing packet by default) the contents of two registers 56, 58 the one intended to contain the address ADDS corresponding to the packet memory selected and the other the corresponding priority coefficient PRI0. The sequencer 54 next generates commands to read from the work memory 50. At each read CA 02203787 1997-04-2~

cycle, the sequencer 54 increments by one unit an address counter delivering the read address, so as sequentially to read the parameters BM, Tideal, Tmax - Tideal and Tideal -Tmin which relate to the various possible addresses. The election circuit 42 comprises a subtractor 60 receiving on its positive input the transmission time Ts emanating from the register 52 and on its negative input the ideal time Tideal emanating from the memory 50. The sign bit of the output of the subtractor 60 controls a multiplexer 62 one input (positive sign) of which receives the parameter Tmax -Tideal from the memory 50 and the other input (negative sign) of which receives the parameter Tideal - Tmin from the memory 50. A divider 64 calculates the quotient between the output from the subtractor 60 and the output from the multiplexer 62. The priority coefficient of the current packet thus supplied by the divider 64 is addressed to an input of a comparator 66 whose other input receives the contents of the register 58. An AND gate 68 receives on the one hand the bit BM relating to the current packet, and on the other hand the comparison bit produced by the comparator 66. This comparison bit is equal to 1 if the computed priority coefficient of the current packet is larger than that recorded in the register 58 and 0 otherwise. For synchronism purposes, a shift register 70 delays the bit BM
addressed to the AND gate 68 by a number of cycles equal to that required for the calculations performed by the elements 60 to 66. The address ADD generated by the sequencer 54 is CA 02203787 l997-04-2 addressed to the register 56 after having been passed through a shift register 72 which delays it by the same number of cycles. The priority coefficient produced by the divider 64 is addressed to the register 58. The cycle clock CCK is supplied by the sequencer 54 to the registers 56 to 58 with a view to their updating, but this updating is performed only on condition that the output from the AND
gate 68 is at 1.
The circuit 42 described above makes it possible to execute the election algorithm of annex 1 in a very short time. Once the election circuit has scanned all the possible addresses, the address ADDS corresponding to the memory PMi at which the next packet will have to be read is available in the register 56. The processor 40 can then read this register 56 by way of the parameter bus 12.
Once the processor 40 knows thereby the selected packet memory PMi, it undertakes the following operations:
- the modification parameters of the selected packet are read from the associated parameter memory ZMi;
- the processor 40 analyzes these modification parameters and, if necessary performs the corresponding modifications of the packet in the memory PMi. To modify a packet, the processor 40 takes command of the packet bus 10 via the gate 48. The modification addresses are deduced from the number of the selected memory and the modification parameters. The temporal data to be modified (PCR or LTW) are so as a function of the previously computed transmission time Ts. If it is necessary to modify identification fields PID, the processor 40 uses the output multiplex mapping data (PSI). While the processor 40 takes command of the packet bus 10, the sequencer 44 interrupts the transfer of the packet in progress;
- the processor 40 determines, as a function of the number ADDS of the selected packet memory, the start address to be supplied to the transfer sequencer 44 for the transfer of the next packet of the multiplex OS; the processor determines this start address in such a way as to comply with the order of input of the packets into each packet memory;
- the election parameters of the packet which came in second position in the selected memory PMi are read from the associated parameter memory ZMi and written to the work memory 50 at the corresponding address; if there is no such second packet, the corresponding bit B~ is set to 0 in the work memory 50;
- the processor 40 computes the transmission time Ts of the following packet and supplies it to the election circuit 42 as also the following election command EC.
Of course, the processor 40 can also fulfill other functions which are not detailed here since they do not relate directly to the present invention.
The proposed organization of the multiplexing module is well suited to the constraints imposed by the MPEG2 system standard.

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The packetizing modules supply the multiplexing module with the information affording it the possibility of arriving at an optimal distribution of the packets over time, by giving it not only the ideal time of broadcast of each packet, but also the minimum time and the maximum time which make it possible to comply with the input buffers of a decoder located downstream.
The multiplexing module does not have to know the multiplexing characteristics of the sources which it manages (bit rate, critical multiplexing factor). A generic multiplexing card may therefore be defined which covers the multiplexing aspects proper and also remultiplexing aspects, this permitting very considerable flexibility.
The multiplexing processor is relieved so as to cope with the management of configurations which are unwieldy in terms of the number and bit rate of elementary streams, without needing prohibitive computational power. The multiplexing process is very systematic and can in part be installed in very fast hard-wired logic such as the election circuit 42.
The number m of elementary streams which can be managed is limited only by the width of the address buses of the multiplexing module. This permits great flexibility, since packetizing modules can easily be added to or removed from the multiplexing module. The device configures itself when powered up and ascertains how many packetizing modules are present, and to which addresses on the packet bus and on CA 02203787 1997-04-2~

the parameter bus they will write their data.
The parameters required for election and for modification of the packets are identical irrespective of the type of stream managed by the packetizing module. The multiplexing module therefore ignores the nature of the streams which it multiplexes. It ascertains simply how many sources of transport packets are connected to it, and it works systematically (and hence faster). In the proposed organization, each packet of each source waiting in the packet memory space has available an associated area in the parameter memory space.
A variant embodiment of the device of Figure 1 is shown in Figure 10. In this variant, the interface between the packetizing modules C1, ..., Cn and the multiplexing module 14 comprises packet memories PM1, ..., PMm, memories ZM1, ..., ZMm for receiving the election parameters of the packets and memories YM1, ..., YMm for receiving the modification parameters of the packets. Each packetizing module therefore writes the modification parameters to a memory YMi also associated with the packet memory PMi, but distinct (at least as regards addressing) from the election parameter memory ZMi. The bus 12 which allows the multiplex-ing module 14 to see the collection of memories ZMi as a single addressing space serves in this variant merely for the reading of the election parameters. A similar bus 16 is provided between the multiplexing module 14 and the memories YMi in order to read the modification parameters. The CA 02203787 1997-04-2~

memories YMi are therefore also seen as a single addressing space by the multiplexing module. This architecture allows the processor of the multiplexing module to perform the modification of one or more elected packets while the election circuit selects a packet memory for a following packet of the output multiplex OS, it being observed that several packets can be elected in advance, it being possible for the packet transmission times Ts to be brought forward.
For example, while packet N exits the output buffer, packet N+1 can be written to the output buffer, packet N+2 can be modified in its packet memory and packet N+3 can be elected.
By thus increasing the parallelization of the operations, it is possible to accommodate even higher output bit rates.

A~NEX 1 int election (int Ts, nb_sources,valid_TP_flag[~, Tmin[], Tideall], ~ ( ] ) {

int current_ehAnnel, eleet-d_TP_chAnnel;
float eurrent priority, eleeted_TP_priority;
/ initialization of the eleeted TP to its default value:
stuffing ~ac~et with a ~riority of -1 /
elected_TP_~-hAnn-l ~ -1;
eleeted_TP_priority ~ -1.0;
/ main loop for seAnn~ng t_e sourees for (eurrent_ehAnnel~0; eurrent_ehannel<nb_sourees;

current_chAnnel~ ~ ) if (valid TP_flagleurrent_channel~) {

/ calculate the ~riority of the current TP
if (Tideal[eurrent_chAnnel3 <~ Ts) eurrent_priority ~ (Ts-Tideal leurrent_ehannel~)/
(Tmaxleurrent_~hAnnel]-T~dealleurrent_ch~nnel]);
else curr-nt_~riority ~ (Ts-Tideal leurrent_rhAnn-l])/
(Tidealleurrent_ehAnnel]-Tmin[eurrent_ehAnnel]);
/ eomparison of the eleeted TP and the current TP
if (current_priority > elected_TP_priority) { / updating of the ~arameters of the eleeted TP
elected_TP_~riority ~ eurrent_priority;
eleeted_TP_chAnnel r eurrent_ehAnnel;

}
}

return eleeted_TP_chAnnel;

Claims (10)

1. Device for producing a time multiplex of digital information packets, comprising several packetizing modules (C1, C2, ..., Cn) each receiving a digital input stream (IS1, IS2, ..., ISn), several packet memories (PM1, PM2, ..., PMm) each receiving packets emanating from a respective packetizing module, and multiplexing means (14) selecting the packet memories from which the packets of the multiplex are to be extracted and successively transferring said packets to an output of the device, characterized in that at least one packetizing module comprises:
- an input buffer (20) receiving the input stream;
- a detection circuit (22) linked to the output of the input buffer so as to detect synchronization words of the input stream;
- a storage unit (23) successively receiving the bytes of the input stream which have been presented to the detection circuit (22);
- transfer means (32) for transferring bytes from the storage unit (23) to a packet memory (PMi); and - a processor (26) for determining the headers of the packets constructed from the input stream on the basis of the synchronization words detected by the detection circuit (22), writing these headers to the packet memory (PMi) and controlling the transfer means (32), and in that the storage unit (23) is organized in first-in, first-out mode so as to contain at each instant K-k bytes of the input stream, K denoting the number of bytes of a packet of the output multiplex and k denoting the minimum number of bytes of the packet headers, and so that the transfer of a byte from the storage unit (23) to the packet memory (PMi) is accompanied by the transfer of another byte from the detection circuit (22) to the storage unit (23), so that all the bytes of the input stream which may be introduced into a packet are presented to the detection circuit (22) before the writing of this packet to the packet memory commences.

2. Device according to claim 1, characterized in that the processor (26) of a packetizing module computes the number of bytes L of the header of a packet according to the detections of synchronization words performed by the detection circuit (22) while the bytes of a previous packet emanating from the input stream are transferred from the storage unit (23) to the packet memory (PMi), and controls the transfer means (32) so as subsequently to transfer the K-L bytes of the input stream to be included within said packet.

3. Device according to claim 1 or 2, characterized in that, in order to process a raw elementary stream (ES) emanating from an audio or video coder, the processor (26) of a packetizing module is devised so as to determine headers of a first packetizing layer (PES) and headers of a second packetizing layer (TP) on the basis of synchronization words of the elementary stream which are detected by the detection circuit (22), the packets written to the packet memory (PMi) each containing a header of the second layer, and the packets containing a header of the first layer each commencing with a composite header written by the processor (26) to the packet memory (PMi) and consisting of a header of the second layer, followed by said header of the first layer.

4. Device according to claim 3, characterized in that the processor (26) is devised so as to determine said composite headers in such a way that they each occupy the totality of a packet of K bytes.

5. Device according to claim 1 or 2, characterized in that in order to process an elementary stream packetized according to a first packetizing layer (PES), the processor (26) of a packetizing module is devised so as to determine a header of a second packetizing layer (TP), inserted at the beginning of each packet written to the packet memory (PMi) on the basis of synchronization words included within the headers of the first layer and detected by the detection circuit (22), the detection circuit (22) further supplying the processor (26) with an indication of the number of bytes L' of each header of the first layer in such a way that the processor (26) determines a header of the second layer of K-L' bytes for the packet containing this header of the first layer.

6. Device according to any one of the preceding claims, characterized in that the detection circuit (22) comprises a programmable gate array.

7. Device according to claim 6, characterized in that the detection circuit (22) comprises a shift register (24) having a length of k bytes, placed between the output of the input buffer (20) and the input of the storage unit (23), and programmable detection logic (25) receiving the k bytes present in the shift register (24) and indicating to the processor (26) the detections of synchronization words.

8. Device according to any one of the preceding claims, characterized in that the processor (26) of a packetizing module is further devised so as to compute parameters associated with each packet written to a packet memory (PMi) and so as to write these parameters into at least one parameter memory (ZMi; YMi) associated with said packet memory.

9. Device according to claim 8, characterized in that the parameters associated with a packet comprise election parameters allowing the multiplexing means (14) to select the packet memories, and/or modification parameters indicating to the multiplexing means (14) whether they have to modify one or more determined portions of the packet before transferring this packet to the output of the device.

10. Device according to claim 8 or 9, characterized in that the multiplexing means (14) are linked to the packet memories by a common packet bus (10) in such a way that the packet memories (PMi) constitute a single addressing space for the multiplexing means, and in that the multiplexing means (14) are linked to the parameter memories (ZMi) by a common parameter bus (12) in such a way that the parameter memories constitute a single addressing space for the multiplexing means.