JPH10243394A - Mpeg data processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a moving picture expert group(MPEG) data processing circuit with which a system also corresponding to an MPEG2 program stream(PS) can be easily constructed without changing the basic circuit configuration of an MPEG data processing circuit prepared for processing an MPEG2 transport stream(TS). SOLUTION: The MPEG2-TS is fetched from a host bus by a host bus control part 1, stored through a selector 7 into a first-in/first-out FIFO 8 and converted later to video and audio signals by a TS separating part 9 and an A/V decoder 10. In the case of MPEG2-PS, it is fetched from the host bus, afterwards, a packetized elementary stream(PES) and a system clock reference(SCR) are separated by a PS separating part 3, the separated PES and a program clock reference(PCR) generated by a PCR generating part 5 are reprogrammed into MPEG2-TS by a TS programming part 3, stored in the FIFO 8 and converted to video and audio signals by the TS separating part 9 and the A/V decoder 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an MPEG data processing circuit, and more particularly to an MPEG data processing circuit capable of decoding an MPEG2 program stream in addition to an MPEG2 transport stream.

[0002]

2. Description of the Related Art International standards for digital video (video) encoding (compression), audio (audio) encoding and multiplexing / demultiplexing methods include storage media,
MPEG commonly used in fields such as communication and broadcasting
(Moving Picture Experts G
group) (ISO / IEC DIS 13818)
-1 to 3). This MPEG standard includes CD-RO
M (Compact Disk Read Only)
Memory used in storage media such as
In addition to G1 and this MPEG1 application, multimedia,
There is MPEG2, which is a highly efficient encoding technique for data.

[0003] Similar to MPEG1, MPEG2 has an MPEG2 program stream (PS: Pr) that can form one program in a stream.
MPEG2 transport stream (TS: Transport Stream; TS) as a multiplexing / demultiplexing method corresponding to a multi-program capable of composing (transmitting) a plurality of programs in a stream together with an "ogram Stream;
"MPEG2-TS").

[0004] In particular, the MPEG2-TS can convert a plurality of programs into one stream, so that it can be used for television broadcasting and the like, and has a degree of freedom in program organization and a scramble function.

FIG. 6 is a block diagram showing a configuration of an encoding part in an MPEG system. This system converts video data (VD) captured and digitized from an image input device and audio data (AD) captured and digitized from an audio input device into an MPEG2 program stream (PS) or an MPEG2 transformer. This is converted into a port stream (TS). The handling of the MPEG1 stream is the same as that of the MPEG2 program stream.
The PEG2 program stream will be described.

In the encoding process in the MPEG system, digitized video data (VD) and audio data (AD) are separately encoded (compressed) by a video encoder 21 and an audio encoder 22, respectively. . Encoded video data (VE) and encoded audio data (AE)
Is called an “elementary stream”, header information is added to the elementary stream by the video packetizer 23 and the audio packetizer 24, respectively, and the “PES (Packetized Element)”
A packet called "entryStream; packetized elementary stream" is generated. In the PES packet structure, the header portion is slightly more complicated than the MPEG1 packet.

The MPEG2 program stream (P
S), the video PES packet (V-
PES) and audio PES packet (A-PES)
To the program stream multiplexer (PSM
(UX) 25 to add header information to form a stream.
On the other hand, MPEG2 transport stream (TS)
Is generated, the video PES packet (V-PE
S) and an audio PES packet (A-PES) into a transport stream multiplexer (TSM).
UX) 26 to make a stream in the same manner as the MPEG2 program stream.

At this time, a system reference time (STC: System Time Clock) on the encoder side
And information for matching the system reference time on the decoder side. In the MPEG2 program stream, this information is referred to as “SCR (System Clock)”.
k Reference; reference value of system time reference) ", for the MPEG2 transport stream,
“PCR (Program Clock Reference)
nce; program time reference value).

FIG. 3 shows a conventional MPEG2 format.
FIG. 2 is a block diagram showing a data flow in a system for decoding a program stream. It is assumed that the MPEG2 program stream is input through a host bus (HB). The bus control unit 6 controls the host bus (H
B), the MPEG2 program stream is fetched and the FIFO (First In First Out;
(First-in first-out buffer memory) 8.

The bus control unit 6 includes a host bus (HB)
A general-purpose LSI that controls the operation of the system, and an LSI that actually performs processing inside the system, for example, a PLD (Programmab)
leLogic Device; programmable logic device) and gate array (Gate Array)
y) and the like in many cases. The FIFO 8 buffers data sent from the bus control unit 6, and outputs the buffered data in order when necessary.

The FIFO 8 is for transferring PES format data to the A / V decoder 10 without delay when requested by the A / V decoder 10.
The FIFO 8 supplies the data stored in the FIFO 8 to the A / V decoder 10 even if the data from the host bus (HB) is interrupted on the way. For example, Japanese Patent Laid-Open Publication No. Hei 7-30886 describes a method of using a buffer to recover the reproduction of an MPEG bit stream even if the MPEG bit stream is lost.

The A / V decoder 10 is adapted for MPEG1, MP,
EG2 program stream, video and audio PES packet format data, unencoded video signal (VS) and audio signal (AS)
The output data of the FIFO 8 is input. A method for decoding MPEG video and audio data is described in, for example, Japanese Patent Laid-Open No. 7-5.
Reference is made to the description of JP 9084.

The above-described configuration of the MPEG decoding system is used for an MPEG decoder card mounted on a personal computer or a workstation.

FIG. 4 shows a conventional MPEG2 format.
FIG. 3 is a block diagram showing a data flow in a system for decoding a transport stream. MPEG2
The processing from the input of the transport stream via the host bus (HB) to the output of data from the FIFO 8 is the same as that of the program stream.
In the MPEG A / V decoder 10 that cannot decode the MPEG2 transport stream, as shown in FIG. Is input to an A / V decoder 10 capable of decoding. Such a configuration of the MPEG decoding system is used in a set top box (STB) used for broadcasting or the like.

There is currently no A / V decoder capable of processing both the MPEG2 program stream and the MPEG2 transport stream. For this reason, MPEG2-PS and M
MPEG processing both streams of PEG2-TS
To realize the decoder system, a configuration as shown in FIG. 5 is conceivable.

The system shown in the block diagram of FIG.
4 is a combination of the two methods described with reference to FIG. 4, and the data bus to be input to the A / V decoder 10 is divided into an MPEG2 program stream,
PS for PEG2 transport stream
-It is switched by the TS selector 11. That is, when it is desired to decode the MPEG2 transport stream, the PS-TS selector 11 is switched to the TS separation unit 9 side, thereby having the same configuration as that shown in FIG.
PES format data separated from the transport stream can be input.

On the other hand, when it is desired to decode the MPEG2 program stream, the PS-TS selector 11 is switched to the output side from the FIFO 8 so that
And the host bus (HB)
From the A / V decoder 10
Can be entered.

When the systems shown in FIG. 3 and FIG. 4 already exist, these systems are required to support the decoding of both the MPEG2 program stream and the MPEG2 transport stream.
A method of converting a PEG2 program stream or an MPEG2 transport stream into a stream format supported by each decoding system by software has also been considered.

In this case, the system shown in FIG.
Since the EG2 program stream is for storage media, it is not suitable for real-time transfer as performed in the MPEG2 transport stream. Also, MP
Since the EG2 transport stream does not support a plurality of programs as in the case of the EG2 transport stream, in order to support the MPEG2 transport stream in the configuration shown in FIG. After the data is stored in the apparatus, data converted into an MPEG2 program stream for each program by software is stored, and decoding is performed by this system.

In the system shown in FIG.
Similarly, when supporting the EG2 program stream, the MPEG2 program
The stream is once converted to an MPEG2 transport stream, and the converted data is stored on a magnetic disk or the like and input to a decoder.

[0021]

The above-mentioned conventional MPEs
The G data processing circuit has the following problems.

In the currently used MPEG decoding system, an MPEG2 program stream and an MP2
In order to realize a system that supports both streams of the EG2 transport stream, it is necessary to convert data to a stream format compatible with a decoding system by software, but the high speed defined by the MPEG2 standard is required. Data transfer rate, for example, MP ＠
ML (Main Profile Main Leave)
l) The processing speed is insufficient to support the maximum of 15 Mbps, real-time processing cannot be performed,
It causes obstacles such as distorted images.

As shown in FIG. 5, an MPEG2 transport stream and an MPEG2
When a system corresponding to both streams of the program stream is configured, the MPEG2 transport
The part that separates the PES from the stream and the part that decodes the MPEG2 program stream and the PES had to be separate.

Accordingly, the present invention has been made in view of the above-mentioned problems, and has as its object to provide an MPM made for processing an MPEG2 transport stream.
An object of the present invention is to provide an MPEG data processing circuit capable of processing MPEG2 program streams without changing the basic configuration of the EG data processing circuit.

[0025]

According to the present invention, there is provided an MPEG data processing circuit comprising: a PS separation unit for separating PES and SCR from an MPEG2 program stream; and a PES for buffering the separated PES.
A buffer, a PCR generation unit that counts and generates an amount of data for transferring a program time reference value (PCR) to be inserted into the MPEG2 transport stream;
It is characterized by including a TS organization unit that reads the ES and the PCR to generate an MPEG2 transport stream.

[0026]

Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, a bus control unit (6 in FIG. 1) for controlling data transfer to and from a host bus (HB) and a FIFO (FIG. 1) for temporarily storing data read from the host bus 1-8) and MP
EG2 transport stream to PES (Pac
Ketized Elementary Stream
m), and a decoder (10 in FIG. 1) for decoding video or audio data in PES packet format into a video signal and an audio signal, respectively. A bus control unit located before the unit is a PS separation unit for extracting a PES and a system time reference value (SCR) from an MPEG2 program stream input from the host bus (2 in FIG. 1).
And a buffer for storing the separated PES (4 in FIG. 1)
And a PCR generating means for generating a program time reference value (PCR) required for the MPEG2 transport stream by counting the data amount (5 in FIG. 1)
And a TS organizing means (3 in FIG. 1) for organizing and outputting an MPEG2 transport stream from the PES and the generated PCR, and input from the host bus via the host bus control unit (1 in FIG. 1). Selector for switching between data and data created by the TS organizing means (FIG. 1)
7).

In the embodiment of the present invention, MPEG2
The transport stream is taken in from the host bus by the host bus control unit (1 in FIG. 1), temporarily stored in the FIFO (8 in FIG. 1) through the selector, and
The signal is converted into a video signal and an audio signal by a separation unit (9 in FIG. 1) and a decoder (10 in FIG. 1).

On the other hand, in the case of the MPEG2 program stream, after being taken in from the host bus, the PES and SCR are separated by the PS separation means (2 in FIG. 1), and the separated PES and the PCR generated by the PCR generation means are separated. Is re-organized into an MPEG2 transport stream by the TS organizing means (3 in FIG. 1), stored in the FIFO 8, and
The signal is converted into a video signal and an audio signal by the separation unit and the decoder.

As described above, according to the preferred embodiment of the present invention, since the PCR of the MPEG2 transport stream is generated by counting the data amount in the PCR generation unit, clock generation using an oscillator or the like is performed. Compared with the device, accurate PCR values can be generated regardless of the accuracy of the device.

According to a preferred embodiment of the present invention, in the MPEG decoder card corresponding to only the MPEG-2 transport stream, the bus from the host bus control unit to the FIFO is a gate array (G).
ATE Array) and PLDs, which can be easily changed in design compared to the circuit board, make it possible to use the existing circuit board to replace the gate array or PLD.・ A system that can handle streams can be created.

[0031]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; First, an outline of an MPEG system using the MPEG data processing circuit of the present invention will be described, and then details of the MPEG data processing circuit will be described.

FIG. 2 shows an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of an MPEG decoding system using a G data processing circuit. MPEG
The decoding system is used in a computer, a set top box, or the like, and includes a CPU control unit 16, a communication card 17, a storage device 18, an MPEG card 19, a monitor 20, and a speaker 21.

The CPU controller 16, communication card 17, storage device 18, and MPEG card 19 are connected to a host bus (HB), and exchange data with each other. The communication card 17 includes an ATM (Asynchronous Tra).
A communication line (DC) for inputting data into the system through a communication line such as nsfer mode (asynchronous transfer mode) is connected. The video signal (VS) and the audio signal (AS) from the MPEG card 19 are connected to a monitor 20 for displaying and outputting an image and a speaker 21 for outputting audio, respectively.

As described above, the MPEG2 standard includes:
MPEG2 programs mainly used for storage media
Streams and MPEs for use in communications and broadcasting
There is a G2 transport stream. In the MPEG card 19, these MPEG bit streams are decoded, and the video and audio are monitored by the monitor 20 and the speaker 21.
Output to

In this MPEG decoding system, M
A situation where a PEG2 transport stream is used is, for example, watching a broadcast serviced via a set top box. In this case, MP
The EG2 transport stream is a communication line (DC)
Through the communication card 17. This stream is transmitted to the MPEG card 19 via the host bus (HB).
, And a decoding process is performed.

In this MPEG decoding system, the situation where the MPEG2 program stream is used includes, for example, viewing contents recorded on a storage medium such as a CD-ROM. in this case,
Assuming that a CD-ROM is used for the storage device 18,
In response to a request from the user, the content stored in the storage device 18 is selected and read out, and the host bus (H
The data is input to the MPEG card 19 via B) and decryption processing is performed.

FIG. 1 is a block diagram showing the configuration of an MPEG data processing circuit according to one embodiment of the present invention. Referring to FIG. 1, the MPEG data processing circuit of the present embodiment includes a host bus (HB), a bus control unit 6 for controlling the inside of the MPEG data processing circuit, and temporarily reads data read from the host bus (HB). It comprises a FIFO 8 to be stored, a TS separation unit 9 for separating the PES from the MPEG2 transport stream, and an A / V decoder 10 for decoding video or audio data in the PES packet format into a video signal and an audio signal, respectively. It is configured.

This configuration is basically the same as the configuration of the prior art shown in FIG. The bus control unit 6 takes in the MPEG2 program stream from the host bus (HB) and sends it to the FIFO 8. From the FIFO 8, the data sent from the bus control unit 6 is output in order. T
The S separation unit 9 separates the PES format data from the MPEG2 transport stream, and inputs the PES format data to an A / V decoder 10 that can decode the PES format data.
The / V decoder 10 outputs a video signal (VS) and an audio signal (AS).

Referring to FIG. 1, in the present embodiment, the bus control unit 6 exchanges data with the host bus HB for the host bus control unit 1 and the PES and system time reference values (from the MPEG2 program stream). SC
R), a PES buffer 4 for buffering the separated PES, a PCR generation unit 5 for generating a program time reference value (PCR) required for the MPEG2 transport stream, and a PES. A TS knitting unit 3 for packetizing to create an MPEG2 transport stream; and a selector 7 for switching between data input from a host bus (HB) and data created by the TS knitting unit 3. I have.

In the bus controller 6, the host bus controller 1 uses a general-purpose bus controller chip corresponding to the host bus (HB), and the other parts are PLDs.
(Programmable logic devices) and gate arrays.

The host bus controller 1 controls the host bus (H
B), an MPEG stream is input, and this stream is sent to the PS separation unit 2 or the selector 7.

The data in the PES format separated by the PS separation unit 2 is stored in the PES buffer 4 and, when necessary,
It is read from the TS organization unit 3.

The SCR separated by the PS separation unit 2
Is input to correct the value of the PCR generator 5. Then, the PCR generated by the PCR generation unit 5 is input to the TS knitting unit 3 and the PS separation unit 2.

Next, the operation of the MPEG data processing circuit of this embodiment will be described.

First, the operation of the MPEG data processing circuit for decoding an MPEG2 transport stream will be described. The MPEG2 transport stream is sent to the FIFO 8 by the host bus control unit 1 through the host bus (HB). At this time, the selector 7 has been switched to the host bus control unit 1 because it is known in advance that the input data is an MPEG2 transport stream.

The FIFO 8 is provided to absorb the jitter of the input stream. The FIFO 8 buffers the data passing through the selector 7 in order, and transfers the data at a constant transfer rate determined by the system. It is sent to the separation unit 9. The MPEG2 transport stream input from the host bus (HB) is sequentially sent from the FIFO 8 to the TS separation unit 9, and the MPEG2 transport stream on the host bus (HB) is transmitted via a communication line or a host bus (HB). Due to the jitter generated in the data transfer in HB), data does not always flow at constant intervals. However, the data output from the FIFO 8 that absorbs the jitter of the input stream has the jitter absorbed and the data flows at a certain pace.

The TS separation section 9 performs processing for extracting PES format data from the MPEG2 transport stream.

FIG. 8 is a diagram showing a data structure of an MPEG2 transport packet. Referring to FIG.
In the PEG2 transport stream, one packet (transport packet) has 188 bytes (47 bytes).
.Times.4 bytes) (ie, AT
Considering the connectivity with M, the payload 48 of the ATM cell
Sequence of bytes, excluding 1 byte for synchronization 4
One PES format data is divided and stored in a plurality of transport packets. The adaptation field in the transport packet can optionally insert additional information and stuffing bytes for the individual stream,
This option field contains a PCR (program time reference value) and the like.

In the TS separation section 9, the divided PES
The data of the format is collected into one and passed to the A / V decoder 10. The A / V decoder 10 decodes the data in the PES format and decodes the video signal (VS) and the audio signal (AS).
Is output.

Next, the operation of the MPEG data processing circuit of this embodiment for decoding an MPEG2 program stream will be described. The MPEG2 program stream passes through the host bus (HB) to the PS
It is input to the separation unit 2. The PS separation unit 2 extracts a PES format data portion from the input stream,
It is stored in the ES buffer 4.

FIG. 7 shows the data structure of the upper layer of the MPEG2 program stream (MPEG2-PS). Referring to FIG. 7, a pack is generally composed of a plurality of packets, and the first pack is provided with an information group called a system header, which describes an overview of the entire stream (optional for second and subsequent packs). Is provided with an SCR (system time reference value) following the identification code for MPEG1 after the pack start code, followed by information indicating the bit rate of this stream.

The process of extracting the PES from the MPEG2 program stream first detects a pack header,
The system header length in the system header is checked, the length is skipped, and the data is transferred to the PES buffer 4 until the next pack header is detected.

The reference time when the time of the reference clock on the decoder side is matched with the time of the reference clock on the MPEG encoder side is SCR (System Clock Reference) in the case of the MPEG2 program stream.
nce; system time reference value), which is included in the pack header (see FIG. 7). According to the standard, this SCR is inserted into the stream once every 700 msec.

Similarly, in the case of an MPEG2 transport stream, a PCR (Program Clock) is used.
Reference (program time reference value) is included in the stream.
It must be in the stream once every 00 msec.

The PS separation unit 2 extracts the SCR from the MPEG2 program stream and sets the value in the PCR generation unit 5.

The PCR generator 5 is for generating a PCR to be inserted into the MPEG2 transport stream, and can be constituted by a logical stream counter. Here, the logical stream counter refers to an MPEG2 transport stream transfer rate and a data transfer amount that are known in advance.
2 is to calculate the PCR to be inserted into the transport stream.

The PCR generated by the PCR generation unit 5
The separation unit 2 monitors whether the wrapping is large. For example, in the case of performing a jump process for skipping the middle of the content, the information of the SCR is wrapped around the time of the skip (an error occurs). At this time, the SCR in the content is set in the PCR generator 5. Actually, SCR
Is set as it is or is set by adding a predetermined offset to the SCR in consideration of the delay time of the processing in the MPEG data processing circuit.

The TS knitting section 3 stores the buffered P
The data in the ES format is read, and a header of the MPEG2 transport stream is added to make a packet of 188 bytes. At this time, the PCR output from the PCR generation unit 5 is fetched at a pace of once or less every 100 msec and inserted into the MPEG-2 transport stream.

The selector 7 determines that the input data is MPE
Since it is known in advance that the stream is a G2 transport stream, it has been switched to the TS knitting unit 3 side.

The processing after the selector 7 is the same as the processing when the input is directly input from the host bus control unit 1 to the selector 7.

[0061]

As described above, according to the present invention,
The following effects are obtained.

(1) A first effect of the present invention is that a PCR value can be accurately generated.

The reason is that, in the present invention, the PCR is generated based on the data transfer amount and the transfer rate. For this reason, in the present invention, MPE
The setting of the reference time on the G encoder side and the decoder side is MP
Only the error generated in the reference clock generation circuit on the EG encoder side is obtained.

(2) The second effect of the present invention is that even if the MPEG decoder chip does not support the MPEG2 program stream, the MPEG decoder chip supports both the MPEG2 transport stream and the MPEG2 program stream. That is, a decoder system can be constructed.

The reason is that, in the present invention, MPEG
This is because the two program streams are converted to the MPEG2 transport stream.

(3) A third effect of the present invention is that, even when the TS separation section and the A / V decoder are configured on one chip, an MPEG decoding system corresponding to the MPEG2 program stream is constructed. That you can do it.

The reason is that, in the present invention, an MPEG2 program stream is converted into an MPEG2 transport stream at a stage prior to the TS separation section.

(4) The fourth effect of the present invention is that the existing MP
In an EG2 transport stream compatible system, M compatible with MPEG2 program stream
This means that a PEG decoding system can be easily constructed, and it is easy to modify an existing system.

The reason for this is that, in the present invention, the parts constituting the circuit using the PLD and the gate array
This is because a conversion unit for converting an EG2 program stream into an MPEG2 transport stream is provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an MPEG data processing circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a system configuration to which an MPEG data processing circuit according to one embodiment of the present invention is applied;

FIG. 3 is a block diagram showing a configuration of a conventional MPEG data processing circuit corresponding to only an MPEG2 program stream.

FIG. 4 is a block diagram showing a configuration of a conventional MPEG data processing circuit corresponding to only an MPEG2 transport stream.

FIG. 5: MPEG2 program stream and MP
Conventional M for EG2 transport stream
FIG. 3 is a block diagram illustrating a PEG data processing circuit.

FIG. 6 is a block diagram illustrating a configuration of an MPEG encoder system.

FIG. 7 is a configuration diagram schematically showing an MPEG2 program stream.

FIG. 8 is a configuration diagram showing an outline of an MPEG2 transport stream.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host bus control part 2 PS separation part 3 TS organization part 4 PES buffer 5 PCR generation part 6 Bus control part 7 Selector 8 FIFO 9 TS separation part 10 A / V decoder 11 PS-TS selector 16 CPU control part 17 Communication card 18 Storage device 10 MPEG card 20 Monitor 21 Speaker AD audio data AE Audio elementary stream A-PES Audio PES AS Audio signal HB Host bus PCR Program time reference value SCR System time reference value VD Video data VE Video data Elementary stream V-PES video PES VS video signal

Claims (4)

[Claims] 1. An MPEG2 program stream to P
ES (Packetized Elementary)
Stream; a packetized elementary stream) and a system time reference value (System
A clock reference; a system clock reference (hereinafter referred to as “SCR”); a PES buffer for buffering the PES separated by the PS separation means; and a program time reference to be inserted into the MPEG2 transport stream. Reference value (Program Clock
Reference: a program clock reference (hereinafter referred to as “PCR”) generated by counting the amount of data to be transferred, and a TS organizing unit that reads the PES and the PCR to generate an MPEG2 transport stream. An MPEG data processing circuit, comprising: 2. A first-in, first-out memory (referred to as a "FIFO") for temporarily storing data read from a host bus, and a PES (PFI) from an MPEG2 transport stream.
acknowledgmented Elementary Stream
m: a packetized elementary stream), and a decoder for decoding video or audio data in the PES packet format into a video signal and an audio signal, respectively. After being fetched from the host bus and stored in the FIFO,
The MPEG2 program stream is converted into a video signal and / or an audio signal by the TS separation unit and the decoder, and the PES is separated from the MPEG2 program stream after being taken from the host bus. Program clock reference value generated based on the program clock reference
rence, referred to as “PCR”) and re-organized into an MPEG2 transport stream,
The MPEG data processing circuit is configured to be stored in a video signal and / or converted into a video signal and / or an audio signal by the TS separation unit and the decoder. 3. A system time reference value (S) from the MPEG2 program stream together with the PES.
system Clock Reference; "SC
R ”) is extracted and the PCR is performed in the SCR.
3. The MP according to claim 2, wherein the value of
EG data processing circuit. 4. A host bus control unit for controlling transmission / reception of data to / from a host bus, a first-in first-out memory for temporarily storing data read from the host bus, and a PES (P
acknowledgmented Elementary Stream
m), and a decoder for decoding video or audio data in the PES packet format into a video signal and an audio signal, respectively, and a signal input from the host bus at a stage preceding the first-in first-out memory. MPEG2 program stream to PE
S and the system time reference value (System Cl
means for extracting an OCK Reference (referred to as "SCR"), a buffer for storing the extracted PES, and a program time reference value (Program Clock R) required for the MPEG2 transport stream.
reference; referred to as “PCR”) by counting the amount of transferred data, and
PCR generating means for correcting the value by R; MPEG2 transport from the PES stored in the buffer and the PCR generated by the PCR generating means.
Transport stream organizing means for organizing and outputting a stream; and switching between data input from the host bus via the host bus control unit and data created by the transport stream organizing means. An MPEG data processing circuit, comprising: