CA2202003A1 - Method for production of soi substrate by pasting and soi substrate - Google Patents

Method for production of soi substrate by pasting and soi substrate

Info

Publication number
CA2202003A1
CA2202003A1 CA2202003A CA2202003A CA2202003A1 CA 2202003 A1 CA2202003 A1 CA 2202003A1 CA 2202003 A CA2202003 A CA 2202003A CA 2202003 A CA2202003 A CA 2202003A CA 2202003 A1 CA2202003 A1 CA 2202003A1
Authority
CA
Canada
Prior art keywords
substrate
soi substrate
pasting
production
possessing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2202003A
Other languages
French (fr)
Other versions
CA2202003C (en
Inventor
Kenji Yamagata
Takao Yonehara
Tadashi Atoji
Kiyofumi Sakaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2202003A1 publication Critical patent/CA2202003A1/en
Application granted granted Critical
Publication of CA2202003C publication Critical patent/CA2202003C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

This invention solves the problem of a pasted SOI
substrate generating voids in the peripheral part thereof and consequently decreasing the number of devices to be derived therefrom.
It concerns a method for the production of a SOI
substrate obtained by pasting a first Si substrate possessing a SiO2 surface and a second substrate possessing a Si surface on the SiO2 surface and the Si surface, which method comprises washing the Si surface of the second Si substrate thereby imparting hydrophobicity to the Si surface before the first Si substrate and the second Si substrate are pasted together.
CA002202003A 1996-04-08 1997-04-07 Method for production of soi substrate by pasting and soi substrate Expired - Fee Related CA2202003C (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP8518796 1996-04-08
JP8-085187 1996-04-08
JP9079783A JPH09331049A (en) 1996-04-08 1997-03-31 Method for manufacturing bonded SOI substrate and SOI substrate
JP9-079783 1997-03-31

Publications (2)

Publication Number Publication Date
CA2202003A1 true CA2202003A1 (en) 1997-10-08
CA2202003C CA2202003C (en) 2001-02-20

Family

ID=26420778

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002202003A Expired - Fee Related CA2202003C (en) 1996-04-08 1997-04-07 Method for production of soi substrate by pasting and soi substrate

Country Status (8)

Country Link
US (1) US6156624A (en)
EP (1) EP0801420A3 (en)
JP (1) JPH09331049A (en)
KR (1) KR100235398B1 (en)
CN (1) CN1099699C (en)
CA (1) CA2202003C (en)
SG (2) SG80064A1 (en)
TW (1) TW337042B (en)

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JP2000315635A (en) * 1999-04-30 2000-11-14 Mitsubishi Materials Silicon Corp Silicon wafer for bonding and manufacture of bonded substrate using the same
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US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6563133B1 (en) 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US20050226993A1 (en) * 2000-10-03 2005-10-13 Nawrocki Jesse G Medical devices having durable and lubricious polymeric coating
KR100418241B1 (en) * 2001-03-23 2004-02-11 주영창 Reversible Seal Package for Micro Electro Mechanical Systems
JP4628580B2 (en) * 2001-04-18 2011-02-09 信越半導体株式会社 Manufacturing method of bonded substrate
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
FR2851846A1 (en) * 2003-02-28 2004-09-03 Canon Kk CONNECTION SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE
JP2004335642A (en) * 2003-05-06 2004-11-25 Canon Inc Substrate and manufacturing method thereof
WO2004099473A1 (en) * 2003-05-06 2004-11-18 Canon Kabushiki Kaisha Semiconductor substrate, semiconductor device, light emitting diode and producing method therefor
US20050124137A1 (en) * 2003-05-07 2005-06-09 Canon Kabushiki Kaisha Semiconductor substrate and manufacturing method therefor
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
TWI242232B (en) * 2003-06-09 2005-10-21 Canon Kk Semiconductor substrate, semiconductor device, and method of manufacturing the same
JP2005005509A (en) * 2003-06-12 2005-01-06 Canon Inc Thin film transistor and manufacturing method thereof
US20050132332A1 (en) * 2003-12-12 2005-06-16 Abhay Sathe Multi-location coordinated test apparatus
US6992025B2 (en) * 2004-01-12 2006-01-31 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
JP2005347302A (en) 2004-05-31 2005-12-15 Canon Inc Substrate manufacturing method
JP4771510B2 (en) * 2004-06-23 2011-09-14 キヤノン株式会社 Semiconductor layer manufacturing method and substrate manufacturing method
JP4950047B2 (en) * 2004-07-22 2012-06-13 ボード オブ トラスティーズ オブ ザ レランド スタンフォード ジュニア ユニバーシティ Method for growing germanium and method for manufacturing semiconductor substrate
US7422447B2 (en) * 2004-08-19 2008-09-09 Fci Americas Technology, Inc. Electrical connector with stepped housing
JP2006080314A (en) 2004-09-09 2006-03-23 Canon Inc Manufacturing method of bonded substrate
US7371662B2 (en) * 2006-03-21 2008-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a 3D interconnect and resulting structures
US7790565B2 (en) * 2006-04-21 2010-09-07 Corning Incorporated Semiconductor on glass insulator made using improved thinning process
JP5171016B2 (en) 2006-10-27 2013-03-27 キヤノン株式会社 Semiconductor member, manufacturing method of semiconductor article, and LED array using the manufacturing method
JP2009094144A (en) * 2007-10-04 2009-04-30 Canon Inc Method for manufacturing light emitting device
KR20110020850A (en) * 2008-05-23 2011-03-03 후지필름 가부시키가이샤 Method and apparatus for substrate bonding
JP5796936B2 (en) * 2010-06-01 2015-10-21 キヤノン株式会社 Method for producing porous glass
CN103400890A (en) * 2013-07-08 2013-11-20 浙江晶科能源有限公司 Reworking technology for striping re-plating of crystal silicon solar cell PECVD (plasma enhanced chemical vapor deposition) chromatic aberration slice
JP6447439B2 (en) * 2015-09-28 2019-01-09 信越半導体株式会社 Manufacturing method of bonded SOI wafer
EP3349239B1 (en) * 2016-11-25 2020-04-08 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device production method
JP6558355B2 (en) * 2016-12-19 2019-08-14 信越半導体株式会社 Manufacturing method of SOI wafer
KR20230097121A (en) 2020-10-29 2023-06-30 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 Direct bonding method and structure
US20230140107A1 (en) * 2021-10-28 2023-05-04 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures

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KR100292330B1 (en) * 1992-05-01 2001-09-17 이데이 노부유끼 Semiconductor device and its manufacturing method and silicon insulating substrate manufacturing method
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KR100322585B1 (en) 1998-10-31 2002-05-09 윤종용 Optical scanning system of the printing press and its image scanning start timing adjustment method

Also Published As

Publication number Publication date
TW337042B (en) 1998-07-21
EP0801420A2 (en) 1997-10-15
US6156624A (en) 2000-12-05
CA2202003C (en) 2001-02-20
CN1099699C (en) 2003-01-22
SG80064A1 (en) 2001-04-17
EP0801420A3 (en) 1998-05-20
CN1166049A (en) 1997-11-26
JPH09331049A (en) 1997-12-22
SG54491A1 (en) 1998-11-16
KR100235398B1 (en) 1999-12-15

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