CA2145423A1 - Inverse modeller, system including same, and methods relating thereto - Google Patents

Inverse modeller, system including same, and methods relating thereto

Info

Publication number
CA2145423A1
CA2145423A1 CA002145423A CA2145423A CA2145423A1 CA 2145423 A1 CA2145423 A1 CA 2145423A1 CA 002145423 A CA002145423 A CA 002145423A CA 2145423 A CA2145423 A CA 2145423A CA 2145423 A1 CA2145423 A1 CA 2145423A1
Authority
CA
Canada
Prior art keywords
token
data
stage
recited
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002145423A
Other languages
English (en)
French (fr)
Inventor
Adrian Philip Wise
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Discovision Associates
Original Assignee
Discovision Associates
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9405914A external-priority patent/GB9405914D0/en
Application filed by Discovision Associates filed Critical Discovision Associates
Publication of CA2145423A1 publication Critical patent/CA2145423A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Image Processing (AREA)
  • Complex Calculations (AREA)
  • Television Systems (AREA)
CA002145423A 1994-03-24 1995-03-23 Inverse modeller, system including same, and methods relating thereto Abandoned CA2145423A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB9405914A GB9405914D0 (en) 1994-03-24 1994-03-24 Video decompression
GB9405914.4 1995-02-28
GB9504046A GB2288520B (en) 1994-03-24 1995-02-28 Pipeline
GB9504046.5 1995-02-28

Publications (1)

Publication Number Publication Date
CA2145423A1 true CA2145423A1 (en) 1995-09-25

Family

ID=26304580

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002145423A Abandoned CA2145423A1 (en) 1994-03-24 1995-03-23 Inverse modeller, system including same, and methods relating thereto

Country Status (5)

Country Link
JP (2) JPH0897725A (ja)
KR (1) KR100304511B1 (ja)
CN (1) CN1114489A (ja)
CA (1) CA2145423A1 (ja)
GB (1) GB2288520B (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3263807B2 (ja) * 1996-09-09 2002-03-11 ソニー株式会社 画像符号化装置および画像符号化方法
US20030159152A1 (en) 2001-10-23 2003-08-21 Shu Lin Fast motion trick mode using dummy bidirectional predictive pictures
US8284844B2 (en) 2002-04-01 2012-10-09 Broadcom Corporation Video decoding system supporting multiple standards
US8731054B2 (en) * 2004-05-04 2014-05-20 Qualcomm Incorporated Method and apparatus for weighted prediction in predictive frames
KR100711088B1 (ko) * 2005-04-13 2007-04-24 광주과학기술원 동화상 인코더를 위한 정수 변환 장치
US8401073B2 (en) 2007-03-28 2013-03-19 Panasonic Corporation Inverse quantization circuit, inverse quantization method and image reproducing apparatus
US8194977B2 (en) * 2008-12-09 2012-06-05 Microsoft Corporation Remote desktop protocol compression acceleration using single instruction, multiple dispatch instructions
US20150049098A1 (en) * 2013-08-13 2015-02-19 Mediatek Inc. Data processing apparatus for transmitting/receiving compressed pixel data groups via multiple display ports of display interface and related data processing method
GB2534420B (en) * 2015-01-26 2021-01-13 Advanced Risc Mach Ltd Data processing systems
CN112817889B (zh) * 2019-11-15 2024-06-21 合肥美亚光电技术股份有限公司 一种数据的采集方法及系统
CN111064912B (zh) * 2019-12-20 2022-03-22 江苏芯盛智能科技有限公司 一种帧格式变换电路与方法
CN113747060B (zh) * 2021-08-12 2022-10-21 荣耀终端有限公司 图像处理的方法、设备、存储介质
CN114580628A (zh) * 2022-03-14 2022-06-03 北京宏景智驾科技有限公司 一种神经网络卷积层的高效量化加速方法及硬件电路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0576749B1 (en) * 1992-06-30 1999-06-02 Discovision Associates Data pipeline system
GB2059724B (en) * 1979-09-28 1984-04-04 Racal Datacom Ltd Data transmission systems
JPS61194989A (ja) * 1985-02-22 1986-08-29 Mitsubishi Electric Corp 静止画伝送装置
US4680581A (en) * 1985-03-28 1987-07-14 Honeywell Inc. Local area network special function frames
GB8618060D0 (en) * 1986-07-24 1986-12-17 Gec Avionics Data processing apparatus
EP0255767A3 (en) * 1986-07-31 1990-04-04 AT&T Corp. Selective broadcasting arrangement for local area networks
JPH0695986A (ja) * 1992-06-19 1994-04-08 Westinghouse Electric Corp <We> リアルタイムデータ・イメージングネットワークシステム及びその操作方法
FR2695278B1 (fr) * 1992-08-26 1994-10-14 Euro Cp Sarl Procédé d'échange d'informations, en particulier entre équipements d'un local, et unité fonctionnelle et installation s'y rapportant.

Also Published As

Publication number Publication date
CN1114489A (zh) 1996-01-03
KR100304511B1 (ko) 2001-12-01
GB2288520A (en) 1995-10-18
JPH0897725A (ja) 1996-04-12
JP2003143018A (ja) 2003-05-16
GB2288520B (en) 1998-10-14
GB9504046D0 (en) 1995-04-19
KR950033894A (ko) 1995-12-26
JP3423942B2 (ja) 2003-07-07

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Legal Events

Date Code Title Description
EEER Examination request
FZDC Correction of dead application (reinstatement)
FZDE Dead