CA2141058A1 - Dispositif de transposition de niveau ecl en niveau cmos et tampon bicmos - Google Patents

Dispositif de transposition de niveau ecl en niveau cmos et tampon bicmos

Info

Publication number
CA2141058A1
CA2141058A1 CA 2141058 CA2141058A CA2141058A1 CA 2141058 A1 CA2141058 A1 CA 2141058A1 CA 2141058 CA2141058 CA 2141058 CA 2141058 A CA2141058 A CA 2141058A CA 2141058 A1 CA2141058 A1 CA 2141058A1
Authority
CA
Canada
Prior art keywords
coupled
voltage
input
source
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2141058
Other languages
English (en)
Inventor
Ban P. Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microunity Systems Engineering Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2141058A1 publication Critical patent/CA2141058A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
CA 2141058 1992-08-13 1993-05-28 Dispositif de transposition de niveau ecl en niveau cmos et tampon bicmos Abandoned CA2141058A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US92929592A 1992-08-13 1992-08-13
US07/929,295 1992-08-13

Publications (1)

Publication Number Publication Date
CA2141058A1 true CA2141058A1 (fr) 1994-03-03

Family

ID=25457621

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2141058 Abandoned CA2141058A1 (fr) 1992-08-13 1993-05-28 Dispositif de transposition de niveau ecl en niveau cmos et tampon bicmos

Country Status (5)

Country Link
EP (1) EP0655177A4 (fr)
JP (1) JPH08500225A (fr)
AU (1) AU4397293A (fr)
CA (1) CA2141058A1 (fr)
WO (1) WO1994005085A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19633723C1 (de) * 1996-08-21 1997-10-02 Siemens Ag Verzögerungsarmer Pegelumsetzer mit Schutzschaltung
GB0413152D0 (en) * 2004-06-14 2004-07-14 Texas Instruments Ltd Duty cycle controlled CML-CMOS converter

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380710A (en) * 1981-02-05 1983-04-19 Harris Corporation TTL to CMOS Interface circuit
DE3680064D1 (de) * 1985-10-09 1991-08-08 Nec Corp Differenzverstaerker-schaltungsanordnung.
KR910002967B1 (ko) * 1986-12-12 1991-05-11 가부시끼가이샤 히다찌세이사꾸쇼 바이폴라 트랜지스터와 mos 트랜지스터를 조합한 반도체 집적회로
US5019729A (en) * 1988-07-27 1991-05-28 Kabushiki Kaisha Toshiba TTL to CMOS buffer circuit
US5039886A (en) * 1989-05-26 1991-08-13 Nec Corporation Current mirror type level converters
US5113097A (en) * 1990-01-25 1992-05-12 David Sarnoff Research Center, Inc. CMOS level shifter circuit
JP2545146B2 (ja) * 1990-01-25 1996-10-16 富士通株式会社 レベル変換回路
JPH04335297A (ja) * 1991-05-09 1992-11-24 Mitsubishi Electric Corp 半導体集積回路装置のための入力バッファ回路
US5153465A (en) * 1991-08-06 1992-10-06 National Semiconductor Corporation Differential, high-speed, low power ECL-to-CMOS translator
US5202594A (en) * 1992-02-04 1993-04-13 Motorola, Inc. Low power level converter

Also Published As

Publication number Publication date
AU4397293A (en) 1994-03-15
WO1994005085A1 (fr) 1994-03-03
JPH08500225A (ja) 1996-01-09
EP0655177A1 (fr) 1995-05-31
EP0655177A4 (fr) 1997-03-26

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Legal Events

Date Code Title Description
FZDE Dead