CA2045662A1 - Binary floating point arithmetic rounding in conformance with ieee 754-1985 standard - Google Patents

Binary floating point arithmetic rounding in conformance with ieee 754-1985 standard

Info

Publication number
CA2045662A1
CA2045662A1 CA2045662A CA2045662A CA2045662A1 CA 2045662 A1 CA2045662 A1 CA 2045662A1 CA 2045662 A CA2045662 A CA 2045662A CA 2045662 A CA2045662 A CA 2045662A CA 2045662 A1 CA2045662 A1 CA 2045662A1
Authority
CA
Canada
Prior art keywords
standard
ieee
floating point
point arithmetic
rounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2045662A
Other languages
French (fr)
Other versions
CA2045662C (en
Inventor
Clif Liu
Brett Louis Lindsley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2045662A1 publication Critical patent/CA2045662A1/en
Application granted granted Critical
Publication of CA2045662C publication Critical patent/CA2045662C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/552—Powers or roots, e.g. Pythagorean sums
    • G06F7/5525—Roots or inverse roots of single operands
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
    • G06F2207/5355—Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/487—Multiplying; Dividing
    • G06F7/4873—Dividing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49957—Implementation of IEEE-754 Standard

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

2045662 9110189 PCTABS00006 A method and a high speed processor (HSP) incorporating that method are set forth for processing signals representing outputs generated by remainderless division algorithms (102) and remainderless square root algorithms so as to obtain rounded outputs (112) conforming to the IEEE 754-1985 binary floating point arithmetic standard. The method and procedure of the present invention allow the solutions of floating-point computations to be rounded such that sign bits, as well as binary bits, of the rounded results are in full compliance with all guidelines of the stated standard.
CA002045662A 1989-12-29 1990-12-17 Binary floating point arithmetic rounding in conformance with ieee 754-1985 standard Expired - Fee Related CA2045662C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45902189A 1989-12-29 1989-12-29
US459,021 1989-12-29

Publications (2)

Publication Number Publication Date
CA2045662A1 true CA2045662A1 (en) 1991-06-30
CA2045662C CA2045662C (en) 1994-04-26

Family

ID=23823065

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002045662A Expired - Fee Related CA2045662C (en) 1989-12-29 1990-12-17 Binary floating point arithmetic rounding in conformance with ieee 754-1985 standard

Country Status (5)

Country Link
EP (1) EP0461241A4 (en)
JP (1) JPH04507023A (en)
KR (1) KR940008611B1 (en)
CA (1) CA2045662C (en)
WO (1) WO1991010189A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9312745D0 (en) * 1993-06-21 1993-08-04 Questech Ltd Accurate digital divider
US5729481A (en) * 1995-03-31 1998-03-17 International Business Machines Corporation Method and system of rounding for quadratically converging division or square root
US6898614B2 (en) 2001-03-29 2005-05-24 Koninklijke Philips Electronics N.V. Round-off algorithm without bias for 2's complement data
JP4388980B2 (en) 2005-12-02 2009-12-24 富士通株式会社 Arithmetic apparatus and method for performing floating-point division or square root operation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468748A (en) * 1981-06-11 1984-08-28 Data General Corporation Floating point computation unit having means for rounding the floating point computation result
JPS6125245A (en) * 1984-07-12 1986-02-04 Nec Corp Rounding process circuit
JPS61213927A (en) * 1985-03-18 1986-09-22 Hitachi Ltd floating point arithmetic processing unit
JPH0644225B2 (en) * 1986-03-27 1994-06-08 日本電気株式会社 Floating point rounding normalization circuit
US4777613A (en) * 1986-04-01 1988-10-11 Motorola Inc. Floating point numeric data processor
US4758972A (en) * 1986-06-02 1988-07-19 Raytheon Company Precision rounding in a floating point arithmetic unit
JPH01275377A (en) * 1988-04-27 1989-11-06 Tech Res & Dev Inst Of Japan Def Agency High speed reeling out light fibre reel

Also Published As

Publication number Publication date
JPH04507023A (en) 1992-12-03
KR940008611B1 (en) 1994-09-24
CA2045662C (en) 1994-04-26
EP0461241A1 (en) 1991-12-18
WO1991010189A1 (en) 1991-07-11
KR920701902A (en) 1992-08-12
EP0461241A4 (en) 1993-09-01

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