CA2043100A1 - Circuit for providing dv/dt immunity - Google Patents
Circuit for providing dv/dt immunityInfo
- Publication number
- CA2043100A1 CA2043100A1 CA002043100A CA2043100A CA2043100A1 CA 2043100 A1 CA2043100 A1 CA 2043100A1 CA 002043100 A CA002043100 A CA 002043100A CA 2043100 A CA2043100 A CA 2043100A CA 2043100 A1 CA2043100 A1 CA 2043100A1
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- CA
- Canada
- Prior art keywords
- circuit
- output
- pulse
- transistor
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000036039 immunity Effects 0.000 title claims description 9
- 230000001052 transient effect Effects 0.000 claims description 9
- 238000010304 firing Methods 0.000 claims description 3
- 238000001914 filtration Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 7
- 238000001514 detection method Methods 0.000 description 5
- QHGVXILFMXYDRS-UHFFFAOYSA-N pyraclofos Chemical compound C1=C(OP(=O)(OCC)SCCC)C=NN1C1=CC=C(Cl)C=C1 QHGVXILFMXYDRS-UHFFFAOYSA-N 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 244000187656 Eucalyptus cornuta Species 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920000136 polysorbate Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
Abstract
ABSTRACT OF THE DISCLOSURE
A pulse filter is connected between a high voltage level shift circuit which produces output puls-es in a pattern determined by an input logic circuit and the high side logic circuit which controls the production of power MOSFET or IGBT gate signals or the like. The pulse filter immunizes the circuit against false operation due to the fast dv/dt transients. The circuit is integrated into a power integrated circuit for a MOS device gate driver.
A pulse filter is connected between a high voltage level shift circuit which produces output puls-es in a pattern determined by an input logic circuit and the high side logic circuit which controls the production of power MOSFET or IGBT gate signals or the like. The pulse filter immunizes the circuit against false operation due to the fast dv/dt transients. The circuit is integrated into a power integrated circuit for a MOS device gate driver.
Description
IR-977 (2- ) CIRCUIT FOR PROVIDING_DV/DT IMMUNITY
~L~
This invention relates to a novel level shifting circuit which provides immunity to false oper-ation due to unintended transient dv/dt pulses in the circuit.
Level shifting circuits for shifting the potential of a small control signal to a higher or lower voltage level are well known, and are frequently integrated into a power integrated circuit chip. A
typical device of this type is the IR 2110 sold by the International Rectifier Corporat;on, the assignee of the present invention. The IR 2110 is a high voltage, high speed MOs gated power device for driving the gate of a power MOSFET or insulated gate bipolar transistor, 1~ (hereinafter an "IGBT'l) with independent high side and low side output channels. It has logic inputs supplied by the user of the driver chip. The floating high side channel may be used to drive an N-channel power MOSFET
or IGBT which operates off a high voltage rail at up to ~o 500 Yolts.
A common problem in such circuits is false operation, that is, production of an output which is not called for by the logic input, under the influence of high dv/dt transients. More specifically, such 6~
circuits commonly have h;gh voltage level shif~ing transistor circuits which act to transpose a low volt~
age referenced signal to a high voltage floating rail to operate a switching circuit at the voltage of the floating rail. The level shifting transis~or is turned on for only the duration of a short pulse in order to minimize power dissipation~ However/ the output of the high voltage switching circuit can be switched by fast dv/dt transients because of the parasitic capacitance on the drain or collector of the level shifting tran-sistor, even if there is no change in input~
RIEF DESCRIPTION OF THE INVENTION
In accordance with the present invention, a pulse d;scrimination circuit is coupled between the output of the high voltage DMOS level shifting circuit and the main switching circuit to discriminate normal switching pulses from fast dv/dt transients. The novel invention has been measured to provide dv/dt immunity o greater than i 50 V/ns~ and theoretically is totally immune.
BR I EF DESCR I PT I ON OF THE DRAW I NGS
Figure 1 is a schemat;c diagram of a known IR 2110 power integrated circuit which drives a pair of power MOSFETs.
Figure 2 shows the application of the power integrated circuit of Figure 1 to a buck converter circuit.
Figure 3 is a functional block diagram of the power integrated circuit of Figure 1 and particu-larly shows the novel dv/dt immunity circuit of the invention.
h ~ ~ 3 Figures 4a to 4c are input/output timing diagrams for the chip of Figur2 3O
Figures 5a to 5h are diagrams on a common time base of voltages at differen~ points in the dia-gram of Figure 3.
Figure 6 is a circuit diagram of an embodiment of the pulse generator of Figure 3~
Figure 7 is a circuit diagram of one of the pulse filters of Figure 3.
Figures 8A through 8F show the pulse wave forms at various parts of the circuit of Figure 7.
DETAILED DESCRIPTION OF THE DRAWINGS
Referring first to Fic~ure l, there is shown, in schemat.ic form, a power integrated circuit 20 which acts as a high voltage MOS gate driver for power MOSFETs 21 and 22. The integrated circuit 20 has out-put pins numbered l-~, 5-7 and 9-13.
The pins in Figure l and in other following figures have the following assigmnents:
~o Pin No~ Assiqnment l Low side output voltage (to gate of low side MOSFET 22), which swings, for example, from 0 ~ 20 volts.
~L~
This invention relates to a novel level shifting circuit which provides immunity to false oper-ation due to unintended transient dv/dt pulses in the circuit.
Level shifting circuits for shifting the potential of a small control signal to a higher or lower voltage level are well known, and are frequently integrated into a power integrated circuit chip. A
typical device of this type is the IR 2110 sold by the International Rectifier Corporat;on, the assignee of the present invention. The IR 2110 is a high voltage, high speed MOs gated power device for driving the gate of a power MOSFET or insulated gate bipolar transistor, 1~ (hereinafter an "IGBT'l) with independent high side and low side output channels. It has logic inputs supplied by the user of the driver chip. The floating high side channel may be used to drive an N-channel power MOSFET
or IGBT which operates off a high voltage rail at up to ~o 500 Yolts.
A common problem in such circuits is false operation, that is, production of an output which is not called for by the logic input, under the influence of high dv/dt transients. More specifically, such 6~
circuits commonly have h;gh voltage level shif~ing transistor circuits which act to transpose a low volt~
age referenced signal to a high voltage floating rail to operate a switching circuit at the voltage of the floating rail. The level shifting transis~or is turned on for only the duration of a short pulse in order to minimize power dissipation~ However/ the output of the high voltage switching circuit can be switched by fast dv/dt transients because of the parasitic capacitance on the drain or collector of the level shifting tran-sistor, even if there is no change in input~
RIEF DESCRIPTION OF THE INVENTION
In accordance with the present invention, a pulse d;scrimination circuit is coupled between the output of the high voltage DMOS level shifting circuit and the main switching circuit to discriminate normal switching pulses from fast dv/dt transients. The novel invention has been measured to provide dv/dt immunity o greater than i 50 V/ns~ and theoretically is totally immune.
BR I EF DESCR I PT I ON OF THE DRAW I NGS
Figure 1 is a schemat;c diagram of a known IR 2110 power integrated circuit which drives a pair of power MOSFETs.
Figure 2 shows the application of the power integrated circuit of Figure 1 to a buck converter circuit.
Figure 3 is a functional block diagram of the power integrated circuit of Figure 1 and particu-larly shows the novel dv/dt immunity circuit of the invention.
h ~ ~ 3 Figures 4a to 4c are input/output timing diagrams for the chip of Figur2 3O
Figures 5a to 5h are diagrams on a common time base of voltages at differen~ points in the dia-gram of Figure 3.
Figure 6 is a circuit diagram of an embodiment of the pulse generator of Figure 3~
Figure 7 is a circuit diagram of one of the pulse filters of Figure 3.
Figures 8A through 8F show the pulse wave forms at various parts of the circuit of Figure 7.
DETAILED DESCRIPTION OF THE DRAWINGS
Referring first to Fic~ure l, there is shown, in schemat.ic form, a power integrated circuit 20 which acts as a high voltage MOS gate driver for power MOSFETs 21 and 22. The integrated circuit 20 has out-put pins numbered l-~, 5-7 and 9-13.
The pins in Figure l and in other following figures have the following assigmnents:
~o Pin No~ Assiqnment l Low side output voltage (to gate of low side MOSFET 22), which swings, for example, from 0 ~ 20 volts.
2 Common ground connection~
3 Low side fixed supply voltage, for example, 20 volts.
High side floating supply offset voltage (for example, 500 volts).
6 High side floating supply absolute voltage, for example, 5~0 volts.
7 High side output voltage (to gate of high side MOSFET 213, which swings, for example, between 500 and 520 volts.
9 Lo~ic supply voltage (20 volts~.
1~ 10,11,12 Low voltage logic inputs for the desired control of the output voltage at pins l and 7 in accordance with the timing chart, for example, of Figures ~a, 4b ancl 4c.
13 The logic supply ground.
Figure 2 shows the integrated circuit 20 of Figure l connected to drive a buck converter. The main power MOSFET 30 has a drain electrode connected to the 2~ high voltage supply VR which is lless than or equal to about 500 volts. The buck converter circuit includes the conventional diode 31, inductor 32, capacitor 33 and a load 3~ is connected across the capacitor 33 in the usual manner. A 0.1 microfarad capacitor 35 is 2s connected across pins 5 and 6 and a diode 36, which may be a 10KF6 type diode, is connected between pins 3 and 6. A 15 volt power supply input is connected to pins 3 and 9 and a l microfarad capacitor 37 is con-nected from pin 9 to pins 2, ll, 12 and 130 A suitable logic input is connected to pin ll.
In accordance with the invention, the integrated circuit 20 contains a novel circuit for ~ 5 --immunizing the circuits of Figures 1 and 2 from false trigyering due to fast dvJdt transients appearing, for example, at the circuit node connected to pin 5.
Figure 3 is a functional block diagram of the circuit contained w;thin the integrated circuit 20 in Figures 1 and 2. The pin numbers in Figure 3 corre-spond to the same numbered pins of Figures 1 and 2.
Logic input pins 10, 11 and 12 are connected through Schmitt triggers 50, 51 and 52 to the RS latches 55 and 55q Latches 55 and 56 are connected through gates 57 and 58, respectively, to level shit circuits 59 and Ç0O As wi].l be seen, the outputs of the level shift circuits 59 and 60 control the high side control output and low sicle control output at pins 7 and 1, respec-tively.
The ou~put from level shift circuit 60 in the low voltage channel is applied through a delay circuit 61 and one input of gate circuit 62. The out-put of gate 62 is connected to the gate electrodes of output MOSFET transistors 63 and 64. As will be later described, these transistors will produce a gate volt-a~e at pin 1 when required by the logic input to pins 11 and 12.
Figure 3 also contains an under-voltage detection circuit 70 which disables the output from gate 62 when an under voltage is detected at p;n 3 to prevent turn-on of the power MOSFET or IGBT operated from pin 1.
The level shift circuit 59 for the high voltage channel of the circuit has one input onnected to the pulse generator 8G. Under-voltage detection circuit 70 is also connected to pulse generator 80 and will turn off the high voltage output channel respon-sive to the detection of an under-voltage condition at pin 3O
Pulse generator 80 has two outputs, a set output (Figure 5b) connected to the gate of MOSFET 81 and a reset output (Figure 5c) connected to the gate of MOSFET 82. Figure 5a shows the wave form for the input HIN at pin 10. The set pulses of Figure 5b are applied to MOSFET 81 and the reset pulses of Figure 5c are applied to MOSFET 82. A set pulse is triggered with the rise of the pulse HIN and the reset pulse is trig-gered with the fall of pulse HIN. These pulses have a given length tS and tr, respectively as shown.
The sources of MOSFETs 81 and 82 are connected to a common connection rail and their drains are connected to resistors 90 and 91, respectively.
During normal operation, the application of pulseg to MOSFETs 81 and 82 from l:he pulse generator 80 will produce output voltage pulses Vset and Yrst at the nodes between MOSFETs 81 and 32 and their respec~ive resistors 90 and 91. Pulses Vset and Vrst have the wave forms shown in Figures 5d and 5e, respectively.
The pulses vset and Vrst are then applied to a novel pulse filter 93 which is provided in accor-dance with the invention~ The output channels o~ fil-ter 93 are connected to the R and S inputs of latch 94, in accordance with the present invent;on. A second under-voltage detectlon circuit 102 is provided as an input to the latch 9~ to ensure that no signal is ap-plied at pin 7 i an under voltage is detected at pin6. Under normal conditions, the pulses Yset and Vrst which pass throuyh the pulse filter 93 will have the ~ 7 ~
wave shapes shown in Figures 5f and 5g, respectively, and will have lengths of t~ and ~r~ respectively.
The pulses are shortened by an amount tf~ which is the delay in the pulse filter. Note that the value tf is the filter time, such that tsf - (tS-tf) and trf = (tr tf). However, a transient dv/dt pulse which appears at the input of pulse filter 93 will have the appearance o~ the pulses of Figure 5h and will have a pulse length tv, which is shorter than the value tf.
Consequently, the pulses tv produced by transient dv/dt signals within the system are easily discriminated and will not pass through the pulse filter to operate the RS latch 94.
The output of the RS latch 94 is then used 15to turn MOSFETs 100 and 101 on and off. Thus, if a high signal is applied to input R of the RS latch, the output at pin 7 is turned off. Ii- a high signal is applied to the S input of latch 94, the output at pin 7 will turn on.
~oIt is now possible to give a functional description of the operation of the block diagram of Figure 3. In general, the structure in Figure 3 is implemented as a monolithic high voltage chip and acts as a high speed, two channel power MOSFET or IGBT driv-er. The driver essentially translates the logic input signals at pins lOr 11 and 12 and to corresponding "in phase" low impedance outputs. The low side channel output pin l is referenced to the fixed rail at pin 3 and the high side channel output at pin 7 is referenced ~O to the floating rail at pin 6 with offset capability up to 500 voltsO
The logic input to pins 10, 11 and 12 provides the control pulses for the two output channels as described in connection with Figures 4a, 4b and 4c.
Thus, in Figure 4c the H0 and L0 outputs at pins 7 and 1~ respectively, are in phase with the HIN and LIN
logic inputs at pins 10 and 12 in Figure ~al The two outputs H0 and LO will turn off when the 5D input at pin 11 (Figure 4b) switches high. The outputs will remain of even ater the SD input at pin 11 returns to low and until the next rising edge of the respective inputs in Figure 4a.
When the voltage at pin 3 is below the under-voltage trip point, the under-voltage trip detec-tion circuit 70 sends a shut-down signal to disable both channels as previously described. Also a separate under-voltage detection block 102 is used to disable the high side channel when the vo;ltage at pin 6 is below its own under-volta~e trip point. The logic inputs 10, 11 and 12 use Schmitt trigger circuits with a hysteretic band to provide high noise in~unity and can accept inputs with slow rise time.
The logic circuit is then referenced to its own logic supply to allow the use of a lower supply voltage than the output operating supply voltage. The level shift circuits 59 and 60 are preferably high noise immunity circuits which translate the logic sig-nal to the output drivers. Thus, with a + 5 volt rated offset capability between the logic ~round 13 and the power ground 2, the logic circuit is unaffected by noise coupling generated by the switching action of the output dr iYers ~
Propagation delay for the two channels is matched using the low side delay channel to simplify the timing requirements of the control pulses. The turn-on delay is matched at 120 nanoseconds for the low side channel and the high side channel, when the volt-age at pin 5 is at 0 volt since the high side turn-on command is usually executed when the voltage at pin 5 is at or near 0 volt. The turn-off delay is matched at 94 nanoseconds for the low side channel and the high lo side channel, when the voltage at pin 5 is 500 volts, since the high side turn-off command is usually execut-ed after the high side power MOSFET is on and the volt-age at pin 5 is at or near the high voltage rail at pin 6.
Both channels in the functional bloclt diagram of Figure 3 use identical low cross-conduction totem pole output connection transistors. Thus, the output driver consists of the two N-channel MOSFETs 100 and 101 which have peak current capability above 2 amperes and an on-resistance of less than about 3 ohms.
One of the output MOSFETs is connected as a source follower and the other in a common source configura-tion. Because of the totem pole arrangement, the rise time is slower than the fall time driving a capacitive load. For example, for a typical 3300 picofarad load the rise and fall times are 50 nanoseconds and 33 nano-seconds, respectively.
The high voltage level shifting circuit is designed to function normally even when the potential ~o at pin 5 swings more than 4 volts below the voltage of pin 2. This condition can often occur during the recirculation period of the output free wheeling diode in a circuit of the type shown in Figure 2.
~3~
For the high side channel, narrow on and off pulses triggered, respectively, by the rising and falling edge of input HIN in Figure 4a are generated by the pulse generator 80. Tlle respective pulses are used to drive the separate high voltage level transistors 81 and 82 which set or reset the RS latch 94 operatiny off the floating rail, Level shifting of the ground reference HIN signal at pin 10 is thus accomplished by transposing the signal referenced to the floa~ing rail.
Because each hiyh voltage level transistor 81 and 82 is turned on for only the duration of the short on or off pulses with each set or reset event, power dissipation is minimized. This led to the problem, however, of false triggering by transient high dv/dt pulses.
In accordance with the present invention, false triggerin~ of the RS latch '34 due to fast dvJdt transients on the pin 5 is prevented by effectively differentiating them from normal pull-down pulses by use of the pulse discriminator circuit 93~ Thus, cir-~0 cuit 93 makes the high side chann~l essentially i~une to any magnitude dv/dt value transient pulse.
The MOSFET driver 20 can be used in numerous circuit applications. By way of example, two such drivers can be used for driving a conventional H
bridge; three such drivers can be used to control the power MOSFETs or IGBT devices in a three-phase bridge motor drive. In general/ the MOSFET driver has virtu-ally any applîcation for power MOSFETs or IGBTs.
Figure 6 is a circuit diagram of a preferred pulse generator which can be used for pulse generator block 80. The input lead l~beled "HIN" is the lead from level 5hift circuit 59 in Figure 3, The 3~
output leads labeled "SET" and ~RESET" correspond to the leads connected to the gates of MOSFETs 81 and ~2 in Figure 3.
The pulse generator circuit itself comprises two channels. The first channel comprises an inverter gate 200 which is connected to one input of digital NOR gate 201. The first channel also includes a delay block consisting of series-connected inverter gates 202, 203, 204 and 205~ The output of gate 205 is connected to the other input of NOR gate 201. Two 2.3 picofarad capacitors are connected from the nodes be-tween inverters 203-20~ and 204-205, respectively.
The second channel of the pulse generator, used for reset pulses, has the same structure as the first and includes inverter yate 21~ and delay block inverters 211~ 212, 213 and ~1~, which are connected to NOR gate 215.
It will be apparent that the circuit of Fi~ure 6 can be implemented in int:egrated circuit form.
In operation, the circuit of Figure 6 will produce a pulse having a pulse width determined by the ~ime for a signal to pass through the chain of invert-ers 202 through 205 or 211 through 21~.
Figure 7 shows one half of the pulse filter 2S 93 and MOSFET 81. The other half of pulse filter 93 is identical to the one half which is shown, but is asso-ciated with MOSFET 82~ The use of MOSFETs is optional, and the circuit could also be implemented with a bipo-lar level shift transistor.
Pull-up resistor 90 may be a 250 ohm resistor. Pull-up resistor 90 can also he a current source of any desired type. The inven~ion may also be ~6~ a~
applied when level shiEting from a high to a low volt-age. In that case, the level shift transistor would become a P channel MOSFET or PNP transistor, and the pull-up resistor would become a pull-down resistor or other current sink type.
When the circuit is formed as an integrated circuit, resistor 90 may be implemented as a P type region in an N type epitaxial substrate. Such a structure will have inherent diodes 220, 221 and 2?2 distributed along its length, A second resistor 223 may be implemented as a polysilicon resistor. Resistor 223 is a ballast resistor in series with the source of transistor 81 to prevent parasitic bipolar turn on.
Also shown in Figure 7 is the capacltance 224 between the drain and source of MOSFET 81.
The one half of the pulse filter 93 shown in Figure 7 consists o~ an inverter chain circuit which, in turn, consists of MOSFET pairs 230-231, 23~-233, 234-235 and 236-237. These function to "square-2~ up" pulses produced by transistor 81 in the manner to be described hereinafter. Capacitor 240 and resistor 241, which are 3 picofarads and 10k ohms respectively, produce a delay in the point where this pulse rises as will also be later described.
The operation of the circuit of Figure 7 is best understood with reference to the wave forms of Figures 8A through 8F which show the pulse shape at points A through F, respectively in Figure 7O
Thus, the pulse used to turn on the "set"
transistor 81 is the pulse on the gate of MOSFET 81shown in Figure 7 which is derived from the set channel output of ~ate 201 of Figure 6. This creates a pulse of the shape shown in Figure 8B at point B in Figure 7 as a result of the actio~ of pull-up resistor 90.
Stage 230-231 squares-up the pulse at point C as shown in Fi~ure 8C and it is further squared at point D by st~ge 232-233 r as shown in Figure 8D. Capacitor 240 and resistor 2~1 in the next stage 234-235 act to delay the rise of the pulse at point E as shown in Figure 8E.
This pulse is squared at point F by sta~e 236-237, shown in Figure 8F. This pulse, however, has its lead-ing edge delayed from the leading edge of the pulse applied at point A by about 50 nanoseconds.
Consider next the effect of a transient high dv/dt signal applied to point B of the circuit.
In prior circuits, such a high dv/dt signal would be falsely recognized as an intended firing signal which would be applied to the RS latch '34 in Figure 3, pro-ducing a false firing signal at pin 7. However, in accordance with the invention, suc:h a dv/dt pulse will not pass through filter 93.
A transient dv/dt pulse is shown in dotted lines in Figure 8B. This pulse is squared up in Fig-ures 8C and 8D. This short pulse canno~ produce a sufficient gate drive for stage 236-237 so that no pulse appears at its output at point F. Consequently, dv/dt induced pulses will not cause false tri~yering of the circuit.
Althoush the present invention has been described in relation to particular embodiments there-of, many other variations and modifications and other 3~ uses will become apparent to those skilled in the art.
It is preferred, therefore, tha~ the present invention be limited not by the specific disclosure herein, but only by the appended claims.
High side floating supply offset voltage (for example, 500 volts).
6 High side floating supply absolute voltage, for example, 5~0 volts.
7 High side output voltage (to gate of high side MOSFET 213, which swings, for example, between 500 and 520 volts.
9 Lo~ic supply voltage (20 volts~.
1~ 10,11,12 Low voltage logic inputs for the desired control of the output voltage at pins l and 7 in accordance with the timing chart, for example, of Figures ~a, 4b ancl 4c.
13 The logic supply ground.
Figure 2 shows the integrated circuit 20 of Figure l connected to drive a buck converter. The main power MOSFET 30 has a drain electrode connected to the 2~ high voltage supply VR which is lless than or equal to about 500 volts. The buck converter circuit includes the conventional diode 31, inductor 32, capacitor 33 and a load 3~ is connected across the capacitor 33 in the usual manner. A 0.1 microfarad capacitor 35 is 2s connected across pins 5 and 6 and a diode 36, which may be a 10KF6 type diode, is connected between pins 3 and 6. A 15 volt power supply input is connected to pins 3 and 9 and a l microfarad capacitor 37 is con-nected from pin 9 to pins 2, ll, 12 and 130 A suitable logic input is connected to pin ll.
In accordance with the invention, the integrated circuit 20 contains a novel circuit for ~ 5 --immunizing the circuits of Figures 1 and 2 from false trigyering due to fast dvJdt transients appearing, for example, at the circuit node connected to pin 5.
Figure 3 is a functional block diagram of the circuit contained w;thin the integrated circuit 20 in Figures 1 and 2. The pin numbers in Figure 3 corre-spond to the same numbered pins of Figures 1 and 2.
Logic input pins 10, 11 and 12 are connected through Schmitt triggers 50, 51 and 52 to the RS latches 55 and 55q Latches 55 and 56 are connected through gates 57 and 58, respectively, to level shit circuits 59 and Ç0O As wi].l be seen, the outputs of the level shift circuits 59 and 60 control the high side control output and low sicle control output at pins 7 and 1, respec-tively.
The ou~put from level shift circuit 60 in the low voltage channel is applied through a delay circuit 61 and one input of gate circuit 62. The out-put of gate 62 is connected to the gate electrodes of output MOSFET transistors 63 and 64. As will be later described, these transistors will produce a gate volt-a~e at pin 1 when required by the logic input to pins 11 and 12.
Figure 3 also contains an under-voltage detection circuit 70 which disables the output from gate 62 when an under voltage is detected at p;n 3 to prevent turn-on of the power MOSFET or IGBT operated from pin 1.
The level shift circuit 59 for the high voltage channel of the circuit has one input onnected to the pulse generator 8G. Under-voltage detection circuit 70 is also connected to pulse generator 80 and will turn off the high voltage output channel respon-sive to the detection of an under-voltage condition at pin 3O
Pulse generator 80 has two outputs, a set output (Figure 5b) connected to the gate of MOSFET 81 and a reset output (Figure 5c) connected to the gate of MOSFET 82. Figure 5a shows the wave form for the input HIN at pin 10. The set pulses of Figure 5b are applied to MOSFET 81 and the reset pulses of Figure 5c are applied to MOSFET 82. A set pulse is triggered with the rise of the pulse HIN and the reset pulse is trig-gered with the fall of pulse HIN. These pulses have a given length tS and tr, respectively as shown.
The sources of MOSFETs 81 and 82 are connected to a common connection rail and their drains are connected to resistors 90 and 91, respectively.
During normal operation, the application of pulseg to MOSFETs 81 and 82 from l:he pulse generator 80 will produce output voltage pulses Vset and Yrst at the nodes between MOSFETs 81 and 32 and their respec~ive resistors 90 and 91. Pulses Vset and Vrst have the wave forms shown in Figures 5d and 5e, respectively.
The pulses vset and Vrst are then applied to a novel pulse filter 93 which is provided in accor-dance with the invention~ The output channels o~ fil-ter 93 are connected to the R and S inputs of latch 94, in accordance with the present invent;on. A second under-voltage detectlon circuit 102 is provided as an input to the latch 9~ to ensure that no signal is ap-plied at pin 7 i an under voltage is detected at pin6. Under normal conditions, the pulses Yset and Vrst which pass throuyh the pulse filter 93 will have the ~ 7 ~
wave shapes shown in Figures 5f and 5g, respectively, and will have lengths of t~ and ~r~ respectively.
The pulses are shortened by an amount tf~ which is the delay in the pulse filter. Note that the value tf is the filter time, such that tsf - (tS-tf) and trf = (tr tf). However, a transient dv/dt pulse which appears at the input of pulse filter 93 will have the appearance o~ the pulses of Figure 5h and will have a pulse length tv, which is shorter than the value tf.
Consequently, the pulses tv produced by transient dv/dt signals within the system are easily discriminated and will not pass through the pulse filter to operate the RS latch 94.
The output of the RS latch 94 is then used 15to turn MOSFETs 100 and 101 on and off. Thus, if a high signal is applied to input R of the RS latch, the output at pin 7 is turned off. Ii- a high signal is applied to the S input of latch 94, the output at pin 7 will turn on.
~oIt is now possible to give a functional description of the operation of the block diagram of Figure 3. In general, the structure in Figure 3 is implemented as a monolithic high voltage chip and acts as a high speed, two channel power MOSFET or IGBT driv-er. The driver essentially translates the logic input signals at pins lOr 11 and 12 and to corresponding "in phase" low impedance outputs. The low side channel output pin l is referenced to the fixed rail at pin 3 and the high side channel output at pin 7 is referenced ~O to the floating rail at pin 6 with offset capability up to 500 voltsO
The logic input to pins 10, 11 and 12 provides the control pulses for the two output channels as described in connection with Figures 4a, 4b and 4c.
Thus, in Figure 4c the H0 and L0 outputs at pins 7 and 1~ respectively, are in phase with the HIN and LIN
logic inputs at pins 10 and 12 in Figure ~al The two outputs H0 and LO will turn off when the 5D input at pin 11 (Figure 4b) switches high. The outputs will remain of even ater the SD input at pin 11 returns to low and until the next rising edge of the respective inputs in Figure 4a.
When the voltage at pin 3 is below the under-voltage trip point, the under-voltage trip detec-tion circuit 70 sends a shut-down signal to disable both channels as previously described. Also a separate under-voltage detection block 102 is used to disable the high side channel when the vo;ltage at pin 6 is below its own under-volta~e trip point. The logic inputs 10, 11 and 12 use Schmitt trigger circuits with a hysteretic band to provide high noise in~unity and can accept inputs with slow rise time.
The logic circuit is then referenced to its own logic supply to allow the use of a lower supply voltage than the output operating supply voltage. The level shift circuits 59 and 60 are preferably high noise immunity circuits which translate the logic sig-nal to the output drivers. Thus, with a + 5 volt rated offset capability between the logic ~round 13 and the power ground 2, the logic circuit is unaffected by noise coupling generated by the switching action of the output dr iYers ~
Propagation delay for the two channels is matched using the low side delay channel to simplify the timing requirements of the control pulses. The turn-on delay is matched at 120 nanoseconds for the low side channel and the high side channel, when the volt-age at pin 5 is at 0 volt since the high side turn-on command is usually executed when the voltage at pin 5 is at or near 0 volt. The turn-off delay is matched at 94 nanoseconds for the low side channel and the high lo side channel, when the voltage at pin 5 is 500 volts, since the high side turn-off command is usually execut-ed after the high side power MOSFET is on and the volt-age at pin 5 is at or near the high voltage rail at pin 6.
Both channels in the functional bloclt diagram of Figure 3 use identical low cross-conduction totem pole output connection transistors. Thus, the output driver consists of the two N-channel MOSFETs 100 and 101 which have peak current capability above 2 amperes and an on-resistance of less than about 3 ohms.
One of the output MOSFETs is connected as a source follower and the other in a common source configura-tion. Because of the totem pole arrangement, the rise time is slower than the fall time driving a capacitive load. For example, for a typical 3300 picofarad load the rise and fall times are 50 nanoseconds and 33 nano-seconds, respectively.
The high voltage level shifting circuit is designed to function normally even when the potential ~o at pin 5 swings more than 4 volts below the voltage of pin 2. This condition can often occur during the recirculation period of the output free wheeling diode in a circuit of the type shown in Figure 2.
~3~
For the high side channel, narrow on and off pulses triggered, respectively, by the rising and falling edge of input HIN in Figure 4a are generated by the pulse generator 80. Tlle respective pulses are used to drive the separate high voltage level transistors 81 and 82 which set or reset the RS latch 94 operatiny off the floating rail, Level shifting of the ground reference HIN signal at pin 10 is thus accomplished by transposing the signal referenced to the floa~ing rail.
Because each hiyh voltage level transistor 81 and 82 is turned on for only the duration of the short on or off pulses with each set or reset event, power dissipation is minimized. This led to the problem, however, of false triggering by transient high dv/dt pulses.
In accordance with the present invention, false triggerin~ of the RS latch '34 due to fast dvJdt transients on the pin 5 is prevented by effectively differentiating them from normal pull-down pulses by use of the pulse discriminator circuit 93~ Thus, cir-~0 cuit 93 makes the high side chann~l essentially i~une to any magnitude dv/dt value transient pulse.
The MOSFET driver 20 can be used in numerous circuit applications. By way of example, two such drivers can be used for driving a conventional H
bridge; three such drivers can be used to control the power MOSFETs or IGBT devices in a three-phase bridge motor drive. In general/ the MOSFET driver has virtu-ally any applîcation for power MOSFETs or IGBTs.
Figure 6 is a circuit diagram of a preferred pulse generator which can be used for pulse generator block 80. The input lead l~beled "HIN" is the lead from level 5hift circuit 59 in Figure 3, The 3~
output leads labeled "SET" and ~RESET" correspond to the leads connected to the gates of MOSFETs 81 and ~2 in Figure 3.
The pulse generator circuit itself comprises two channels. The first channel comprises an inverter gate 200 which is connected to one input of digital NOR gate 201. The first channel also includes a delay block consisting of series-connected inverter gates 202, 203, 204 and 205~ The output of gate 205 is connected to the other input of NOR gate 201. Two 2.3 picofarad capacitors are connected from the nodes be-tween inverters 203-20~ and 204-205, respectively.
The second channel of the pulse generator, used for reset pulses, has the same structure as the first and includes inverter yate 21~ and delay block inverters 211~ 212, 213 and ~1~, which are connected to NOR gate 215.
It will be apparent that the circuit of Fi~ure 6 can be implemented in int:egrated circuit form.
In operation, the circuit of Figure 6 will produce a pulse having a pulse width determined by the ~ime for a signal to pass through the chain of invert-ers 202 through 205 or 211 through 21~.
Figure 7 shows one half of the pulse filter 2S 93 and MOSFET 81. The other half of pulse filter 93 is identical to the one half which is shown, but is asso-ciated with MOSFET 82~ The use of MOSFETs is optional, and the circuit could also be implemented with a bipo-lar level shift transistor.
Pull-up resistor 90 may be a 250 ohm resistor. Pull-up resistor 90 can also he a current source of any desired type. The inven~ion may also be ~6~ a~
applied when level shiEting from a high to a low volt-age. In that case, the level shift transistor would become a P channel MOSFET or PNP transistor, and the pull-up resistor would become a pull-down resistor or other current sink type.
When the circuit is formed as an integrated circuit, resistor 90 may be implemented as a P type region in an N type epitaxial substrate. Such a structure will have inherent diodes 220, 221 and 2?2 distributed along its length, A second resistor 223 may be implemented as a polysilicon resistor. Resistor 223 is a ballast resistor in series with the source of transistor 81 to prevent parasitic bipolar turn on.
Also shown in Figure 7 is the capacltance 224 between the drain and source of MOSFET 81.
The one half of the pulse filter 93 shown in Figure 7 consists o~ an inverter chain circuit which, in turn, consists of MOSFET pairs 230-231, 23~-233, 234-235 and 236-237. These function to "square-2~ up" pulses produced by transistor 81 in the manner to be described hereinafter. Capacitor 240 and resistor 241, which are 3 picofarads and 10k ohms respectively, produce a delay in the point where this pulse rises as will also be later described.
The operation of the circuit of Figure 7 is best understood with reference to the wave forms of Figures 8A through 8F which show the pulse shape at points A through F, respectively in Figure 7O
Thus, the pulse used to turn on the "set"
transistor 81 is the pulse on the gate of MOSFET 81shown in Figure 7 which is derived from the set channel output of ~ate 201 of Figure 6. This creates a pulse of the shape shown in Figure 8B at point B in Figure 7 as a result of the actio~ of pull-up resistor 90.
Stage 230-231 squares-up the pulse at point C as shown in Fi~ure 8C and it is further squared at point D by st~ge 232-233 r as shown in Figure 8D. Capacitor 240 and resistor 2~1 in the next stage 234-235 act to delay the rise of the pulse at point E as shown in Figure 8E.
This pulse is squared at point F by sta~e 236-237, shown in Figure 8F. This pulse, however, has its lead-ing edge delayed from the leading edge of the pulse applied at point A by about 50 nanoseconds.
Consider next the effect of a transient high dv/dt signal applied to point B of the circuit.
In prior circuits, such a high dv/dt signal would be falsely recognized as an intended firing signal which would be applied to the RS latch '34 in Figure 3, pro-ducing a false firing signal at pin 7. However, in accordance with the invention, suc:h a dv/dt pulse will not pass through filter 93.
A transient dv/dt pulse is shown in dotted lines in Figure 8B. This pulse is squared up in Fig-ures 8C and 8D. This short pulse canno~ produce a sufficient gate drive for stage 236-237 so that no pulse appears at its output at point F. Consequently, dv/dt induced pulses will not cause false tri~yering of the circuit.
Althoush the present invention has been described in relation to particular embodiments there-of, many other variations and modifications and other 3~ uses will become apparent to those skilled in the art.
It is preferred, therefore, tha~ the present invention be limited not by the specific disclosure herein, but only by the appended claims.
Claims (17)
1. A level shifting circuit for translating a logic voltage state from one voltage level to a different voltage level with dv/dt immunity;
said circuit including logic level input circuit means;
a pulse generator circuit coupled to said input circuit means; transistor means having a control electrode coupled to the output of said pulse generator means and a pair of main electrodes; a current source means; said main electrodes of said transistor means connected in series with said current source means; a pulse filter for passing only selected normal-operation pulses which are differentiated from pulses produced by dv/dt tran-sient signals applied to said main electrodes of said transistor by the length of said pulses; and output circuit means coupled to the output of said pulse fil-ter; said output circuit means producing a switching function in response to the passage of a pulse signal through said pulse filter.
said circuit including logic level input circuit means;
a pulse generator circuit coupled to said input circuit means; transistor means having a control electrode coupled to the output of said pulse generator means and a pair of main electrodes; a current source means; said main electrodes of said transistor means connected in series with said current source means; a pulse filter for passing only selected normal-operation pulses which are differentiated from pulses produced by dv/dt tran-sient signals applied to said main electrodes of said transistor by the length of said pulses; and output circuit means coupled to the output of said pulse fil-ter; said output circuit means producing a switching function in response to the passage of a pulse signal through said pulse filter.
2. The circuit of claim 1, wherein said transistor means includes at least one MOSFET.
3. The circuit of claim 1, wherein said transistor means includes at least one NPN bipolar transistor.
4. The circuit of claim 1, which includes a voltage level shift means coupled to said logic level input circuit means and producing an output which translates the logic level of said input circuit means to a different voltage level.
5. The circuit of claim 1, wherein said current source means is a resistor in series with a voltage source.
6. The circuit of claim 2, wherein said current source means is a resistor in series with a voltage source.
7. The circuit of claim 1, wherein said output circuit means comprises a latch circuit.
8. The circuit of claim 6, wherein said output circuit means comprises a latch circuit.
9. A gate driver for an MOS circuit has an input logic circuit means providing the signal informa-tion for commanding the desired information for the operation of an MOS device; an MOS drive output circuit for connection to an MOS device gate circuit to operate said MOS device in accordance with the commands of said input logic circuit means; pulse generator means con-nected to said input logic circuit means for producing a train of output pulses of given duration in accor-dance with the logic circuit means input; transistor switch means having a control circuit connected to said pulse generator means and turned on and off by pulse signals from said pulse generator means, and having an output circuit; said output circuit of said transistor switch means coupled to said MOS drive output circuit to turn said MOS drive output circuit on and off in accordance with the commands of said input logic cir-cuit means; the improvement which comprises a pulse filter circuit coupled between said output circuit of said transistor switch means and said MOS drive output circuit; said pulse filter circuit passing pulses which have a pulse length of those generated by said pulse generator means but for filtering and not pass-ing shorter pulses with a high dv/dt, thereby to immu-nize said circuit from inadvertent dv/dt firing caused by noise pulses produced in said MOS drive output cir-cuit.
10. The gate driver circuit of claim 9 wherein said circuit has dv/dt immunity against pulses having a dv/dt of 10 volts per nanosecond or faster.
11. The gate driver circuit of claim 9, which further includes voltage level shifting circuit means coupled between said input logic circuit means and said pulse generator means for shifting the logic level voltage state from one voltage level to a second voltage level.
12. The gate driver circuit of claim 10, which further includes voltage level shifting circuit means coupled between said input logic circuit means and said pulse generator means for shifting the logic level voltage state from one voltage level to a second voltage level.
13. A level shifting circuit for translating a logic voltage state from one voltage level to a different voltage level with dv/dt immunity;
said circuit including logic level input circuit means;
a pulse generator circuit coupled to said input circuit means; transistor means having a control electrode coupled to the output of said pulse generator means and a pair of main electrodes a current sink means; said main electrodes of said transistor means connected in series with said current sink means; a pulse filter for passing only selected normal-operation pulses which are differentiated from pulses produced by dv/dt transient signals applied to said main electrodes of said tran-sistor by the length of said pulses; and output circuit means coupled to the output of said pulse filter; said output circuit means producing a switching function in response to the passage of a pulse signal through said pulse filter.
said circuit including logic level input circuit means;
a pulse generator circuit coupled to said input circuit means; transistor means having a control electrode coupled to the output of said pulse generator means and a pair of main electrodes a current sink means; said main electrodes of said transistor means connected in series with said current sink means; a pulse filter for passing only selected normal-operation pulses which are differentiated from pulses produced by dv/dt transient signals applied to said main electrodes of said tran-sistor by the length of said pulses; and output circuit means coupled to the output of said pulse filter; said output circuit means producing a switching function in response to the passage of a pulse signal through said pulse filter.
14. The circuit of claim 13, which includes a voltage level shift means coupled to said logic level input circuit means and producing an output which translates the logic level of said input circuit means to a different voltage level.
15. The circuit of claim 13, wherein said transistor means includes at least one MOSFET.
16. The circuit of claim 13, wherein said transistor means is a P channel MOSFET.
17. The circuit of claim 13, wherein said transistor means is an NPN transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US528,145 | 1983-08-31 | ||
| US52814590A | 1990-05-24 | 1990-05-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2043100A1 true CA2043100A1 (en) | 1991-11-25 |
Family
ID=24104431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002043100A Abandoned CA2043100A1 (en) | 1990-05-24 | 1991-05-23 | Circuit for providing dv/dt immunity |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP3092862B2 (en) |
| CA (1) | CA2043100A1 (en) |
| DE (1) | DE4114176A1 (en) |
| GB (1) | GB2244400B (en) |
| IT (1) | IT1248393B (en) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2763237B2 (en) * | 1992-11-02 | 1998-06-11 | 株式会社日立製作所 | Level shift circuit and inverter device using the same |
| DE4319977A1 (en) * | 1993-06-11 | 1994-12-15 | Mikroelektronik Und Technologi | Circuit arrangement for suppressing dynamic interference in digital circuits |
| US5545955A (en) * | 1994-03-04 | 1996-08-13 | International Rectifier Corporation | MOS gate driver for ballast circuits |
| US5514981A (en) * | 1994-07-12 | 1996-05-07 | International Rectifier Corporation | Reset dominant level-shift circuit for noise immunity |
| US5550436A (en) * | 1994-09-01 | 1996-08-27 | International Rectifier Corporation | MOS gate driver integrated circuit for ballast circuits |
| JP3429937B2 (en) * | 1996-01-12 | 2003-07-28 | 三菱電機株式会社 | Semiconductor device |
| JP3635975B2 (en) | 1999-03-02 | 2005-04-06 | 富士電機デバイステクノロジー株式会社 | Level shift circuit |
| DE19949389C1 (en) * | 1999-10-13 | 2001-02-01 | Gruendl & Hoffmann | Control circuit for MOSFET or insulated-gate bipolar transistor power end stage has power driver stage controlled by input stage with current sinks and associated current detectors |
| JP2001196906A (en) | 2000-01-14 | 2001-07-19 | Mitsubishi Electric Corp | Protection circuit, pulse generating circuit and drive circuit |
| JP2003169465A (en) * | 2001-11-30 | 2003-06-13 | Toshiba Corp | Gate drive circuit and power conversion device |
| JP4088466B2 (en) * | 2002-03-19 | 2008-05-21 | 三菱電機株式会社 | Power device drive circuit |
| AU2003269496A1 (en) | 2002-12-20 | 2004-07-14 | Matsushita Electric Industrial Co., Ltd. | Gate driver, motor driving device including the gate driver, and apparatus equipped with the motor driving device |
| JP2004215493A (en) * | 2002-12-20 | 2004-07-29 | Matsushita Electric Ind Co Ltd | Gate driver, motor drive including the gate driver, and equipment provided with the motor drive |
| JP4091038B2 (en) | 2003-11-19 | 2008-05-28 | 松下電器産業株式会社 | Sustain driver for plasma display and control circuit thereof |
| JP4360310B2 (en) | 2004-10-22 | 2009-11-11 | サンケン電気株式会社 | Drive device |
| JP2007243254A (en) * | 2006-03-06 | 2007-09-20 | Matsushita Electric Ind Co Ltd | Switch element driving circuit |
| JP4531075B2 (en) * | 2007-05-16 | 2010-08-25 | 株式会社日立製作所 | Semiconductor circuit |
| JP5326927B2 (en) | 2009-08-19 | 2013-10-30 | 富士電機株式会社 | Level shift circuit |
| JP5018866B2 (en) | 2009-11-19 | 2012-09-05 | サンケン電気株式会社 | Level shift circuit and switching power supply device |
| JP5466545B2 (en) | 2010-03-17 | 2014-04-09 | 株式会社 日立パワーデバイス | Level shift circuit and power conversion device |
| US8044699B1 (en) | 2010-07-19 | 2011-10-25 | Polar Semiconductor, Inc. | Differential high voltage level shifter |
| JP5880225B2 (en) * | 2012-04-02 | 2016-03-08 | 富士電機株式会社 | Semiconductor device |
| US8633745B1 (en) | 2012-08-30 | 2014-01-21 | Allegro Microsystems, Llc | Circuits and related techniques for driving a high side of a half bridge circuit |
| JP5862520B2 (en) * | 2012-08-31 | 2016-02-16 | 三菱電機株式会社 | Inverse level shift circuit |
| US9859732B2 (en) * | 2014-09-16 | 2018-01-02 | Navitas Semiconductor, Inc. | Half bridge power conversion circuits using GaN devices |
| US9571093B2 (en) | 2014-09-16 | 2017-02-14 | Navitas Semiconductor, Inc. | Half bridge driver circuits |
| EP3157153B1 (en) * | 2015-10-15 | 2021-12-22 | Nxp B.V. | Dc-dc converters having a half-bridge node, controllers therefor and methods of controlling the same |
| US9831867B1 (en) | 2016-02-22 | 2017-11-28 | Navitas Semiconductor, Inc. | Half bridge driver circuits |
| US10230356B2 (en) | 2017-02-27 | 2019-03-12 | Allegro Microsystems, Llc | High-side output transistor circuit |
| CN111130533B (en) * | 2020-01-10 | 2023-03-24 | 电子科技大学 | High-speed high dv/dt inhibition ability's level shifter circuit |
| EP4224712A1 (en) * | 2022-02-08 | 2023-08-09 | NXP USA, Inc. | Circuits for inverters and pull-up/pull-down circuits |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3875516A (en) * | 1973-10-26 | 1975-04-01 | Rank Organisation Ltd | Discriminator circuits |
-
1991
- 1991-04-30 DE DE4114176A patent/DE4114176A1/en not_active Withdrawn
- 1991-05-08 IT ITMI911246A patent/IT1248393B/en active IP Right Grant
- 1991-05-13 GB GB9110324A patent/GB2244400B/en not_active Expired - Fee Related
- 1991-05-23 CA CA002043100A patent/CA2043100A1/en not_active Abandoned
- 1991-05-23 JP JP03118439A patent/JP3092862B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| GB2244400A (en) | 1991-11-27 |
| GB2244400B (en) | 1994-07-06 |
| GB9110324D0 (en) | 1991-07-03 |
| ITMI911246A1 (en) | 1992-11-08 |
| DE4114176A1 (en) | 1991-11-28 |
| JP3092862B2 (en) | 2000-09-25 |
| ITMI911246A0 (en) | 1991-05-08 |
| JPH04230117A (en) | 1992-08-19 |
| IT1248393B (en) | 1995-01-11 |
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Legal Events
| Date | Code | Title | Description |
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| FZDE | Discontinued |