JP3117696B2 - Electronic circuit - Google Patents

Electronic circuit

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Publication number
JP3117696B2
JP3117696B2 JP02117776A JP11777690A JP3117696B2 JP 3117696 B2 JP3117696 B2 JP 3117696B2 JP 02117776 A JP02117776 A JP 02117776A JP 11777690 A JP11777690 A JP 11777690A JP 3117696 B2 JP3117696 B2 JP 3117696B2
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JP
Japan
Prior art keywords
circuit
drive
terminal
control
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP02117776A
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Japanese (ja)
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JPH033415A (en
Inventor
エフ ヴェゲネル アルミン
Original Assignee
コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ
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Priority to US07/349,365 priority Critical patent/US4989127A/en
Priority to US349365 priority
Application filed by コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ filed Critical コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ
Publication of JPH033415A publication Critical patent/JPH033415A/en
Application granted granted Critical
Publication of JP3117696B2 publication Critical patent/JP3117696B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/38Means for preventing simultaneous conduction of switches
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/538Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04Modifications for accelerating switching
    • H03K17/041Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0412Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/04123Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06Modifications for ensuring a fully conducting state
    • H03K17/063Modifications for ensuring a fully conducting state in field-effect transistor switches
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

Description

Description: FIELD OF THE INVENTION The present invention relates to an electronic circuit for driving an electronic device having a control terminal through which a capacitive current flows during a turn-off period.

In many applications, it is necessary to supply a load with a current of variable frequency or amplitude. To achieve this with high efficiency and minimal required circuit component size and cost, it is preferred to operate the output power stage in switched mode. Normally, power connected in series between both ends of a DC power supply
A circuit using two power transistors such as a MOSFET or an IGBT and connecting a load to a connection point between these two output transistors, that is, a so-called half-bridge circuit is used.

Applications for such circuits include high intensity gas discharges (HI
D) There are electronic ballasts for lamps, switching mode power supply circuits with high switching frequency and motor drivers for electronically rectified DC and AC motors. A control method generally applied to such an integrated circuit (IC) is to adjust current or power using pulse width modulation as a control signal to determine an arc current, a motor torque, and the like.

A major problem encountered in the design of such a half-bridge circuit is how to drive the upper one of the two power devices (transistors). The upper device is the upper switch with respect to the output terminal of the half bridge circuit. The voltage at such an output terminal of the half-bridge circuit varies between approximately 0 volts and the voltage of the DC feed line, which voltage is 500 volts for a 230 volt power line.
It can be as high as V.

To minimize the size of the circuit components and to make any noise generated by the inverter or switched mode amplifier inaudible, the half-bridge output circuit is frequently operated at frequencies above 20 kHz and is audible by this circuit. Avoid noise.

A drive circuit for a switched half-bridge output circuit must satisfy a number of conditions, including the following:

 The breakdown voltage is at least 500V;

The gate drive current is sufficient to increase the switching speed of the power transistors and reduce the switching losses.

-Reduce gate drive current to minimize electromagnetic interference.

-Ensure that the two power devices are not conducting simultaneously to prevent the DC power supply circuit from being short-circuited (prevention of shoot-through).

One output signal of the microcontroller, i.e. an input signal level of 5 to 15 volts, for each branch of each half-bridge circuit, allowing direct addressing without external delay circuits.

The allowable range of the slew rate of the output voltage during the switching period is up to 5-10 V / ns, especially with dielectric loads.

 -The switching frequency response is 500 kHz.

 -Lower power consumption.

[Conventional technology]

Conventional discrete drive circuits fall into two categories: fast-acting, relatively inefficient, and therefore undesirably high power consumption, or efficient but slow-acting.

European Patent Application No. 0264614 discloses that a resistor should be connected between each output transistor and a common node connecting the load, or that the rising edge of the turn-on input signal should be sufficiently delayed. Teach that the other transistor should be completely turned on.

For relatively complex high voltage integrated circuits that prevent shoot-through, see HFPC, May 1988, "Proceedings" No. 237-
“An HVIC MOSFET / IGT Drive for Half-Bridge” on page 245
Topologies ".

U.S. Pat. No. 4,740,717 teaches using a hysteresis circuit in the half-bridge power stage to prevent noise generated in the integrated circuit from undesirably changing the state of the output device.

Other techniques for improving shoot-through prevention have very different configurations. Although pulse transformers have been used successfully, they are expensive. Although optical couplers provide good isolation of the devices above the full-wave output stage, they are slow and often not very accurate, and the power consumption of the internal light emitting diodes is significantly higher.

[Summary of the Invention]

It is an object of the present invention to provide a half-bridge high-voltage switching device with a minimum level of electromagnetic interference.

It is another object of the present invention to provide an interface drive circuit for a half-bridge output circuit that automatically adapts to the gate current and capacitance of the output power device.

It is a further object of the present invention to protect one output device from turning on, so that it does not undergo shoot-through caused by the Miller capacitance of the other turned off output device. Is to do.

Yet another object of the present invention is to provide a method for controlling a transistor
An object of the present invention is to make it possible to control the gate drive current of a transistor regardless of the gate drive impedance when turning off.

According to the present invention, in order to achieve these objects, a first electronic device having a current path and a control terminal for controlling the current path; and a drive input terminal for receiving a drive input signal; A drive output terminal connected to the control terminal; a buffer having a buffer input terminal connected to one of the drive input terminals and a buffer output terminal connected to the drive output terminal; A controllable current sink connected and operative to discharge the voltage at the drive output terminal; and a first sense input terminal connected to one of the drive input terminals, a second sense input connected to the control terminal. A first drive circuit comprising: a detection and delay circuit having a terminal and a detection output terminal connected to the current sink; wherein the detection and delay circuit comprises a first control circuit at the first detection input terminal. Operating to activate the current sink under combination control of a voltage and a second control voltage lower than a predetermined low voltage value at the second sensing input terminal; and An electronic circuit operable to deactivate the current sink under combination control with a second control voltage higher than a predetermined high voltage value at the second sensing input.

In a preferred embodiment of the present invention, the circuit part for detecting the control voltage of the transistor includes a Schmitt trigger circuit, and the triggering level in the falling direction (transistor is turned off) of the trigger circuit is determined by turning the transistor on / off. An off-voltage or less, and a triggering level of the trigger circuit for a rising signal is set higher than a turn-on / turn-off voltage of the transistor.

Furthermore, in a preferred embodiment of the invention, the current sink stage is constituted by a transistor having one current carrying electrode connected to the control terminal, the transistor receiving and driving one signal from the Schmitt trigger circuit. It is controlled by a gate that receives the other signal based on the input signal to the circuit.

In still another preferred embodiment of the present invention, the low-voltage drive circuit for the high-voltage half-bridge circuit includes a lower drive circuit for driving the lower transistor of the half-bridge circuit, and an upper drive circuit for driving the upper transistor. And these upper and lower drive circuits turn on / off each transistor.
It has a similar first and second stage that turns off and sinks capacitive current from the control terminal of the transistor.

In yet another preferred embodiment, the high voltage half-bridge switched power circuit has upper and lower field effect transistors at an output terminal, and a lower driver circuit drives a first of the output transistor gates; A second stage for sinking a mirror capacitive current from the first and second stages, wherein the level shift circuit supplies turn-on and turn-off pulses to the upper drive circuit, and the upper drive circuit comprises the first and second stages. , Except that a latch circuit for supplying a control signal to the lower drive circuit is added.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, the high-voltage half-bridge circuit shown in FIG.
An upper field-effect transistor T1 and a lower field-effect transistor T2 having the same configuration and connected in series between cc and a ground point are provided. A load is connected to a terminal OUT, which is a common connection point for these two transistors. Control electrodes of the transistors T1 and T2, that is, the gate is connected to the terminals G u and G L novel high interface circuit 11.

The interface circuit 11 is formed as one integrated circuit, which includes upper and lower drive circuits Du and DL having substantially the same configuration as shown, a level shift circuit LS for control pulses for the upper drive circuit Du, Includes the four main sub-circuits with the control circuit CON. The control circuit CON receives an input signal from a microcontroller or other applied special unit that determines when and when each transistor T1 and T2 is turned on, performs a protection function, and is connected to the level shift circuit LS. A signal is supplied to the side drive circuit DL.

According to the invention, each drive circuit has an amplifier or a buffer stage.
BUF, the transistor M1, and the detection and delay circuit SWO are provided, the output terminal of the buffer stage BUF is connected to each terminal Gu or GL, and the gate control voltage, gate turn on and gate turn Supplying off current, the drain electrode of transistor M1 is connected to the gate of power transistor T1 or T2, and this transistor M1 functions as a current sink for the capacitance (mirror capacitance) to the gate of the power transistor, and also detects and delays circuit SWO may turn the transistor M1 when the gate voltage at the terminals G u and G L drops below selected minimum value
The transistor M1 is turned on, and the transistor M1 is turned off when the gate voltage rises above a predetermined higher voltage.

For convenience of explanation, the structure and operation of the detection and delay circuit SWO will be described with respect to the lower drive circuit DL. The circuit SWO includes a schmitt trigger circuit 13 connected to the gate voltage terminal GL . When the power transistor T2 has a gate turn-on / turn-off voltage of at least 2.0 volts, and the supply voltage supplied by the power supply 14 in the interface circuit 11 is 12 volts, the trigger circuit 13 The design is such that the state switches at about 1.8 volts for a negative going signal and about 6 volts for a positive going signal. The output of the trigger circuit 13 is inverted by an inverter 15 and supplied as one input to a NAND gate 17. The output of gate 17 is an inverting amplifier
The signal is amplified at 19 and supplied to the transistor M1 as control or gate voltage.

The drive circuit DL receives two input signals from the logic control circuit CON, and one of the input signals IN L is a turn-on / turn-off signal for the buffer BUF, and the other inverted signal IN
NL is the second input signal to gate 17. The detection and delay circuit SWO having such a configuration operates as follows.

When the turn-on signal IN L is received, the output of the buffer BuF goes high, turning on the transistor T2. This because the input signal INN L becomes low level at the same time, the output of NAND gate 17 goes high, inverter
The output of 19 goes low, turning off sink transistor M1. When the voltage of the gate terminal GL passes the rising trigger level of the Schmitt trigger circuit 13, the output of the trigger circuit goes high and the output of the inverter 15 goes low. The output of NAND gate 17 remains high.

When to turn off the transistor T2, the input signal IN L and INN L, respectively low and high levels. The voltage of the gate terminal G L drops with a slew rate determined by the capacitance of the gate of the current capacity and the transistor T2 of the buffer BUF (mainly Miller effect). The output of NAND gate 17 does not change immediately. The reason is that the voltage GL
Is smaller than or equal to the turn-off value of the transistor T2, and the state of the trigger circuit 13 does not change until it falls to the trigger level value for the Schmitt trigger circuit 13. Then, the output of the trigger circuit 13 goes low,
15 outputs go high. Since the other input of NAND gate 17 is already high, the output of NAND gate 17 is low, which turns on sink transistor M1 via inverter 19. Thus, until the transistor T2 is completely turned off, no low impedance sink is provided to the gate of the transistor T2. This ensures that the value of dV / dt does not rise to a high level that creates a significant EMI field.

Functionally similar parts of the upper drive circuit Du are denoted by the same symbols as those of the lower drive circuit DL, and these parts perform the turn-on and turn-off functions in exactly the same way. In the upper drive circuit Du, a signal IN u is set from a latch circuit LA which is set or reset by current pulses from two current mirrors in the level shift circuit LS.
And INN u . The use of such a short current pulse in combination with a latch circuit can reduce static power consumption and approach zero. Also, the latch circuit can be configured to be in a reset state whenever it is powered up, thus ensuring that transistor T1 is turned off.

One output transistor is turned on and turned off
When turned off and the other output transistor remains turned off, each turn on of one output transistor induces a large Miller capacitance current in the gate circuit of the other transistor. The circuit according to the invention prevents such a current from turning on the other transistor undesirably (shoot-through) in order to provide a current sink stage transistor M1.

Preferably, the control logic circuit CON provides a short delay time of about 500 ns between the turn-off time of one power transistor and the turn-on time of the other transistor to further prevent shoot-through as described above. I do. The control logic is also provided with a normal failure prevention mechanism, which switches off both power transistors in the event of a fault signal, as is well known. After a short delay, the lower transistor T2 turns on and charges the bootstrap capacitor in the power supply circuit 14, while the upper transistor T1 remains off.

The integrated HVIC as shown is “IEEE International Sol
id-State Circuits Con. "at Wacyk, Amato and Rumenni
(1986, pp. 16-17) "A Power
IC with CMOS Analog Control ". If the high-voltage device (power transistor) is an LDMOS transistor designed based on the RESURF principle, set V cc = 500VDC and set the CMOS transistor to 3
Preferably, a voltage as low as μm appears. The process architecture can be based on a dual poly, dual well CMOS process with self-aligned n and p wells. CM in the upper drive circuit Du
The OS circuit is isolated from the p-type ground substrate by an n + buried layer and an n-well diffusion region. Thus, the upper drive circuit CM
Insulating the OS from high voltages is the same as isolating the LDMOS transistors from high voltages. By such a process, the breakdown voltage for the floating well and the LDMOS transistor can be set to 600 V or more, whereby a sufficient margin can be given to the 500 V DC power supply line.

In the test circuit according to the present invention, when the gate voltage of the power transistor falls below the minimum threshold voltage of the transistor, the transistor M1 switches on and the power device (transistor) keeps completely turning off. . Transistor M1 continued to switch on while the voltage at gate terminal GL was less than 0.5 volts. Transistor M1 turns NA high after the level of input signal IN goes high.
He turned off immediately after ND Gate 17. Thus, such adaptive switching may result in a negative slope of the power device gate voltage which is affected by the device dimensions (device gate and Miller capacitance), the value of the high voltage power supply and the general configuration of the power supply circuit. Automatically adapted.

Tested with an experimental chip, 5 ohms with an 800 ohm resistive load in series with an inductance of 1 mh
Good performance was exhibited for DC voltages up to 00V. When operated at a supply voltage of 300 V at a frequency of 300 kHz and with a large inductive load, the value of dV / dt was 11 V / ns or more without causing any circuit or chip failure.

The transistor M1 and the circuit SWO dynamically change the gate discharge impedance of the transistor T2 depending on the actual gate voltage. Because of this, the applications of such circuits are wide. The reason for this is that the parameters of the power transistor, the DC supply voltage and the configuration of the power stage and its general operation can be broadened.

When pulse width modulation is used, the performance of the driving circuits DL and Du becomes critical. The drive current needs to be relatively high to shorten the switching time and thus reduce the switching losses. At the same time, the switching speed has an upper limit imposed by the recovery time of the high voltage device carrying the load current and flywheel current. Drive circuit is 10V / ns dV / ds
, And the gate current drawn by the buffer stage must be limited according to the value of the gate-drain (Miller) capacitance.

In order to be able to use a wide variety of power devices, the peak current that can be extracted by the HVIC 11 is selected to be 100 mA. In this case, the optimum driving current for a specific power transistor is determined by an external resistor (not shown).
Obtained by Alternatively, the rate of rise of the reverse voltage of the body diode can be limited by turning on the snubber circuit. Such a circuit is
When turned on, the amplitude value of the reverse recovery current is also reduced.

If the gate capacitance is discharged very quickly by making the gate current too large, unwanted electromagnetic interference (EM) can occur due to the coupling of the switching pulse edges to the ground line.
I). Therefore, it is desirable to limit the value of the sink current to 300 mA.

The present invention is not limited to the above-described example, but may include various modifications. For example, a half-bridge circuit and drive circuit can be used for each phase of a polyphase motor, in which case the half-bridge is sequentially switched in phase with respect to the other. By controlling both the switching frequency and the pulse width to change the power level supplied to the load, the load can be made to respond to the amount of power extracted.

If it is not desired to drive the output of the half-bridge circuit in a balanced manner, but one end of the load must be at ground potential, a single drive circuit according to the present invention will provide the desired characteristics of the power switching device. And a higher frequency response without erroneous turn-on operation due to Miller capacitance affecting the gate voltage.

Although the present invention has been described with respect to a power field effect transistor, it is clear that the detection and delay action of the circuit SWO can be applied to any drive circuit in which compensation for a current such as the Miller effect is desired. is there.

[Brief description of the drawings]

 FIG. 1 is a bridge diagram of an electronic circuit according to the present invention. T1, T2… Power (output) transistors DU, DL… Drive circuit LS… Level shift circuit CON… Control circuit BUF… Buffer stage M1… Sink transistor SWO… Detection and delay circuit GU, GL… Gate voltage terminal LA Latch circuit 11 Interface circuit 13 Schmitt trigger circuit 14 Power supply circuit 15 Inverter 17 NAND gate 19 Inverting amplifier

Claims (5)

(57) [Claims]
1. A current path and a control terminal of the power flow passage control and;; (T2 T1); a first electronic device having a (G U G L) - driving the input terminal of the drive input signal received ( IN U , INN U ; I
N L, INN L); - the drive output terminal is connected to a control terminal; - a buffer output terminal connected to the buffer input terminal and the driving output terminal is connected to one of said drive input terminal A controllable current sink (M1) connected to the drive output terminal and operative to discharge the voltage at the drive output terminal; and a first buffer connected to one of the drive input terminals. A detection and delay circuit (SWO) having a detection input terminal, a second detection input terminal connected to the control terminal, and a detection output terminal connected to the current sink; Wherein the detection and delay circuit comprises a combination of a first control voltage at the first detection input terminal and a second control voltage lower than a predetermined low voltage value at the second detection input terminal. Said current sink under control Activating the current sink and deactivating the current sink under a combination control of the first control voltage and a second control voltage higher than a predetermined high voltage value at the second sensing input terminal. An electronic circuit designed to work.
2. The Schmitt trigger circuit (13) having a trigger input terminal connected to the second detection input terminal and having a trigger output terminal; and the first detection. A logic gate having a first gate input terminal connected to the input terminal, a second gate input terminal coupled to the trigger output terminal, and a gate output terminal coupled to the sensing output terminal. The electronic circuit according to claim 1, wherein:
The have; (G L G U) - wherein said first electronic device of the other control terminal of the other current path and said other current path control which is connected in series to the current path Two electronic devices (T2; T1); and-other drive input terminals (IN L , IN) for receiving other drive signals.
N L; IN U, INN U ) and the second drive circuit has a drive output terminal connected to the other control terminal (DL; and DU); a comprises, the first and second drive circuit 3. The electronic circuit according to claim 1, wherein the electronic circuit is functionally identical.
4. The first electronic device comprises a power transistor, the current path of which is connected between a high voltage supply node (Vcc) and an output node (OUT);-the second electronic device. 4. The electronic circuit according to claim 3, wherein the electronic circuit comprises a power transistor, and the other current path of the transistor is connected between the output node and a low voltage / power supply node (GND).
5. A drive circuit coupled to said drive input terminal of said first drive circuit and operative to provide a level-shifted drive input signal with respect to said other drive signal provided to said second drive circuit. 5. The electronic circuit according to claim 4, wherein the electronic circuit includes a level shift circuit.
JP02117776A 1989-05-09 1990-05-09 Electronic circuit Expired - Fee Related JP3117696B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US07/349,365 US4989127A (en) 1989-05-09 1989-05-09 Driver for high voltage half-bridge circuits
US349365 1989-05-09

Publications (2)

Publication Number Publication Date
JPH033415A JPH033415A (en) 1991-01-09
JP3117696B2 true JP3117696B2 (en) 2000-12-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP02117776A Expired - Fee Related JP3117696B2 (en) 1989-05-09 1990-05-09 Electronic circuit

Country Status (4)

Country Link
US (1) US4989127A (en)
EP (1) EP0397241B1 (en)
JP (1) JP3117696B2 (en)
DE (1) DE69011189T2 (en)

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DE69011189D1 (en) 1994-09-08
JPH033415A (en) 1991-01-09
US4989127A (en) 1991-01-29
EP0397241A1 (en) 1990-11-14
EP0397241B1 (en) 1994-08-03
DE69011189T2 (en) 1995-03-02

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