CA2015933A1 - Synchronisation des blocs dans les flux de donnees - Google Patents

Synchronisation des blocs dans les flux de donnees

Info

Publication number
CA2015933A1
CA2015933A1 CA2015933A CA2015933A CA2015933A1 CA 2015933 A1 CA2015933 A1 CA 2015933A1 CA 2015933 A CA2015933 A CA 2015933A CA 2015933 A CA2015933 A CA 2015933A CA 2015933 A1 CA2015933 A1 CA 2015933A1
Authority
CA
Canada
Prior art keywords
data stream
frame synchronisation
digits
stream frame
check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2015933A
Other languages
English (en)
Other versions
CA2015933C (fr
Inventor
Simon Daniel Brueckheimer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ericsson AB
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CA002296835A priority Critical patent/CA2296835A1/fr
Publication of CA2015933A1 publication Critical patent/CA2015933A1/fr
Application granted granted Critical
Publication of CA2015933C publication Critical patent/CA2015933C/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/33—Synchronisation based on error coding or decoding
    • H03M13/333—Synchronisation on a multi-bit block basis, e.g. frame synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Mobile Radio Communication Systems (AREA)
CA002015933A 1989-05-04 1990-05-02 Synchronisation des blocs dans les flux de donnees Expired - Lifetime CA2015933C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA002296835A CA2296835A1 (fr) 1989-05-04 1990-05-02 Synchronisation des blocs dans les flux de donnees

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8910255.2 1989-05-04
GB898910255A GB8910255D0 (en) 1989-05-04 1989-05-04 Data stream frame synchronisation

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CA002296835A Division CA2296835A1 (fr) 1989-05-04 1990-05-02 Synchronisation des blocs dans les flux de donnees

Publications (2)

Publication Number Publication Date
CA2015933A1 true CA2015933A1 (fr) 1990-11-04
CA2015933C CA2015933C (fr) 2000-03-28

Family

ID=10656213

Family Applications (2)

Application Number Title Priority Date Filing Date
CA002015933A Expired - Lifetime CA2015933C (fr) 1989-05-04 1990-05-02 Synchronisation des blocs dans les flux de donnees
CA002296835A Abandoned CA2296835A1 (fr) 1989-05-04 1990-05-02 Synchronisation des blocs dans les flux de donnees

Family Applications After (1)

Application Number Title Priority Date Filing Date
CA002296835A Abandoned CA2296835A1 (fr) 1989-05-04 1990-05-02 Synchronisation des blocs dans les flux de donnees

Country Status (9)

Country Link
EP (1) EP0396403B1 (fr)
JP (1) JP3046988B2 (fr)
AU (1) AU629334B2 (fr)
CA (2) CA2015933C (fr)
DE (1) DE69019777T2 (fr)
DK (1) DK0396403T3 (fr)
ES (1) ES2076314T3 (fr)
GB (2) GB8910255D0 (fr)
NO (1) NO304290B1 (fr)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01141436A (ja) * 1987-11-27 1989-06-02 Sony Corp フレーム同期化方法
EP0453876B1 (fr) * 1990-04-21 1997-06-11 Alcatel SEL Aktiengesellschaft Méthode de synchronisation pour systèmes de signaux numériques d'une hiérarchie synchrone et circuit et procédé pour la reconaissance de différentes structures de données
CA2055172A1 (fr) * 1990-12-10 1992-06-11 Joseph H. Condon Detection des erreurs et verrouillage de trame dans les paquets transmis dans une suite de cellules de longueur fixe
JP2655547B2 (ja) * 1991-03-13 1997-09-24 富士通株式会社 Ｃｒｃ演算方法及びａｔｍ交換方式におけるｈｅｃ同期装置
US5267249A (en) * 1991-05-09 1993-11-30 Codex Corporation Device and method for asynchronous cyclic redundancy checking for digital receivers
FI95982C (fi) * 1994-04-11 1996-04-10 Nokia Telecommunications Oy Menetelmä aikajakoisen tietoliikennesignaalin siirtämiseksi
GB9419785D0 (en) * 1994-09-30 1994-11-16 Plessey Telecomm Cyclic redundancy code checking
CA2206688C (fr) * 1994-12-12 2002-02-19 British Telecommunications Public Limited Company Systeme de transmission numerique pour le codage et le decodage de donnees d'attribut en symboles de controle d'erreurs des donnees principales
DE19519946A1 (de) * 1995-06-02 1996-12-05 Thomson Brandt Gmbh Verfahren zur Synchronisation eines aus Informationsdaten und einem anschließenden Prüfsummenfeld bestehenden empfangenen Datenblocks sowie Vorrichtung zur Durchführung des Verfahrens
JPH09284270A (ja) * 1996-04-19 1997-10-31 Nec Corp シンボル同期追従方法及びそれを適用したシンボル同期追従装置
JP2967748B2 (ja) * 1997-03-05 1999-10-25 日本電気株式会社 Ａｔｍセル同期回路
US20050114751A1 (en) * 2003-11-24 2005-05-26 Ungstad Steve J. Two input differential cyclic accumulator
US8611305B2 (en) 2005-08-22 2013-12-17 Qualcomm Incorporated Interference cancellation for wireless communications
US9071344B2 (en) 2005-08-22 2015-06-30 Qualcomm Incorporated Reverse link interference cancellation
US7933256B2 (en) * 2008-02-27 2011-04-26 Qualcomm Incorporated Coherent single antenna interference cancellation for GSM/GPRS/EDGE
US20100046660A1 (en) 2008-05-13 2010-02-25 Qualcomm Incorporated Interference cancellation under non-stationary conditions
US8995417B2 (en) 2008-06-09 2015-03-31 Qualcomm Incorporated Increasing capacity in wireless communication
US9237515B2 (en) 2008-08-01 2016-01-12 Qualcomm Incorporated Successive detection and cancellation for cell pilot detection
US9277487B2 (en) 2008-08-01 2016-03-01 Qualcomm Incorporated Cell detection with interference cancellation
US8503591B2 (en) 2008-08-19 2013-08-06 Qualcomm Incorporated Enhanced geran receiver using channel input beamforming
US8509293B2 (en) 2008-08-19 2013-08-13 Qualcomm Incorporated Semi-coherent timing propagation for GERAN multislot configurations
US9160577B2 (en) 2009-04-30 2015-10-13 Qualcomm Incorporated Hybrid SAIC receiver
US8787509B2 (en) 2009-06-04 2014-07-22 Qualcomm Incorporated Iterative interference cancellation receiver
US8831149B2 (en) 2009-09-03 2014-09-09 Qualcomm Incorporated Symbol estimation methods and apparatuses
US8619928B2 (en) 2009-09-03 2013-12-31 Qualcomm Incorporated Multi-stage interference suppression
US9673837B2 (en) 2009-11-27 2017-06-06 Qualcomm Incorporated Increasing capacity in wireless communications
US9509452B2 (en) 2009-11-27 2016-11-29 Qualcomm Incorporated Increasing capacity in wireless communications
CN110365342B (zh) * 2019-06-06 2023-05-12 中车青岛四方机车车辆股份有限公司 波形解码方法及装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE656364A (fr) * 1963-11-29
US3466601A (en) * 1966-03-17 1969-09-09 Bell Telephone Labor Inc Automatic synchronization recovery techniques for cyclic codes
US3466501A (en) * 1966-09-08 1969-09-09 Gordon W Young Self-illuminating devices and systems
US4729123A (en) * 1986-08-14 1988-03-01 General Datacomm, Inc. Method for establishing and maintaining synchronization between communicating multiplexers using checksum values

Also Published As

Publication number Publication date
EP0396403A1 (fr) 1990-11-07
NO304290B1 (no) 1998-11-23
JPH0380727A (ja) 1991-04-05
ES2076314T3 (es) 1995-11-01
JP3046988B2 (ja) 2000-05-29
CA2296835A1 (fr) 1990-11-04
GB2232040B (en) 1993-10-06
GB8910255D0 (en) 1989-06-21
AU629334B2 (en) 1992-10-01
GB9009933D0 (en) 1990-06-27
CA2015933C (fr) 2000-03-28
AU5470990A (en) 1990-11-08
NO901979D0 (no) 1990-05-03
NO901979L (no) 1990-11-05
EP0396403B1 (fr) 1995-05-31
DK0396403T3 (da) 1995-07-03
DE69019777D1 (de) 1995-07-06
DE69019777T2 (de) 1995-11-09
GB2232040A (en) 1990-11-28

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