CA2007051A1 - Processeur de signaux - Google Patents

Processeur de signaux

Info

Publication number
CA2007051A1
CA2007051A1 CA2007051A CA2007051A CA2007051A1 CA 2007051 A1 CA2007051 A1 CA 2007051A1 CA 2007051 A CA2007051 A CA 2007051A CA 2007051 A CA2007051 A CA 2007051A CA 2007051 A1 CA2007051 A1 CA 2007051A1
Authority
CA
Canada
Prior art keywords
signal processor
coupled
arithmetic
data
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2007051A
Other languages
English (en)
Other versions
CA2007051C (fr
Inventor
Kevin D. Balmforth
Gary A. Bates
Steven P. Davies
Hans L. Habereder
R. Loyd Harrison
Donald M. Hopp
George G. Ricker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of CA2007051A1 publication Critical patent/CA2007051A1/fr
Application granted granted Critical
Publication of CA2007051C publication Critical patent/CA2007051C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8092—Array of vector units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8061—Details on data memory access
    • G06F15/8069—Details on data memory access using a cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
CA002007051A 1989-01-27 1990-01-03 Processeur de signaux Expired - Fee Related CA2007051C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/303,790 US5187795A (en) 1989-01-27 1989-01-27 Pipelined signal processor having a plurality of bidirectional configurable parallel ports that are configurable as individual ports or as coupled pair of ports
US303,790 1989-01-27

Publications (2)

Publication Number Publication Date
CA2007051A1 true CA2007051A1 (fr) 1990-07-27
CA2007051C CA2007051C (fr) 1994-06-21

Family

ID=23173709

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002007051A Expired - Fee Related CA2007051C (fr) 1989-01-27 1990-01-03 Processeur de signaux

Country Status (7)

Country Link
US (1) US5187795A (fr)
EP (1) EP0380098B1 (fr)
JP (1) JP2550197B2 (fr)
AU (1) AU4883790A (fr)
CA (1) CA2007051C (fr)
DE (1) DE69030128T2 (fr)
ES (1) ES2098230T3 (fr)

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US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
JP3005250B2 (ja) * 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
US5303349A (en) * 1990-06-06 1994-04-12 Valitek, Inc. Interface for establishing a number of consecutive time frames of bidirectional command and data block communication between a Host's standard parallel port and a peripheral device
JP2651267B2 (ja) * 1990-07-26 1997-09-10 富士通株式会社 演算処理装置及び演算処理方法
JP2861560B2 (ja) * 1991-12-25 1999-02-24 松下電器産業株式会社 データ処理装置
WO1993021577A1 (fr) * 1992-04-09 1993-10-28 Electronic Associates, Inc. Systeme d'ordinateur a multiprocesseur et procede pour le traitement en parallele d'operations scalaires
US5640521A (en) * 1992-06-17 1997-06-17 Texas Instruments Incorporated Addressable shadow port and protocol with remote I/O, contol and interrupt ports
JPH0628485A (ja) * 1992-07-09 1994-02-04 Toshiba Corp テクスチャーアドレス生成器、テクスチャーパターン生成器、テクスチャー描画装置及びテクスチャーアドレス生成方法
US5542074A (en) * 1992-10-22 1996-07-30 Maspar Computer Corporation Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount
US5717947A (en) * 1993-03-31 1998-02-10 Motorola, Inc. Data processing system and method thereof
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
US5717950A (en) * 1994-01-11 1998-02-10 Hitachi, Ltd. Input/output device information management system for multi-computer system
US5524267A (en) * 1994-03-31 1996-06-04 International Business Machines Corporation Digital I/O bus controller circuit with auto-incrementing, auto-decrementing and non-incrementing/decrementing access data ports
US6279099B1 (en) * 1994-04-29 2001-08-21 Sun Microsystems, Inc. Central processing unit with integrated graphics functions
US5734874A (en) * 1994-04-29 1998-03-31 Sun Microsystems, Inc. Central processing unit with integrated graphics functions
US5524258A (en) * 1994-06-29 1996-06-04 General Electric Company Real-time processing of packetized time-sampled signals employing a systolic array
JPH0830577A (ja) * 1994-07-15 1996-02-02 Mitsubishi Electric Corp Ｓｉｍｄプロセッサ
US5600793A (en) * 1994-12-20 1997-02-04 International Business Machines Corporation Method and system of bi-directional parallel port data transfer between data processing systems
US5784076A (en) * 1995-06-07 1998-07-21 International Business Machines Corporation Video processor implementing various data translations using control registers
US5764558A (en) * 1995-08-25 1998-06-09 International Business Machines Corporation Method and system for efficiently multiplying signed and unsigned variable width operands
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
KR0174977B1 (ko) * 1995-12-30 1999-04-01 김광호 멀티 옵션을 지원하는 장치 및 그 제어방법
US5896543A (en) * 1996-01-25 1999-04-20 Analog Devices, Inc. Digital signal processor architecture
JPH1165989A (ja) * 1997-08-22 1999-03-09 Sony Computer Entertainment:Kk 情報処理装置
US6002882A (en) * 1997-11-03 1999-12-14 Analog Devices, Inc. Bidirectional communication port for digital signal processor
US6061779A (en) * 1998-01-16 2000-05-09 Analog Devices, Inc. Digital signal processor having data alignment buffer for performing unaligned data accesses
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6590901B1 (en) * 1998-04-01 2003-07-08 Mosaid Technologies, Inc. Method and apparatus for providing a packet buffer random access memory
US6378017B1 (en) * 1998-07-08 2002-04-23 Nms Communications Corporation Processor interconnection
US6519695B1 (en) * 1999-02-08 2003-02-11 Alcatel Canada Inc. Explicit rate computational engine
US7058862B2 (en) * 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
US7506136B2 (en) 1999-04-09 2009-03-17 Clearspeed Technology Plc Parallel data processing apparatus
US7526630B2 (en) 1999-04-09 2009-04-28 Clearspeed Technology, Plc Parallel data processing apparatus
US7627736B2 (en) 1999-04-09 2009-12-01 Clearspeed Technology Plc Thread manager to control an array of processing elements
GB2348977A (en) * 1999-04-09 2000-10-18 Pixelfusion Ltd Parallel data processing systems with a SIMD array
US7802079B2 (en) 1999-04-09 2010-09-21 Clearspeed Technology Limited Parallel data processing apparatus
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US7225383B1 (en) * 2000-01-19 2007-05-29 Sun Microsystems, Inc. System and method for enhancing communication between devices in a computer system
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US6968417B1 (en) * 2002-03-21 2005-11-22 Advanced Micro Devices, Inc. Method and apparatus for reducing latency in a peripheral interface circuit of an I/O node of a computer system
EP1544630B1 (fr) * 2003-12-17 2008-05-14 STMicroelectronics Limited Scan test avec multiplexage de TAP dépendant du temps
US7346761B2 (en) * 2005-10-08 2008-03-18 National Chung Cheng University Alu with auxiliary units for pre and post processing of operands and immediate value within same instruction cycle
US8755515B1 (en) 2008-09-29 2014-06-17 Wai Wu Parallel signal processing system and method
CN108364065B (zh) 2018-01-19 2020-09-11 上海兆芯集成电路有限公司 采布斯乘法的微处理器
CN111651138B (zh) * 2020-05-28 2023-11-03 Oppo广东移动通信有限公司 一种集成电路、信号处理方法及装置、存储介质

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US3828325A (en) * 1973-02-05 1974-08-06 Honeywell Inf Systems Universal interface system using a controller to adapt to any connecting peripheral device
FR2296221A1 (fr) * 1974-12-27 1976-07-23 Ibm France Systeme de traitement du signal
US4541048A (en) * 1978-10-06 1985-09-10 Hughes Aircraft Company Modular programmable signal processor
US4598358A (en) * 1980-02-11 1986-07-01 At&T Bell Laboratories Pipelined digital signal processor using a common data and control bus
JPS5779551A (en) * 1980-11-06 1982-05-18 Nec Corp Information transfer device
US4393468A (en) * 1981-03-26 1983-07-12 Advanced Micro Devices, Inc. Bit slice microprogrammable processor for signal processing applications
US4627026A (en) * 1982-10-21 1986-12-02 I.R.C.A.M. (Institut De Recherche Et De Coordination Accoustique/Misique Digital real-time signal processor
US4833605A (en) * 1984-08-16 1989-05-23 Mitsubishi Denki Kabushiki Kaisha Cascaded information processing module having operation unit, parallel port, and serial port for concurrent data transfer and data processing
US4716527A (en) * 1984-12-10 1987-12-29 Ing. C. Olivetti Bus converter
US4794517A (en) * 1985-04-15 1988-12-27 International Business Machines Corporation Three phased pipelined signal processor
US4744078A (en) * 1985-05-13 1988-05-10 Gould Inc. Multiple path multiplexed host to network data communication system
US4972314A (en) * 1985-05-20 1990-11-20 Hughes Aircraft Company Data flow signal processor method and apparatus
US4760525A (en) * 1986-06-10 1988-07-26 The United States Of America As Represented By The Secretary Of The Air Force Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction
US4912636A (en) * 1987-03-13 1990-03-27 Magar Surendar S Data processing device with multiple on chip memory buses
KR0134042B1 (ko) * 1987-07-17 1998-05-15 이우에 사또시 디지탈 신호처리장치 및 신호처리방법
US4878166A (en) * 1987-12-15 1989-10-31 Advanced Micro Devices, Inc. Direct memory access apparatus and methods for transferring data between buses having different performance characteristics
US4959776A (en) * 1987-12-21 1990-09-25 Raytheon Company Method and apparatus for addressing a memory by array transformations

Also Published As

Publication number Publication date
EP0380098A3 (fr) 1991-08-14
EP0380098B1 (fr) 1997-03-12
ES2098230T3 (es) 1997-05-01
AU4883790A (en) 1990-08-16
JP2550197B2 (ja) 1996-11-06
CA2007051C (fr) 1994-06-21
EP0380098A2 (fr) 1990-08-01
US5187795A (en) 1993-02-16
DE69030128T2 (de) 1997-10-09
JPH0333915A (ja) 1991-02-14
DE69030128D1 (de) 1997-04-17

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