CA1322575C - Frequency output generator - Google Patents
Frequency output generatorInfo
- Publication number
- CA1322575C CA1322575C CA000609458A CA609458A CA1322575C CA 1322575 C CA1322575 C CA 1322575C CA 000609458 A CA000609458 A CA 000609458A CA 609458 A CA609458 A CA 609458A CA 1322575 C CA1322575 C CA 1322575C
- Authority
- CA
- Canada
- Prior art keywords
- latch
- output
- bit rate
- capacity
- word length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
Landscapes
- Measuring Volume Flow (AREA)
- Manipulation Of Pulses (AREA)
- Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
IMPROVED FREQUENCY OUTPUT GENERATOR
ABSTRACT OF THE DISCLOSURE
A frequency generator which produces a series of output pulses proportional to the input pulse applied thereto is disclosed. An input signal is converted into digital signal having a word length which exceeds the capacity of the components within the generator. A
microprocessor directs a portion of the word to a first latch and the remainder of the word to a second latch over a common bus, each latch and the bus having a capacity less than the total word length of the digital signal being transmitted. The output of the latches are connected to a plurality of rate multipliers connected in a cascade arrangement producing an output signal representative of the input signal. A programmable frequency divider is provided permitting the introduction of operator applied inputs to scale the resulting output signal produced by the generator.
ABSTRACT OF THE DISCLOSURE
A frequency generator which produces a series of output pulses proportional to the input pulse applied thereto is disclosed. An input signal is converted into digital signal having a word length which exceeds the capacity of the components within the generator. A
microprocessor directs a portion of the word to a first latch and the remainder of the word to a second latch over a common bus, each latch and the bus having a capacity less than the total word length of the digital signal being transmitted. The output of the latches are connected to a plurality of rate multipliers connected in a cascade arrangement producing an output signal representative of the input signal. A programmable frequency divider is provided permitting the introduction of operator applied inputs to scale the resulting output signal produced by the generator.
Description
t~22~75 The present invention relates, in general, to a frequency generator and, more particularly, to a frequency generator that produces a series of output pulses that have a frequency proportional to the input frequency applied thereto.
Various types of instrumentation are available to produce a train of output pulses having a frequency which is proportional to the input signal applied thereto. Such instrumentation includes both analog and digital techniques~
A typical analog technique utilizes a voltage to frequency converter in single chip form or in discrete circuit form.
Such techniques require costly reference levels and variable resistors or switches for calibration purposes.
Alternatively, combinations of digital and analog techniques can be utilized but they have similar disadvantages with respect to reference levels and/or calibration. Complete microcomputer techniques require timer outputs which utilize a significant amount of execution time, particularly at higher frequencies. Other techniques include a combination of microcomputers, bit rate multipliers and digital counters to achieve high resolution over a broad frequency range.
Because of the foregoing, it has become desirable to develop a generator which produces an output signal representative of the frequency of the input signal that is, 1322~73 applied thereto, and which utilizes relatively inexpensive components to produce an output signal having a high degree of resolution over a broad frequency range.
The present invention solves the problems associated with the prior art and other problems by providing a frequency generator circuit that utilizes a minimum number of inexpensive components to produce an output signal representative of the frequency of the input signals applied thereto.
According to the present invention, a generator for producing a series of output pulses having a frequency that is proportional to the analog input signal applied thereto comprises means for converting the analog input signal into a digital signal having a predetermined word length, means for transmitting a portion of said word length to a first latch means and the remaining portion of said word length to a second latch means, bus means interconnecting said transmitting means and said first latch means and said second latch means, said bus means having a capacity which approximates said portion of said word length transmitted to said first latch means, and a plurality of rate multipliers connected to said first latch means and said second latch means producing an output signal representative of the analog input signal.
Further features of the invention will be apparent from the following description of an exemplary preferred embodiment thereof, with reference to the accompanying drawings, in which:
Fig. 1 shows stages in the processing of two mass flowmeter signals in a generator in accordance with the present invention.
Fig. 2A depicts circuit signal conditioning and microprocessing elements of the circuit.
1322~7~
Fig. 2B depicts latching and rate multiplying elements of the circuit which may be connected to the Fig~ 2A
circuit.
Fig. 2C depicts programmable frequency divider elements of the circuit which may be connected to the Fig. 2B
circuit.
Referring now to the drawings where the illustration is for the purpose of describing the preferred embodiment of the present invention and is not intended to limit the invention hereto, Figures 2A, 2~ and 2~ of the drawings together form a schematic diagram of the circuit 10 which embodies the present invention. The circuit 10 includes a signal conditioner 12, microprocessors 14 and 16 as shown in Figure 2A, electronic latches 18, 20 and 22, along with bit rate multipliers 24, 26 and 28, as shown in Figure 2B, and a programmable frequency divider 30 as shown in Figure 2C, all interconnected as shown.
The signal conditioner 12 receives one or more analog signals, amplifies same, filters the signals to reduce common mode noise and then digitizes same. The output of the signal conditioner 12 is connected to the input to microprocessor 14. It should be noted that even though two microprocessors (microprocessor 14 and 16) are shown, one microprocessor with sufficient capacity can be used in place thereof.
Microprocessor 14 produces a plurality of output signals which are transmitted to electronic latches 18, 20 and 22 via a bus 32. The output signals from the microprocessor 14 include an enable signal to allow the transmission of bits to latch 18, an enable signal to allow transmission of bits to latch 20, and a control signal on bus 32. The capacity of bus 32 is limited in that it is an 8 bit bus. Electronic latches 18, 20 and 22 are commercially available 8 bit latches, such as Part No. 74LS374 available from Texas Instruments, Inc. The outputs of latch 18 are connected to .
, :
1322~75 the inputs to bit rate multipliers 24 and 26, and the outputs of latch 20 are connected to the inputs to bit rate multipliers 26 and 28. The bit rate multipliers 24, 26 and 28 are commercially available devices, such as Part No. 7497 available from Texas Instruments, Inc. A clock having an output frequency rj is also connected as an input to each of the bit rate multipliers 24, 26 and 28 which are interconnected in a cascade arrangement. The outputs of bit rate multipliers 26 and 28 are connected to a commercially available OR gate 34, such as Part No. 74LS02 available from Texas Instruments, Inc. The output of OR gate 34 is connected to an input to the programmable frequency divider 30.
As previously mentioned, latch 22 receives input signals over bus 32 from microprocessor 14. This latch also receives a separate input signal from microprocessor 16. An output of latch 22 is connected to the enable input to bit rate multiplier 28. Another output of latch 22 is connected to all of the clear inputs to bit rate multipliers 24, 26 and 28 and to an inverter 36 whose output is connected to the clear input to the programmable frequency divider 30. A
still another output of the latch 22 is connected to the strobe input to bit rate multiplier 28. Lastly, the remaining outputs of latch 22 are connected to inputs to the programmable frequency divider 30. The programmable frequency divider 30 produces a scaled frequency output signal indicative of the variable being measured.
Operationally, the signal conditioner 12 receives analog signals from a device, such as mass flowmeter as described in U.S. Patent No. 4,763,530. The flowmeter disclosed in the foregoing patent produces two phase shifted sine waves A and B (see Figure 1) wherein the degree of phase shift therebetween is indicative of the mass flow rate through the flowmeter. Thus, with such a flowmeter, the 1322~75 signals received by the signal conditioner 12 are typically the zero crossing points of the sine waves, and the signal conditioner produces digital signals indicative thereof.
These digital signals are transmitted to the microprocessor 14 which produces a 15 bit word proportional to the phase lag and representative of the mass flow rate through the flowmeter, following the steps illustrated in Figure 1. The 16th bit produced by the microprocessor 14 is a sign bit.
The microprocessor 14 also transmits an enable signal to latch 18 allowing the first 8 bits of the 15 bit word to be transmitted thereto over bus 32. It then disables latch 18 and transmits an enable signal to latch 20 allowing the remaining bits of the 15 bit word to be transmitted thereto over bus 32. Thus, the microprocessor 14 directs the transmission of a word having a bit length that exceeds the capacity of the bus and of each of the latches 18 and 20 by directing the first 8 bits of the word to latch 1 and then directing the remaining bits of the word to latch 20 all over an 8 bit bus (bus 32). Since each bit rate multiplier 24, 26, and 28 has an input/output relationship of rO - m x rj/26 where m has a word length of 6 bits and rj is the output frequency of the foregoing clock, three bit rate multipliers are required to accommodate the 15 bit word being transmitted from the latches 18 and 20. It should be noted that, depending upon the word length being transmitted, any number of bit rate multipliers may be interconnected in a cascade arrangement. Since one of the inputs to each of the bit rate multipliers 24, 26 and 28 is a clock input frequency ri, the output of OR gate 34 produces a signal proportional to the foregoing clock input frequency and the mass flow being sensed by the flowmeter.
Before any portion of the 15 bit word is transmitted by microprocessor 16 to the latches 18 and 20, the microprocessor 16 produces a separate 5 bit word which is used for scaling the output of the circuit 10. The operator can input various scaling information, e.g., upper and lower range values, etc., into the microprocessor 16 which produces a 5 bit word output signal representative of such and which is utilized as an input to the latch 22. As previously mentioned, one of the outputs of latch 22 is used to clear the bit rate multipliers 24, 26 and 28 and to clear the programmable frequency divider 30 via inverter 36. Another output is utilized to enable bit rate multiplier 28. The remaining outputs of latch 22 are connected to inputs to the programmable frequency divider 30 which produces the desired scaling factor (l/2n), wherein n is the rate output scale factor and can have a value of 2 through 31. The use of such a programmable frequency divider 30 permits scaling of the output of the circuit 10 and improves the resolution of the resulting output signal therefrom. With respect to the aforementioned flowmeter, the frequency of the output signal produced by the programmable frequency divider 30 is representative of the flow rate passing through the flowmeter and this output signal can be scaled, if desired, by the operator.
Certain modifications and improvements will occur to those skilled in the art upon reading the foregoing. It should be understood that all such modifications and improvements have been deleted herein for the sake of conciseness and readability, but are properly within the scope of the following claims.
Various types of instrumentation are available to produce a train of output pulses having a frequency which is proportional to the input signal applied thereto. Such instrumentation includes both analog and digital techniques~
A typical analog technique utilizes a voltage to frequency converter in single chip form or in discrete circuit form.
Such techniques require costly reference levels and variable resistors or switches for calibration purposes.
Alternatively, combinations of digital and analog techniques can be utilized but they have similar disadvantages with respect to reference levels and/or calibration. Complete microcomputer techniques require timer outputs which utilize a significant amount of execution time, particularly at higher frequencies. Other techniques include a combination of microcomputers, bit rate multipliers and digital counters to achieve high resolution over a broad frequency range.
Because of the foregoing, it has become desirable to develop a generator which produces an output signal representative of the frequency of the input signal that is, 1322~73 applied thereto, and which utilizes relatively inexpensive components to produce an output signal having a high degree of resolution over a broad frequency range.
The present invention solves the problems associated with the prior art and other problems by providing a frequency generator circuit that utilizes a minimum number of inexpensive components to produce an output signal representative of the frequency of the input signals applied thereto.
According to the present invention, a generator for producing a series of output pulses having a frequency that is proportional to the analog input signal applied thereto comprises means for converting the analog input signal into a digital signal having a predetermined word length, means for transmitting a portion of said word length to a first latch means and the remaining portion of said word length to a second latch means, bus means interconnecting said transmitting means and said first latch means and said second latch means, said bus means having a capacity which approximates said portion of said word length transmitted to said first latch means, and a plurality of rate multipliers connected to said first latch means and said second latch means producing an output signal representative of the analog input signal.
Further features of the invention will be apparent from the following description of an exemplary preferred embodiment thereof, with reference to the accompanying drawings, in which:
Fig. 1 shows stages in the processing of two mass flowmeter signals in a generator in accordance with the present invention.
Fig. 2A depicts circuit signal conditioning and microprocessing elements of the circuit.
1322~7~
Fig. 2B depicts latching and rate multiplying elements of the circuit which may be connected to the Fig~ 2A
circuit.
Fig. 2C depicts programmable frequency divider elements of the circuit which may be connected to the Fig. 2B
circuit.
Referring now to the drawings where the illustration is for the purpose of describing the preferred embodiment of the present invention and is not intended to limit the invention hereto, Figures 2A, 2~ and 2~ of the drawings together form a schematic diagram of the circuit 10 which embodies the present invention. The circuit 10 includes a signal conditioner 12, microprocessors 14 and 16 as shown in Figure 2A, electronic latches 18, 20 and 22, along with bit rate multipliers 24, 26 and 28, as shown in Figure 2B, and a programmable frequency divider 30 as shown in Figure 2C, all interconnected as shown.
The signal conditioner 12 receives one or more analog signals, amplifies same, filters the signals to reduce common mode noise and then digitizes same. The output of the signal conditioner 12 is connected to the input to microprocessor 14. It should be noted that even though two microprocessors (microprocessor 14 and 16) are shown, one microprocessor with sufficient capacity can be used in place thereof.
Microprocessor 14 produces a plurality of output signals which are transmitted to electronic latches 18, 20 and 22 via a bus 32. The output signals from the microprocessor 14 include an enable signal to allow the transmission of bits to latch 18, an enable signal to allow transmission of bits to latch 20, and a control signal on bus 32. The capacity of bus 32 is limited in that it is an 8 bit bus. Electronic latches 18, 20 and 22 are commercially available 8 bit latches, such as Part No. 74LS374 available from Texas Instruments, Inc. The outputs of latch 18 are connected to .
, :
1322~75 the inputs to bit rate multipliers 24 and 26, and the outputs of latch 20 are connected to the inputs to bit rate multipliers 26 and 28. The bit rate multipliers 24, 26 and 28 are commercially available devices, such as Part No. 7497 available from Texas Instruments, Inc. A clock having an output frequency rj is also connected as an input to each of the bit rate multipliers 24, 26 and 28 which are interconnected in a cascade arrangement. The outputs of bit rate multipliers 26 and 28 are connected to a commercially available OR gate 34, such as Part No. 74LS02 available from Texas Instruments, Inc. The output of OR gate 34 is connected to an input to the programmable frequency divider 30.
As previously mentioned, latch 22 receives input signals over bus 32 from microprocessor 14. This latch also receives a separate input signal from microprocessor 16. An output of latch 22 is connected to the enable input to bit rate multiplier 28. Another output of latch 22 is connected to all of the clear inputs to bit rate multipliers 24, 26 and 28 and to an inverter 36 whose output is connected to the clear input to the programmable frequency divider 30. A
still another output of the latch 22 is connected to the strobe input to bit rate multiplier 28. Lastly, the remaining outputs of latch 22 are connected to inputs to the programmable frequency divider 30. The programmable frequency divider 30 produces a scaled frequency output signal indicative of the variable being measured.
Operationally, the signal conditioner 12 receives analog signals from a device, such as mass flowmeter as described in U.S. Patent No. 4,763,530. The flowmeter disclosed in the foregoing patent produces two phase shifted sine waves A and B (see Figure 1) wherein the degree of phase shift therebetween is indicative of the mass flow rate through the flowmeter. Thus, with such a flowmeter, the 1322~75 signals received by the signal conditioner 12 are typically the zero crossing points of the sine waves, and the signal conditioner produces digital signals indicative thereof.
These digital signals are transmitted to the microprocessor 14 which produces a 15 bit word proportional to the phase lag and representative of the mass flow rate through the flowmeter, following the steps illustrated in Figure 1. The 16th bit produced by the microprocessor 14 is a sign bit.
The microprocessor 14 also transmits an enable signal to latch 18 allowing the first 8 bits of the 15 bit word to be transmitted thereto over bus 32. It then disables latch 18 and transmits an enable signal to latch 20 allowing the remaining bits of the 15 bit word to be transmitted thereto over bus 32. Thus, the microprocessor 14 directs the transmission of a word having a bit length that exceeds the capacity of the bus and of each of the latches 18 and 20 by directing the first 8 bits of the word to latch 1 and then directing the remaining bits of the word to latch 20 all over an 8 bit bus (bus 32). Since each bit rate multiplier 24, 26, and 28 has an input/output relationship of rO - m x rj/26 where m has a word length of 6 bits and rj is the output frequency of the foregoing clock, three bit rate multipliers are required to accommodate the 15 bit word being transmitted from the latches 18 and 20. It should be noted that, depending upon the word length being transmitted, any number of bit rate multipliers may be interconnected in a cascade arrangement. Since one of the inputs to each of the bit rate multipliers 24, 26 and 28 is a clock input frequency ri, the output of OR gate 34 produces a signal proportional to the foregoing clock input frequency and the mass flow being sensed by the flowmeter.
Before any portion of the 15 bit word is transmitted by microprocessor 16 to the latches 18 and 20, the microprocessor 16 produces a separate 5 bit word which is used for scaling the output of the circuit 10. The operator can input various scaling information, e.g., upper and lower range values, etc., into the microprocessor 16 which produces a 5 bit word output signal representative of such and which is utilized as an input to the latch 22. As previously mentioned, one of the outputs of latch 22 is used to clear the bit rate multipliers 24, 26 and 28 and to clear the programmable frequency divider 30 via inverter 36. Another output is utilized to enable bit rate multiplier 28. The remaining outputs of latch 22 are connected to inputs to the programmable frequency divider 30 which produces the desired scaling factor (l/2n), wherein n is the rate output scale factor and can have a value of 2 through 31. The use of such a programmable frequency divider 30 permits scaling of the output of the circuit 10 and improves the resolution of the resulting output signal therefrom. With respect to the aforementioned flowmeter, the frequency of the output signal produced by the programmable frequency divider 30 is representative of the flow rate passing through the flowmeter and this output signal can be scaled, if desired, by the operator.
Certain modifications and improvements will occur to those skilled in the art upon reading the foregoing. It should be understood that all such modifications and improvements have been deleted herein for the sake of conciseness and readability, but are properly within the scope of the following claims.
Claims (4)
1. A frequency generator for producing a series of output pulses having a frequency that is proportional to an analog input signal applied thereto, comprising:
means for converting the analog input signal into a digital signal having a predetermined word length and scaling factor therefor;
means for transmitting a portion of said word length to a first latch, the remaining portion of said word length to a second latch and said scaling factor for the word length to a third latch;
a bus interconnecting said transmitting means, said first latch, said second latch and said third latch, said bus having a capacity which approximates said portion of said word length transmitted to said first latch;
a plurality of bit rate multipliers interconnected in a cascade arrangement to said first latch, said second latch and said third latch for producing an output signal representative of the analog input signal, said third latch having an output connected to each of said bit rate multipliers to clear same upon receipt of said scaling factor from said transmitting means; and a programmable frequency divider, connected to said plurality of bit rate multipliers for receiving said output signal representative of the analog input signal, and connected to said third latch to permit scaling of the output signal to improve its resolution.
means for converting the analog input signal into a digital signal having a predetermined word length and scaling factor therefor;
means for transmitting a portion of said word length to a first latch, the remaining portion of said word length to a second latch and said scaling factor for the word length to a third latch;
a bus interconnecting said transmitting means, said first latch, said second latch and said third latch, said bus having a capacity which approximates said portion of said word length transmitted to said first latch;
a plurality of bit rate multipliers interconnected in a cascade arrangement to said first latch, said second latch and said third latch for producing an output signal representative of the analog input signal, said third latch having an output connected to each of said bit rate multipliers to clear same upon receipt of said scaling factor from said transmitting means; and a programmable frequency divider, connected to said plurality of bit rate multipliers for receiving said output signal representative of the analog input signal, and connected to said third latch to permit scaling of the output signal to improve its resolution.
2. The frequency generator as defined in claim 1, wherein said third latch means is also connected to said programmable frequency divider via an inverter to clear same.
3. The frequency generator as defined in claim 1, wherein the capacity of said bus is identical to the capacity of said first latch, said second latch and said third latch.
4. The frequency generator as defined in claim 1, wherein the capacity of said first latch and said second latch approximates the capacity of each of said bit rate multipliers in said plurality of bit rate multipliers.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US25283488A | 1988-09-30 | 1988-09-30 | |
| US07/252,834 | 1988-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1322575C true CA1322575C (en) | 1993-09-28 |
Family
ID=22957744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000609458A Expired - Fee Related CA1322575C (en) | 1988-09-30 | 1989-08-25 | Frequency output generator |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH02149019A (en) |
| KR (1) | KR900005682A (en) |
| AU (1) | AU607635B2 (en) |
| CA (1) | CA1322575C (en) |
| IN (1) | IN171476B (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5143664A (en) * | 1974-10-11 | 1976-04-14 | Mitsubishi Chem Ind | Anarogu dejitaruhenkansochi |
| AU1647576A (en) * | 1976-08-02 | 1978-02-09 | Johnson & Johnson | Electronic thermometer |
| JPS62110323A (en) * | 1985-11-08 | 1987-05-21 | Nec Ic Microcomput Syst Ltd | Frequency-digital conversion circuit |
| EP0232451B1 (en) * | 1986-02-10 | 1990-03-14 | LGZ LANDIS & GYR ZUG AG | Method and device for the conversion of an electrical signal into a proportional frequency |
-
1989
- 1989-03-13 IN IN205/CAL/89A patent/IN171476B/en unknown
- 1989-05-19 KR KR1019890006722A patent/KR900005682A/en not_active Application Discontinuation
- 1989-08-25 CA CA000609458A patent/CA1322575C/en not_active Expired - Fee Related
- 1989-09-18 AU AU41532/89A patent/AU607635B2/en not_active Ceased
- 1989-09-29 JP JP1252469A patent/JPH02149019A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| AU4153289A (en) | 1990-04-05 |
| KR900005682A (en) | 1990-04-14 |
| JPH02149019A (en) | 1990-06-07 |
| AU607635B2 (en) | 1991-03-07 |
| IN171476B (en) | 1992-10-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0200896A2 (en) | Digital flow meter circuit and method for measuring flow | |
| US4420809A (en) | Frequency determining apparatus | |
| EP0177557B1 (en) | Counting apparatus and method for frequency sampling | |
| GB1600585A (en) | Gas turbine engine trim test set apparatus | |
| CA1322575C (en) | Frequency output generator | |
| EP0204310A2 (en) | Method of measuring the frequency of a wave | |
| US4809558A (en) | Method and apparatus for use with vortex flowmeters | |
| US5644288A (en) | Vehicle speed detecting apparatus | |
| McCarthy | A digital instantaneous frequency meter | |
| US4537081A (en) | Flow metering circuit and method | |
| EP0236108B1 (en) | Tacho signal processing | |
| US4536743A (en) | Method of converting a digital signal into an analog signal and a digital-to-analog converter therefor | |
| Prokin | Dynamic response of a frequency measuring system | |
| US3991303A (en) | Voltage pulse multiplying circuit | |
| US4392749A (en) | Instrument for determining coincidence and elapse time between independent sources of random sequential events | |
| EP0122984A1 (en) | Time measuring circuit | |
| SU997228A1 (en) | Digital multiplier of periodic pulse repetition frequency | |
| SU1272271A1 (en) | Digital spectrum analyzer | |
| EP0030053A1 (en) | Aircraft low range radio altimeter simulator | |
| SU1053285A1 (en) | A.c.-voltage-to-code converter | |
| SU1267286A1 (en) | Digital phase meter | |
| SU1553917A1 (en) | Method of measuring phase shift | |
| SU943599A1 (en) | Phase shift to code converter | |
| SU1173339A1 (en) | Digital integrating phasemeter | |
| SU1478333A1 (en) | Frequency transducer characteristic linearizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |