AU607635B2

AU607635B2 - Improved frequency output generator

Info

Publication number: AU607635B2
Application number: AU41532/89A
Authority: AU
Inventors: Nelson R. Blank; Gary L. Zelonis
Original assignee: Babcock and Wilcox Co
Current assignee: International Control Automation Finance SA Luxembourg
Priority date: 1988-09-30
Filing date: 1989-09-18
Publication date: 1991-03-07
Anticipated expiration: 2009-09-18
Also published as: AU4153289A; KR900005682A; JPH02149019A; IN171476B; CA1322575C

Description

liiAjzAxMAnismdoNWIIHOi :9V 'id OL .2 IIIII~1111'25 -11111____1.4 11 777111 1 Ir ~c~7~35 COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 COMPLETE SPECIFICATION FOR OFFICE USE Form Short Title: Int. Cl: Application Number: Lodged: 0 0 C 0, 0 0 6 Complete Specification-Lodged: Accepted: Lapsed: Published: Priority: Related Art: 46.0 a 00 4 00 TO BE COMPLETED BY APPLICANT Name of Applicant: Address of Applicant: 4 00 0 44 4 too 4 4 Actual Inventor: Address for Service: THE BABCOCK WILCOX COMPANY 1010 Common Street, New Orleans, Louisanna 70160, UNITED STATES OF AMERICA Nelson R. BLANK and Gary L. ZELONIS URIFFITH HACK CO.

71 YORK STREET SYDNEY NSW 2000

AUSTRALIA

Complete Specification for the invention entitled: IMPROVED.CREQUENCY OUTPUT GENERATOR The following statement is a full description of this invention, including the best method of performing it known to me/us- -I IMPROVED FREQUENCY OUTPUT GENERATOR TECHNICAL FIELD The present invention relates, in general, to a frequency generator and, more particularly, to a frequency generator that produces a series of output pulses that have a frequency proportional to the input frequency applied thereto.

BACKGROUND ART Various types of instrumentation are available to produce a train of outpat pulses having a frequency which is proportional to the input signal applied thereto. Such S instrumentation includes both analog and digital S* 'techniques. A typical analog technique utilizes a voltage So** to frequency converter in single chip form or in discrete circuit form. Such techniques require costly reference 480064 S levels and variable resistors or switches for calibration purposes. Alternatively, combinations of digital and analog techniques can be utilized but they have similar disadvantages with reseect to reference levels and/or calibration. Complete microcomputer techniques require I o a* timer outputs which utilize a significant amount of e o executinn time, narticilarv at higher frequencies.

£0 Other techniques include a combination of microcomputers, bit rate multipliers and digital counters to achieve high o 25 resolution over a broad frequency range.

Because of the foregoing, it has become desirable to develop a generator which produces an output signal St representative of the frequency of the input signal that is 1 ec applied thereto, and which utilizes relatively inexpensive SC.C 1 -2components to produce an output signal having a high degree of resolution over a broad frequency range.

SUMMARY OF THE INVENTION The present invention solves the problems associated with the prior art and other problems by providing a frequency generator circuit that utilizes a minimum number, of inexpensive components to produce an output signal representative of the frequency of the input signals applied thereto. The circuit includes a microprocessor which converts the input signal being monitored into a Sbit word and directs same over an 8 bit bus to two 8 bit 9 latches, the first latch receiving the first 8 bits of the 9o 15 bit word and the second latch receiving the remaining 0 15 bits of the 15 bit word. The outputs of these latches are used an inputs to a plurality of bit rate multipliers interconnected in a cascade arrangement to produce an oucput signal representative of the input signal. This output signal is applied to an input to a programmable frequency divider which is responsive to operator applied inputs in order to scale the resulting output therefrom. The resulting output of the programmable frequency divider is representative of the frequency of the input signal applied to the circuit and is scaled in accordance with the desires of the operator.

BRIEF DESCRIPTICN OF THE ORAWING S" The single figure of the drawing is an electrical schematic of the preferred embodiment of the present invention.

l* 1 I -3- DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawing where the illustration is for the purpose of describing the preferred embodiment of the present invention and is not intended to limit the invention hereto, the single figure of the drawing is a schematic diagram of the circuit 10 which embodies the present invention. The circuit 10 includes a signal conditioner 12, microprocessors 14 and 16, electronic' latches 18, 20 and 22, bit rate multipliers 24, 26'and 28, and a programmable frequency divider 30 all interconnected as shown.

The signal conditioner 12 receives one or more analog signals, amplifies same, filters the signals to reduce 15 common mode noise and then digitizes same. The output of a the signal conditioner 12 is connected to the input to @0 microprocessor 14. It should be noted that even though two microprocessors (microprocessor 14 and 16) are shown, one Stt, microprocessor with sufficient capacity can be used in place sEE 20 thereof. Microprocessor 14 produces a plurality of output signals which are transmitted to electronic latches 18, and 22 via a bus 32. The output signals from the microprocessor 14 include an enable signal to allow the transmission of bits to latch 18, an enablesignal to allow 25 transmission of bits to latch 20, and a control signal on bus 32.

The capacity of bus 32 is limited in cnac it is an 8 bit o bus. Electronic latches 18, 20 and 22 are commercially available 8 bit latches, such as Part No. 74LS374 available from Texas Instruments, Inc. The outputs of latch 18 are connected to zhe inputs to bit rate multipliers 24 and 26, and the outputs of latch 20 are connected to the inputs to atTCt bit rate multipliers 26 and 28. The bit rate Vt C iull U rar~sr t 00 4 00 0 0 00 o00 0 0 t a e« multipliers 24, 26 and 28 are -commercially available devices, such as Part No. 7497 available from Texas Instruments, Inc. A clock having an output frequency r. is also connected as an input to each of the bit rate multipliers 24, 26 and 28 which are interconnected in a cascade arrangement. The outputs of bit rate multipliers 26 and 28 are connected to a commercially available OR gate 34, such as Part No. 74LS02 available from Texas Instruments, Inc. The output *of OR gate 34 is connected to an input to the programmable frequency divider As previously mentioned, latch 22 receives input signals over bus 32 from microprocessor 14. This latch also receives a separate input signal from microprocessor 16. An 15 output of latch 22 is connected to the enable input to bit rate multiplier 28. Another output of latch 22 is connected to all of the clear inputs to bit rate multipliers 24, 26 and 28 and to an inverter 36 whose output is connected to the clear input to the programmable frequency divider 30. A still another output of the latch 22 is connected to the strobe input to bit rate multiplier 28. Lastly, the remaining outputs of latch 22 are connected to inputs to the programmable frequency divider 30. The programmable frequency divider 30 produces a scaled frequency output signal indicative of the variable being measured.

Operationally, the signal conditioner 12 receives analog signals from a device, such as mass flowmeter as described in U.S. Patent No. 4,763,530. The flowmeter disclosed in the foregoing patent produces two phase shifted 30 sine waves wherein the degree of phase shift therebetween is indicative of the mass flow rate through the flowmeter.

Thus, with such a flowmeter, the signals received by the st O 00 0 O

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a ac t ~rr~r_ ;~I signal conditioner 12 are typically the zero crossing points of the sine waves, and the signal conditioner produces digital signals indicative thereof. These digital signals are transmitted to the microprocessor 14 which produces a bit word representative of the mass flow rate through the flowmeter. The 16th bit produced by the microprocessor 14 is a sign bit. The microprocessor 14 also transmits an enable signal to latch 18 allowing the first 8 bits of the 15 bit word to be transmitted thereto over bus .32. It then disables. latch 18 and transmits an enable signal to' latch allowing the remaining bits of the 15 bit word to be U transmitted thereto over bus 32. Thus, the microprocessor

S

1 14 directs the transmission of a word having a bit length 15 that exceeds the capacity of the bus and of each of the o, latches 18 .and 20 by directing the first 8 bits of the word to latch 1 and then directing the remaining bits of the word to latch 20 all over an 8 bit bus (bus 32). Since each bit rate multiplier 24, 26, and 28 has an input/output relationship of r m x r/ 2 where m has a word length of 6 bits and r. is the output frequency of the foregoing clock, three bit rate multipliers are required to accommodate the 15 bit word being ti 6 25 transmitted from the latches 18 and 20. It should be noted that, depending upon the word length being transmitted, any number of bit rate multipliers may be interconnected in a S, cascade arrangement. Since one of the inputs to each of the bit rate multipliers 24, 26 and 28 is a clock input St" 30 frequency r the output of OR gate 34 produces a signal proportional to the foregoing clock input frequency and the mass flow being sensed by the flowmeter.

.*j -6- Before any portion of the 15 bit word is transmitted by microprocessor 16 to the latches 18 and 20, the microprocessor 16 produces a separate 5 bit word which is used for scaling the output of the circuit 10. The operator can input various scaling information, upper and lower range values, etc., into the microprocessor 16 which produces a 5 bit word output signal representative of such and which is utilized as an input to the latch 22. As previously mentioned, one of the outputs of latch 22 is used Sto clear the bit rate multipliers 24, 26 and 28 and to clear S, the programmable frequency divider 30 via inverter 36.

Another output is utilized to enable latch 22. The s remaining outputs of latch 22 are connected to inputs to o 15 the programmable frequency divider 30 which produces the ,O desired scaling factor 1 2 wherein n is the rate output S 'a scale factor and can have a value of 2 through 31,3 or 4. The use of such a programmable frequency divider 30 permits scaling of the output of the circuit 10 and improves the resolution of the resulting output signal therefrom. With respect to the aforementioned flowmeter, the frequency of S sCo the output signal produced by the programmable frequency divider 30 is representative of the flow rate passing through the flowmeter and this output signal can be scaled, if desired, by the operator.

Certain modifications and improvements will occur to those skilled in the art upon reading the foregoing. It t 6 should be understood that all such modifications and *i improvements have been deleted herein for the sake of conciseness and readability, but are properly within the scope of the following claims.

Claims

1. A generator for producing a series of output pulses having a frequency that is proportional to the analog input signal applied thereto comprising means for converting the analog input signal into a digital, signal having a, predetermined word length, means for transmitting a portion of said word length to a first latch means and the remaining portion of said word length to a. second latch means, bus means interconnecting said transmitting means and said first latch means and said second latch means, said bus means having a capacity which approximates said portion of said word length transmitted to said first latch means, and a plurality of rate multipliers connected to said first latch means and said second latch means producing an output signal representative of the analog input signal. CO I I Ir ct I C I C 1 c Cr co Io i

2. The generator 20 plurality of rate cascade arrangement. as defined in claim 1 wherein said multipliers are interconnected in a

3. The generator as defined in claim 1 further including third latch means permitting the introduction of operator input data therein and a programmable frequency divider permitting the scaling of the output of said plurality of rate multipliers, said third latch means being connected to said plurality of rate multipliers and to said programmable frequency divider. i i

4. The generator as defined in claim 3 wherein the output of said plurality of rate multipliers is connected to said programmable frequency divider.

5. The generator as defined in claim 1 wherein the capacity of said bus means approximates the capacity of said first latch means and said second latch means.

6. The generator. as defined in claim 1 wherein capacity of said first latch means and said second latch means approximates the capacity of each of said rate multipliers in said plurality of rate multipliers. o 1 e a~ *o *e a 01 0 feC 0VF

7. A generator for producing a series of outputpulses frequency that is proportional to an analog input signal thereto, substantically as herein before described with to the accompanying drawings. having a applied reference go C C 6 409 4 4 06 0 DATED this 15th day of September 1989 The Babcock Wilcox Company By their Patent Attorney GRIFFITH HACK &f CO.