CA1299289C - Integrated circuit with memory self-test - Google Patents
Integrated circuit with memory self-testInfo
- Publication number
- CA1299289C CA1299289C CA000548276A CA548276A CA1299289C CA 1299289 C CA1299289 C CA 1299289C CA 000548276 A CA000548276 A CA 000548276A CA 548276 A CA548276 A CA 548276A CA 1299289 C CA1299289 C CA 1299289C
- Authority
- CA
- Canada
- Prior art keywords
- test
- word
- integrated circuit
- memory
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 88
- 230000015654 memory Effects 0.000 title claims abstract description 86
- 230000003068 static effect Effects 0.000 claims description 8
- 238000004458 analytical method Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 15
- 230000002250 progressing effect Effects 0.000 abstract 1
- 238000013461 design Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 4
- 238000011960 computer-aided design Methods 0.000 description 3
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 2
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000010420 art technique Methods 0.000 description 2
- 238000013144 data compression Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 101150110971 CIN7 gene Proteins 0.000 description 1
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 1
- 101150110298 INV1 gene Proteins 0.000 description 1
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US914,411 | 1986-10-02 | ||
US06/914,411 US4872168A (en) | 1986-10-02 | 1986-10-02 | Integrated circuit with memory self-test |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1299289C true CA1299289C (en) | 1992-04-21 |
Family
ID=25434325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000548276A Expired - Fee Related CA1299289C (en) | 1986-10-02 | 1987-09-30 | Integrated circuit with memory self-test |
Country Status (2)
Country | Link |
---|---|
KR (1) | KR900008638B1 (ko) |
CA (1) | CA1299289C (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002100738A (ja) * | 2000-09-25 | 2002-04-05 | Toshiba Corp | 半導体集積回路及びテスト容易化回路の自動挿入方法 |
-
1987
- 1987-09-29 KR KR1019870010810A patent/KR900008638B1/ko not_active IP Right Cessation
- 1987-09-30 CA CA000548276A patent/CA1299289C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR880005622A (ko) | 1988-06-29 |
KR900008638B1 (ko) | 1990-11-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MKLA | Lapsed |