CA1293544C

CA1293544C - Plated plastic castellated interconnect for electrical components

Info

Publication number: CA1293544C
Application number: CA000570654A
Authority: CA
Inventors: Timothy P. Patterson; Carl E. Hoge; Joseph Baia
Original assignee: Western Digital Corp
Current assignee: Western Digital Corp
Priority date: 1987-07-01
Filing date: 1988-06-28
Publication date: 1991-12-24
Anticipated expiration: 2008-12-24
Also published as: AU2073088A; WO1989000346A1

Abstract

PLATED PLASTIC CASTELLATED INTERCONNECT
FOR ELECTRICAL COMPONENTS
ABSTRACT OF THE DISCLOSURE
a plated plastic castellated interconnect comprises a substrate made from a molded polymeric material and having top and bottom surfaces with a plurality of separate mutually spaced apart castellations integrally molded to the substrate and projecting from the bottom surface of the substrate. A plurality of separate spaced apart recessed regions may be molded in an edge of the substrate and aligned with the castellations. A plurality of metal conductors are plated to the substrate as separate conductive circuit traces, so that each circuit trace extends continuously from the top surface, along the surface of a corresponding recess and to a common plane on a respective caetellation at the bottom of the substrate.
The plated metal castellations are arranged for soldering or gluing to contacts on a printed circuit board for electrical connection to an electrical component such as an IC chip connected to the circuit traces on the substrate. The plated plastic castellations on one component provide high lead pitch densities, complex configurations, and compliancy of electrical connections to a second electrical component, as well as other advantages.

Description

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_165:19231/wGM 1-: 10 ! PLATED PLA~IC CAS~ELLATED_~NTERCONNECT
~: FOR ELECTRICAL_COMPONENTS
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This is a continuation-in-part of our application Serial No. 069,425, iE~led July 1, 1987, wh~ch i~
incorporated herein by reference.
,, ~ELD OF THE INVENTION
: This invention relates to a plated plastic : ~ 20 castellated interconnect used as an interface for in*erconnecting electrical components.

BACKGROUND OF THE INVENTION
` There are a variety of electrical interconnect techniques used for providing c:onnections between electrical components. Interconnects vary widely in their use and function as do the variety cf electrica.l components be~ng connected. Ele~trical c:omponents can be interconnected by solder~ ng, wire bonding, Tape Automated Bondinq (TAB), or metal strips, for example. Plated ceramic i~terconnects also can be used ~or foYming ~, interconnects. These and other interconnect techniques can .~ ~ be used to interconnect a variety of integra~ed circuit ~IC) co~ponents, and one example ~ncludes th~ techniques used for packaging of integraked circuit chlp~ and surface .
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1 ~ounting them on printed circuit boards (PCB'~). The following background description xelates to the prior ~rt of ~orming electrical interconnect~ u~ed ~n the packaging of int~grated circuit chips ~nd the mounting of IC
packages on PCB's. This descript~on i~ ~n ~xample only, . ~nd iB intended to ~imply provide a better appreciation of the i~prove~ents resulting from the present invention as ; applied to 6urface connection o~ electr~cal ao~ponent~ in gener~l. Other applications of the invention will be more fully understood when considering.the various ambodiments o~ the invention described in greater detail at a later point.
Perhaps the most widely used technigue for packaging integrated c~rcuit chips and mounting them on PCB~
.15 that of encapsulating ~ c~ip in an epoxy or cexamic package. In th~s technigue, the chip i fir t ~ounted at ~ the center of a plurality o~ radially -extending leads.
:: Then, ~ine wires are ~oldered o~to wire bonding pad on the chip. The opposite end Qr each of ~hese wires i8 ~20 601dered to the inner end o~ one of the radial leads.
: ~his process~ ~or electrically connecting the chip ~o the leads with f ine wires is called "wire bonding. Il The chip and the inner end o~ each radial lead are then encapsulated in epoxy or ceramic, with ~he outermost end of each lead being left exposed. ~he exposed ends of the leads are bent downward 50 that they ~ay be plugged ~nto an integrated circuit chip 60cket mounted on the printed :circuit board. In thi6 way, the chip i8 electrically and ~echanically coupled to the printed circuit bo~rd. This method of mounting and packaging integrated c~rcuit~ has ~isadvantages, which include the integrated circuit chips be~ng occasionally damaged when wires are soldered to the wire bonding pads on the chip sur~ace.
In one widely used technique ~or ~ur~ace mounting IC
package~ to pr~nted circult boards, a metal lleadframe is 33~

1 used to make el~ctrical connections between an integrated clrcuit and ~ PC~. ~etal leadframe6 are 6tamped or etched rom a thin, ~lat etrip of matal to ~orm outwardly extending pin-like member~ or leads. Generally, the metal leadframe i~ embedded ln a ~olded plastic body or ls otherwise a~fixed in a ceramic or plastic body with the leads ~xtending out ~rom the side~ between the top and bottom surfaces of the body. The leads are typically bent downward Along ~he ~ides of the body to what i8 commonly referred to a6 a J-~hape, or a wing shape, or straight down to what has been referred to..~s a butt end, for allowing the packages to be ~urface mounted on the PCB.
Surface mounting is an arrangement in which the leads are 601dered to the surface of the PCB, ~s opposed to an arrangement in which the leads extend through plated thru-holes in t~e PCB be~ore soldering.
In one prior art IC package having J-6haped leads, ~, the body has a castellated edge which extends downwardly ; around tha bottom Bide 0~ the ~odyO Separate leads are bent ~n an S-~hape around the raised castellation~. ~his provides a spacing between the bottom of the IC package and the PCB. U.S. Patent 4,012,766 to Phillips, et al.
discloses a ~emiconductor package and a method of manufacturing of the ~eneral type which ~ncludes J-shaped leads.
Use of a lead~rame has disadvantage~. For example, an input/outputs (I/O's) have increased in nu~ber, the ; spacing between leads has decreased ~o as to prevent the Ir packages ~rom becominy excessi~Ply large. As a result, the leadfxames have been forced to become thinner. For ~hese reasons, normal tes~ing, shipping and handling procedures have become very difficult because o~ the need to avoid bending the external leads, Any bend~ng of the metal leads can cause a lateral misalignment wh.Lch can pxevent the bent leads ~rom matc~ing up w$th correspondin~

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~;1 conta~ts on a PCB. Bending of the leads can also cause a non-planar ~i~alignment of the leadls at the bottom of the :IC package, and, as a result, ~ome of the leads ~ay not be ~onnected to a corresponding contact on the PCB.
Another arrangement for surface ~ounting of IC
~ . package6 comprises ~ printed w$ring ~oard in the form of a thin plastic ba~e on whlch ~etalized le~ds ~re formed in a patt~rn. ~he ~etalized leads are typically formed by laminating copper to the board with an epoxy resin and -10 etching away to form the metaliæed leads. ~oles are drilled in. "picture frame" arrays through the thin dimension of the base, from the top to the bottom, and, subsequently, the holes are plated with metal such as : copper or gold. The printed metal leads on the top i~e of the base are then plated with gold or the like to form pattern o~ printed leads which fan out from rectangular central portion o~ the carrier to the plated thru-holes. Small metalized leads are A150 ~ormed on the:
bottom Gide of the base below the plated thru-holes. An ; 20 ~C chip is then mounted w$thin ~a ca~ity in the central portion of the base, and fine condu~tive wires are bonded ~ be~ween the chip and the ends o~ the metal leads. The top ; of the base is then covered with a plast1~ lid, or potted with epoxy resin. The resulting assembly is placed on a PC board, with the bottom side of the base resting against the top face of ~he board. Flow soldering techniques are used to form electrical connections between each e ched metal lead on the bot~om 6ide of the base and corre~ponding contact on the PCB.
The plastic IC package w~th the etched met21 traces ls useful because there are no self-supportiny metal wires or leads which can be bent, inasmuch as the etched me~al leads are affixed ~irmly to the surface of the base and, ~here~ore, do ~ot move. However, this approach has disad-~antages because the etched metal leads on the bottom o~

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1 the ba6e can result in electr~cal ~hort~ fro~ trace to : ~race on d osely spaced traces when ~older~ng the base to a PCB. ThiC, therefore, limits the pltch of the ~tal ~ traces of the package, i.e., its capability o~ being : 5 expanded into providing much finer p~tches and resulting higher I/O'~. The use of printed w~ring board technigues, including ~se of the thick conductive met~l lead~, also limits the board'~ applicability to ~ner lead pitches.
Cera~ic leadles~ IC packages have also been used in the past ~or ~ounting integrated circuits to a PCB. One prior art cerami~ leadless IC paok~ge 1~ ~isclosed in U.S.
Patent 4,525,597 to Abe, in which circuit pattern~ are printed on a ceramic green 6heet with a metali~ing paste.
An i~sulating layer is thn placed over the ~etalized pattern on the top ~urface. The gree~ heet i8 then hot pressed to maXe the t~p sur~ace ~oncave and the bottom '. 6ur~ace convax around a peripheral rim of the ceramic `¦ body. ~he green sheet i5 then f~red. A~ter ~iring, ~he ~: ceramic is plated with a con~uctive metal at posi~ions corresponding to the exposed ~etal circult patterns remaining on the ceramic. The ~tep of hot pxessing t~e ceramic body form6 a 6eries of spaced apart depressions around the periphery in the t~p ~urface, with corresponding stand-off pads on the botto~ ~urfacé of the 2S ceramic body.
: This ceramic IC carrier ha~ ~everal disadvantages.
It is limited in lts ability to provide fine~lead pitches, because the steps involved in forming a cerami~ carrier by casting in green sheets, applying a ~etal pasts, hot pressing, ~ir~n~, and subsequent metal plating techniques limit resolution. These technigues there~ore are not adaptable to producing an IC carrier with the geometries necessary t~ produca a fi~e lead pltch. In addition, ~urface ~ounted ceramic IC packages can be unreliable because thermal transiente can develop ehear ~orces at the ~Z9~

1 ~older ~oints and produce ~atigue and result~ng poor ~lectrical connections~ As lead pitches become fi~er, these prsblems with ceramic IC packages beco~s magnified~
~he ~ore reliable cerami~ IC pacXages to date haue the : 5 ~el~-supporting metal leads whioh have the disadvantages '- o~ the leadframe approach described above.
Thus, tha prior art has provided a variety o~
elec~ronlc interconnect technlgues for a wide variety of electrical components, ~ncluding the previously described techni~ues for ~urface ~ounting cf IC packages. Al} of these interconrlect technigues have disadvantages or limitations which ~re overcome by the present in~ention.

SUMMARY OF THE INVENTIOM
15T~i~ invention provides a plated plastic astel}ated ; interconnect *or us~ in the ~ur~ace ~onnection of electrical components. The interconnect includes a ~irst electrical component comprislng a substrate made ~rom a molded polymeric ~aterial. ~he molded plastic substrate ha~ first and ~econd surface~ ~ubstantially parallel to each other, and a plurali~y o~ ~eparate mutually ~paced apart molded projections or castellations extending ~rom the second ~urface to a ~ubstantially common plane spaced from the 6econd surface of the ~ubstrate. Multiple eleGtrically separated metal ço~ductoxs are plated to the ~ubstrate. ~he plated conductors extend continuQusly from the ~irst ~ur~ace, around or through the substrate, to the common plane on correspondlng castellations ~n the second ~urface o~ the ~ubstrate. The plated castellations are adapted ~or connection ~mechanical adhesion and ~lectrica~
correction) to corresponding electrical contacts, leads, terminals, or other conductor~ on a ~econd electrical component to which the ~ir~t component is ~ur~ace mounted.
The plated plastic castellations are macle ~rom polymeric materials that result in castellations w~llch are 1~3S ~

1 indivldu~lly compliant, at least on a microscopic level.
~he co~pl~ancy of the indi~idual castellation6 al~ows a certain level of flexibility in the indivldual connections to a second component ~uch as a PCB or other ~upport base.
;5 Thi6 provides more effectlve mechanical adhesion and electrical connections than with other prior art 6urface mount techniques such a~ 601der ~oints or ~urface mounted ceram~c IC carriers. ..
'rhe p}ated plastic caskellated interconnect has other advantages when compared w~th the prior ~rt o~ 6ur~ace mounting ~C packages. ~he molded plastic.~ubstrate in combination with the plated ~etal conductors on ~he castellations allows for much finer lead pltches and re~ulting higher lead counts than the metal lead~rame, ~:15 print~d wirlng board, or ceramic IC carrier techniques.
The invention al60 eliminates the sdditional expe.n~e of using ~etal leadframe techniques, while providing other advantages such as allowing ~or thorough cleaning of fluxes and contaminants ~rom between an IC package and a PCB.
The plastic ~ubstrate can be molded in a variety o~
geometric configurations for ~ncreasing lead pitch ~densities. These techniques include forming~multiple rows :o~ ~paced projections along the bottom of the ~ubstrate, adjacent alternating recessed area~ in ~ultiple rows :~paced apart along the edges of the substrate. The~e and other 6imilar arrangements can increase ~ubstantially the lead pitch densities provided ~y the molded p~astic module.
The higher lead pitch densities achievecl by the plated plastic interconnect o~ this invention are n~t aohievable by ceramic IC carriers, espec:la:lly when compared with the complex confi~urations into which the module of thi~ invention can be molded ~o ~acilitate 6uch higher lead counts. In addition, the molde~ plastic ` \

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1 substrate does not undergo the 6ame ~iring ~hrinkage : problems ~haracteristic of ceramic IC ~arriers during fabrication since the ~old itself dictates the package dimen~ions and toler~ncas. ~here~ore, much higher 5 preci8ion i~ achievable Xor attaining ~ine pitches.
'- These and other aspects of the invention will be more fully understood by referring to the following detailed description and the accompanying drawings.

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1 BRIEF DESCRIPTION OF ~H~ DRAWINGS
FIG. ~ i~ a frasmentary ~emi- ohematia ~ide elevation : ~iew il}ustrating a plated pla tic ~astellated interconnect according to princ~ple~ of this invention:
5FIG. 2 is a perspective v1ew illustrating use of the -~ plated plastic castellated interconnect in an lntegrated circuit chip tIC~ carrier;
FIG. 3 15 a top plan view illustrating metal plated conductors on a top surrace of a 6ubstrate ba6e por~ion of the IC carr~er;
FIG. 4 is a ~ide elevation viëw, partly ~n cros~-~ectlon, taken along line 4-4 of FIG. 2:
FIG. 5 is a bottom plan view taken on line 5-5 of FIG. 4,o - 15FIG. 6 is a semi-6chema~ic partly cross-sectional YieW illustratiny use of the plated pl~ætic castellated interconnect tn an alternative techn~que for ~ounting an inteqrated circuit chip to the IC carrier;
FIG. 7 is a top plan view ~llustrating B molded sub-2~ ~trate base portion o~ an IC çarrier during a preliminary tep ~n a process for manufacturing the I~ carriers : FXG. 8 is a bottom plan view of the opposi~e side of the 6ubstrate shown in ~IG. 7;
FIG. 9 is an enlarged fragmentary ~ide elevation view illustrating a portion o~ the IC carrier ~ounted to a ` printed ~ircuit board;
FIG. lO is a fragmentary top plan view ~llu~trating an alternativ embodiment of the invention i~ which lead pitch density of an IC carrier is increased;
30FIG. ll is a fragmentary top plan view illustrating a portion of the alternative IC carrier shown in FIG. l0;
FIG. 12 is a ~ragmentary per~pective view illustrating a bottom portion o~ tbe alter:native IC
carrier;

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1 FIG. 13 is a ~ragmentary top plan ~iew illustrating u~e o~ th~ plated plastic castellated ~nterconnect in an alternative IC carrier wlth plated thru-holes ~n contact with ~astellations on the bottom of the carrier;
FIG. 14 ls a cros6-sectional view o~ the embodiment ~ of FIGo 13;
FIG. 15 i~ a ~ragmentary cro6~-~ectional view illustrating use of the plated plastlc castellated lnterconnect ior the sur$ace connection of an electrical socket to a PCB aocording to principles o~ thi~ invention;
FIG. 1~ is a fragmentary cros~-sect$onal ~iew illustrating an alternate embodiment o~ a plated plastlc castellated interconnect in which an electrical ~ocket is mounted to a PCB; and ;~ 15 FIG. 17 i6 a fragmentary cross-sectional view : $11ustrating a further u~e of the in~ention for suur~cae ;~ mounting a pin grid to a PCB.

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1 DETAIhED DESCRIPTION
This invention provldes a plated plast~c castellated interconnec~ used ~or the 6ur~ace connection ~f a variety o~ electronic ~tructures or ~omponent~. FIG.
S illustrates general prin~iples o~ the inventi~n ~n which . the interconnect foxms an lnterface between a ~ir6t alectrical component 2 and a flat upper 6~r~ace 3 of a second electrisal component 4 to which the ~irst component 2 i8 surface mounted. The ~ir6t electrical component 2 aan be ~ny of a variety o~ electrica? components; and in the illustrated embodiment, the first electrical component 2 comprises a stxucture or substrate 5 ~ade ~ro~ a molded ~ polymeric ~aterial. The ~ubstrate has ~ir~t and second : ~urfaces 6 and 7 respectively, extending ~ubstantially parallel to each other, A plurality of ~ parate ~utually spaced apart molded plastic pro~ections or castellations 8 pro~ect downward from the second surface toward the ~lat upper 6urface 3 of the ~eco~d electrical component 4. The remote ends o~ the castellations are preferably in a ~ubstantially common plane spaced ~rom and parallel ~o the ~econd surface o~ the ~ubstrate. Multiple electrically isolated me~al surfaces g are plated to the substrate.
Each plated metal conductor extends continuously from the first ~urface of the substrate, around a side edge 10 o~
the ~ubstrate, to a common plane on a corresponding one of the castellations on the second surface of the ~ubstrate, : Alternatively, the plated conductive ~urfaces could extend ~rom the first ~uxface o~ thP 6ubstrate throug~ a thru-hole or via hole ~not sb~wn) in the ~ubstrate, to the bottoms o~ the castellations. The non-conductive u~plated ~paces 11 left on the side edge o~ the plastic ~ubstrate between the plated edge surfaces electrically isolate the row o~ individually plated metal ~ur~aces. The plated c~stellations are electrically isolated by the ~nplated ~pace~ 12 on the second sur~ace of the ~ubstruta. ~ha ~;2g35i ~

1 plated conductive aurfaces on the ~ubstrate thereby ~orm independent continuou~ electrically conductive circuit connection~ from the ~irst ~ur~ace o~ the ~bstrate to the botto~ sur~aces o~ the eastellations.
~IG. 1 illustrates one examp}e of ~ means for u electri~ally interconnecting the ~irst electrical component to the ~econd ~omponent. The c~6t~11ations on the ~r6t component can be connected to ~eparate electrical terminals, contacts, leadG, lands, or other -10 electrical conductor6 on the ~ec~nd ~omponent. These connections ~ay be made by ~eparate ~older ~oinks 13 -(shown in dotted lines in FIG. 1~, electr~cally conductive resins, or the llke.
The substrate is preferably made from a poly~eric material capable of being ~olded in~o the castellated con~iguration s~uch as by in~ection molding techniques. A
pre6ently preferred polymeric ~aterial i6 polyetheri~ide, although other polymeric materi~l~ can be used. I~ection molding techniques are desirable ~ec~u e they ~an be adapted to provlding individually narrow and closely spaced castellation~ to prov~de controlled fine pitch densiti s along the row6 of plated pla~ic castellakion~.
The molded plastic ~aterial also produces in~ividual ca~tellations which are compliant, on a microscopic level, in the sense that the individual castellations are able to ~lex or ~ove relatiYe to one another during use.
Preferably, the 6ubstrate is made ~rom a thermoplastic ~aterial which enhances compliancy, although certain thermoset material~ al~o are ~ui~able. The plà6~ic castellated arrangement ~ake~ the resulting int:erconnect between the first electrical component and the second aomponent compliant in three directions. ~hat is, the ca~tellation~ are able to ~lex or move ~on a microscop~o level) vertically, laterally ~parallèl to the row of ca~tellations~ and inwardly or outwardly at ~ach sur~ace .. ,.. ,, ~

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1 connectio~. The ~urface conn~ct~ons are therePore elastic and, a~ a result, they are able to compensate for thermal ~xpansion during use. Thi~ keeps the 601der ~o:ints 13 continuous, a~oiding di~cont$nuitie~ or fracturing ~ue ~o thsrmal ~tresse6 under heat build-up during use. In one . embod~ment, the castellatlons on the ~ubstrate an~ the ~econd component it6elf can both be ~ade ~rom a paastic material having the same thermal expansion properties, wh~ch ~oids thermal etres6es in the ~older ~oints during use~.
~ Other lmprovements provided by the plated plast~c : ~astellated interconnect of thio invention will be more ~pparent from the detailed description below in which the ~nvention is ~escri~ed with raspect to its use as an lnterfac~- for ~nterconnecting Y~rioUs e~ ectrical . components. Further, certain ~peciflc features of the electrlcal components with which the inven~ion may be used are described in detail ~n order t~ pr~vide a better : appreciation of the impr~vements and advant~ges resulting : 20 Irom the invent~on.

U~e o~ the Inerconnect as an Inter~ace Between_IC carrier and PCB
FIGS. 2 through 5 illustrate one embodiment of the plated plastic castellated interconnect used for ~ounting an integrated circuit (IC) chip to a printed circuit board (PCB). FIG. 2 i~ a perspective ~iew l~lustrat~ng basic component~ of an IC carrier 20 which includes a thin, generally parallelepiped shaped molded pla~ti~ base or substrate 22 and a molded plastic lid 24 mounted to the substrate~ The carrier encase~ a~ IC chip 26 mounted withln ~ housing formed by the molded substrate 22 and lid 24. ~he carrier plat2d plaskic castellated int:erconnect sur~ace mounts the IC carrier to a PCB as described below.

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1 FIGSI 3 through 5 illustrate the detailed construction of one embodi~ent of the ~olded plastic ~ubstrate 22. The IC chip 26 can ~ptlonally be ~ounted in a cavity in the c~nter of the ~ubstrate 22 and then elec-trically conn~cted to conductive elements on the u ~u~strate; or the IC chip oan be mounted in ~ ~avity in th~ under~ide of the lid and then connected to conductive elements on the ad~o~ning substrate ba~e. In the fir6t inatance the combination integr~ted circuit mounting and packaging assembly i~ referred to ~5 a "sav~y-up"
: configuration, and ~n latter instance the a~sembly is referred to ~s a "cavity-down" coni~uration. The e~bodiment illustrated in FIGS. 3 through 5 comprises a cavity-up con~iguration of the ~olded plastic substrate 22; ~ cavity down ~onfiguration ~s illustrated in FIG. 6.
Both configurations are considered within the 6cope ~f this invention.
Re~erring to FIGS. 3 throuyh 5, the molded plastic:
substrate has ~ ~all generally rectangular-shaped ~avity 28 extending downwardly ~nto a central region of a flat upper ~urface 30 of the ~ubstrate. The integrated cixcuit chip 26 has a rectangular configuration that matches the hap~ of the cav~ty, and the chip i~ mounted within the cav~ty as ~hown in FIG. 3. The ~ubs~rate also has fieparate rows of individual castellations 32 mutually ~paced apart ~rom one another and exte~ding downwardly ~rom a 1at undersurface 34 o~ the 6ubstrate. The rows of ca~te].lations 32 extend downwardly along ~he perimeter portion of the flat undersurface of the ~ubstrate. The castellations are uniformly ~paced apart along each edge of the rectangular-shaped substrate, and the castellations ln each row are aligned on a common axis. The p:rojections also are of uniform ~ize and shape and all extend from the bottom face of the substrate to a common plane 36 ~hown in FIG. 4. Thi~ arrangement forms uni~ormly spa~ced gaps 38 ~135~9~

1 between adjacent castellation~ around the rectanyular peri~eter of the ~ubstrate.
S~parate rows of mutually ~paced reces~es 40 are ~ormed along the outer ~ide edges of the ~ub~tr~te ln vertical al~gnme~t with corresponding cast~llationg on the unders~de of the ~ubstrate. In the illustrated ~mbodiment, the recesses 40 are each semicir~ular ~when viewed ln plan view as in ~IG. 5), and each rec~ss extends continuou~ly from the edge of the ~lat top surface 30 to the flat bottom ~urface 34 of the ~ubstrate. The projections 32 are each located i~mediately inboard from each corresponding recess 40 60 that ~he ~ur~ace of each recess continues uninterrupted around the outer surface of each corresponding castellation located behind and below it. The maximum width of each castellation thus matchPs the ~aximum width of each reces~ (as 6hown ln FIG. 4).
Each oastellation al60 has downwardly tapered side walls 42 best shown in FIG. 4. The bottom surface 44 of each castellation 32 is rounded, preferably in a ~emicircular configuration as shown best $~ the side view portion of FIG. 3. As ~entioned pre~iously, the rounded bottom : portions of the castellations lie in the common plane 36.
The individual recesses 4~ 6paced apart along each outer edge o~ the substrate are ~eparated by corresponding castellations 45 intervening in the ~paces between adjacent recesses.
As ~hown best in FIG. 3, a plural~ty o~ ~eparate metal conductors 46 are pl~t~d on the flat top ~ur~ace o~
; the substrate. The conductor~ are arranged in ~our groups which fan outwardly ~rom the vicinity o~ each of the four ~ides of the rectangular cavity 28 toward aorresponding outer edges of the rectangular ~ubstrate. Each metal conductor plated to the 6ubstrate exten~s to a corresponding recess 40 formed in the outer ed~e of the 16~
1 ~ubstrate. In the illustrated embodiment, the carrier has 84 conductors, 21 per 6ide.
:~ The metal conductor6 are plated to the ~ubstrate so that they are directly bonded to its ~urf~ce. The conductor~ ~re preferably ~pplied to the 6urface by a ~~combination of electroless plating and electroplating t2chnigues described below. ~hese technique~ plate the ~olded plast~c substrate with one or ~ore layer6 of es~entially pur~ deposited metal while the re6ulting ~etal : 10 layer ~s ~eing bonded directly to the 6ubstrate. A
combination of copper, nickel and gold is preferably used to ~orm the plated metal conductor~; although othe~ m~tals capable o~ being plated to the 6ur~ace of the ~slded plastic ~ubstrate can be used.
The plated co~ductor~ are applled in thin layers and therefore re re~erred to herein ~ conductive metal circuit traces. They are electrically ~eparated ~rom one I another by the electrically in~ulativ~ pla~tia ~ater~al Or . the substrate ~ody which occupies t~e space~ 48 on ~he 6urface between the ind~vidual conductive traces. . These :- ~arrow in~ulatiYe spaces formed ~y ~he ~lat ~ur~ace of the 6ubstrate ~ody thereby ~an outwa~dly toward corre~ponding ~lectr~cally-~nsu~at~ve project~ons 45 ~t the periph~ry o~
the 6ubs~rate. ~he clrcu~t trace~ 4B extend con~inuou91y from the top BurfaCe o~ 1:he E;ubstrate, around the uprlght faces of the recesses 40~ an~a ther~ arour~d the rounded botto~ sU~;l:ace:~i 44 or ~;he cast;ollations 32 . ~rhe bottom ~urfaces OS ~he castellatl~lls~ a~t lea~t iJ~ t~ p~ane 36, are plated wi~h the electrlcally conduct~ve ~t~l t~aces.
q~hus, ~ach condu~tive trac~ on the substrate forms a cont~nuous electri~al lead from the ~ubstrate top ~urface, around the edge o~ the substrate, to the bottom portion o~
A corresponding cas~ellation 32 on the bottom o~ the substrate. The circult traces which are plated to the upright 6emicircular ~aces o~ the recesses 40 are elec-~2~3S~

krically insulated from one another by the corresponding çastellations ~5 that #eparate the re~e~es along the outer edge~ of t~e 6ub~trate. Further, the eleckrlcally conductive traces on the curvad bottom portions of the ; 5 castellations 32 are electrically in~ulated from one '-another by the air gaps 38 that ~eparate the individual castellations along the 6ubstrate bottom ~urface. Owing to the electrical ~eparation o~ the castellations ~rom one another, the $ntegr~ted clrcult carr~er Gan be surface mounted on a PCB having it~ top surface in the plane 36 ~hown in FIG. 4. ~hi~ l~aves the air gap~ 38 between the bottom ~urface 3~ of the substrate and the top of the printed circuit board, as we}l as the open gaps between conductive surfac~s on ad~acent bottom castPllations 32.
Furth~r details relating to mounting of the integrated circuit carrier to ~ printed circuit board are described ; below.
The integrated circuit carrier al~o ~ncludes ~eans for mount~ng the integrated circuit chip 26 within the ~:20 housing ormed by the carrier. In the cavity-up conflguration, the conducti~e metal traces 44 are elec-trically connected to the integrated circuit chip 26 by corresponding fine wire leads 50. These fine wira leads are metallurgically bonded between individual spaced bonding pad~ 52 ~n the integrated circuit and corresponding bonding points 54 on the ~ndividual conductive metal traces 44. In a typical arrangement, the fine wire leads from the integrated circuit ar~ ~eparately connected to certain of the metal traces and need not be connected to all of the conductive metal traces. ~he connection6 between the inteqrated circuit and the conductive metal traces illustrated at FIG. 3 are ~imply an example ~howing connaction between the int:egrated c$rcuit and any desired number of the elect:rically conductive traces. Thuæ, A ~eparate electrical aircuit is 1~935~

1 ~ormed between each lead fro~ the integrated circuit chip arros~ the integrated cirouit carrie:r surface and to th~
~ottom surface of the ~arri~r to ~ 6eparata one of the - bottom caætellations 32 which, in turn, are bonded to corre~pondlng contacts on the printed circuit bo~rd.
~~. As mentioned previously, FIGS. 3 through 5 illustrate the eavity-up configuration in wh~ch the integrated circuit ohip i6 mounted to the substrat~ ~nd connected directly to corresponding ele~trically conductive traces on the 6ubstrat~. In an alternative arrangement, ~ illu6trat&d in FIG. 6, an integrated circuit ~hip 56 can be mounted ~n the eavity-down configuration. In this arrangement, the integrated circuit chip 56 is ffixed t3 ~ spreader 57 oarried ~n a pacXage S8. The ~preader ha~ a ;; 15 downwardly ~acing urfa~e 60 having metal traces (not . shown) ~annlng outwardly fro~ the integrated circult chip : in a manner similar to the top surface 30 of the substrate 1 32. In the cavity-down arrang~ment, the ~olded plastiG
6ubstrate 62 includes a large central cav~ty 64 to provide ; 20 space ~or the downwardly pro~ecting integrated ~ircuit chip 5C. Separate fine w~re leads 66 electrically connect wire bonding pads on the i~tegrated circui~ to corresponding conduc ive metal traces on the spreader 570 ~he electrically conductive traces on the ~preader are 601dered, cemented, or otherwi6e electrically connected to corresponding electrically conductive traces on the top ~ide 68 of the substrate 62. Electrical contact is achieved between the ~preader and ~he substrate by ~eans of the adhesive, ~older or cemenk which iorm discrete, 30 electrically i601ated lands between the two ~;urfaces.
The molded plastic substrate 62 includes the 6paced apart castellation~ 70 extendiny along the outer periphery of the bottom sur~ace of the substrate. Correspondin~
spaced apart rece~6ed regions (not 6hown in FIG. ~) extend along the outer 6ide walls 72 o~ the substx~te, in ~Z9~

vertiGal ~lignment with the b~ttom castellatiorls. As with the embodiment illustrated ira FIGS . 3 through 5 ~ the upright fa~es OI the recesses and the bottom castellations 70 are plated with the elec:tr~cally condu~t~e ~netal 5 circuit traces to prc~vide individual continuous ' - electrically ~onduct~ve paths ~rom the bottom~ . of the ca~tellations 70 to the ~ine ~rire lead6 66 OI the integrated circuit 56.

~o ~ ocessinc~ 'rechniques FIGS. 7 and 8 ~ llustrate one embodlment of a ~ethod ~or ~aking the 6ubstrate base portion of the integrated c:ircuit carrier. The ~ubstrate i6 pre~erably made by in~ ection molding techniques in order to ~irst ~orm a 15 mt~lded plastic base 80 of thin, parallelepiped shape. The molded plastic hase ha~ a flat top surf~ce 82 with a shallow rectangular 6haped recess 84 in its center. Four row~ of holes 86 extend through tl:le depth of the b~se 80.
The rows of holes are uniformly spaced outwardly from the 20 ~Eour ~ides of the central recess. The four rows o~ holes are also unifonnly ~paced inwardly ~rom the four outer edges 88 of the base. The upper surface 82 o~ the base 80 al~o inc:ludes three ~hallow recesses 99 which register with three corresponding alignment pins ~n the underside o~ the lid when the lid 24 is mounted to the integrated circuit carri~r. ~he molded plastic base 80 ~urther includes four rows of ~paced apa~^t ~astel}ations 92 : extending from a ~lat bottom face 94 o~ the ba~e 80. The rows o~ molded bottom castellations 92 are immediately inboard from the holes 86, and the con~iguration of the castellations 92 and their positioning with res~ect to the hole~ i~ ldentical to the castellations 32 on the 6uhstrate illustrated in FIGS. 3 through 5. The bottom face o~ the ba~e 80 also includes a peripheral 6ur~ace 96 35 which is rai6ed slightly ~rom the ~hallow recessed ~ace 94 ~L~93S44 --~o-1 on which the ca~tellation~ are ~ormed. Thi~ raise.d outer peripheral ~ur~ace 96 provt~es a flat ~ur~a¢e ~n ~he same plane ~ the bottom6 o~ the castellations 92.
Ae ~lluded to previously, the molded pla~tic base ~0 5 ~hown in FIGS. 7 and 8 can be ~ade from a variety of u plastic material6 capable o~ ~orming the base by in~ection molding techniques. In~ection molding technigues are preferred because the entire topography o~ the base 80 6hown in FIGS. 7 and 8 can be in~ection mol~ed a~ ~ ~ingle 10 ~ntegral unit~ with retractable plns (not ~hown) used in the ~old ~or forming the rows of ~paced apart h~les 86.
Injection ~olding techniques al60 result in producing a desired configuration of the bottom castellatio~s 92. The castellations also can ~e.molded 60 they are ~dividually 15 narrow and closely paced to provide a ~ine pitch density of castellations along ~he rows o~ corresponding holes.
~he in;ection molded plastic ~aterial al60 re~ults in the individual ca6tellation6 being compliant, on a ml roscopic level t as described previou~ly.
: 20 Following inject$on molding o the plastic base 80, the ~urfaces o~ the ba~e are activated by ~ ~uita~le ~izing material to enhance honding o~ the electrically conductive metal plating to the base 80. ~fter activating the ~urface~, a conductive metal ~uch a~ copper i8 first plated onto all surfaces of the base. In a preferred technique, a continuous ~ilm of electroles~ ~opper is ~ir~t plated on the base, 2referably in a ~lm thickness of about ten ~icro-inches. The copper i~ then patterned usi~g lithographic techniques and etched ~ollowed by depositing a one mil thick ~ilm of electrolytic copper.
Approximately 100 to 150 micro-inches of nickel ara then electroplated over the copper, ~ollowed by an approximately 50 micro-inch layer o~ gold. ~hese dimen~ions and materials can vary without departlng ~rom 93S~4 1 the scope of the invention. The plating technigues also can vary.
Br~e~ly, electroless plating compris~s ~pplying ~
coating o~ ~etal from an electrolyt~ ~olution o~ a ealt containing ion~ of the ~etal being dep~ited. The coating '- i deposited without applying electrical current but by chemical reduction. Electroplatlng oomprises ~pplying the : ~oating o~ ~etal by passing an electric ourrent through an ~lectrolytic ~olution o~ a salt containing ions o~ the metal being deposited. Metal eputtering techniques also can be u~ed and these include applying the coating in a vacuu~ tube having metal ions emana~ing ~rom a cathode and deposited as a film on the object contai~ed within the tube. Three phases o~ this technique compri~e generating . 15 a metal vapor, diffu~on of the vapor, and condensatio~.
Vacuum metalizlng tech~iques al~o can be used and these ; lnclude applying a coating o~ metal ~y evaporating the metal under high vacuum and condensing lt on the ~ur~ace : of t~e base mater~al. Applicable electroplating, : 20 electroless plating, and ~puttering technigues are ~escribed in MODERN PLASTICS ENCYCLVPEDIA, 1986-1987, pp.
370-371; ~nd 1984-1985, pp. 372-374. Applicable vacuum metalizing techniques are described in MOD~RN PL~STICS
- ENCYCLOPEDIA, 1986-198~, pp. 381-382. Plastics injection 2~ molding technigues are described in ~ODERN PLASTICS
ENCYCLOPEDIA, 1983-1984, pp. 248-271; and 1984~-85, pp.
258-281. These di~closures are in~orporated herein by th~s reference.
These techniques for forming a thin metal ~ilm on the ~ubstrate are referred to hereln as "plati~g" techniques in the sense that they deposit on the base a thin film or layer, or multiple layers, of es~entially pure metal which i~ bonded directly to the sur~ace of tha base. 'rhe metal layer which is plated to the base i~ continuous and covers the top and bottom ~ur~aces, the 6ide edge~, and the 3~Z~;~5~4 1 entire upright ~ace of the holes 86 in ths base. The plated ~etal film ls applied in a thin ~il~ thickness : which allows etc~ing aw~y to ef~ectively ~orm th~
electrically ~eparated ~etal circuit traces. The plating techniques allow etching away to form ~onductive traces which are indiv~dually narrow and clo8ely spaced apart in a high pitch density. Conductive tr~oes with a width as low ~ about BiX milB ~nd an on-center 6pacing as low as about ten mils can be formed by such plat~ng ~nd etching . 10 technique Following metal plating o~ the base B0, certai~
rsgions of t~e plated metal are removed ~rom the base to form the resulting pattern of eeparate electrically con-ductive traces on the base~ The metal is removed by 1~ conventional- l~thography and etching technigue~ which ~: lea~e the narrow electrically insulativ~ ~urfaces between the conductive metal traces. Th~ resulting ~etal traces ., are continuous across the top surface; d4wn through the ~ holes 86 and around the bo~tom surfaces of the :~ 20 castellations g2 at the bas~ o~ the plastic ~ubstrate.
~ ollowing the p~ating 6tep, the base i~ ~evered along straight lines extendi~g through the centers of each row o~ the holes 86. One of the lines along which the base is severed i~ shown at 98 in FIG. 7. ~his produces the rectangularly-shaped (square) ~ubstrate ~hown in FIGS. 3 through 5 in which th~ metal pIated semi-circular recessed re~ions are spaced apart along each side edge of the substrate.
Sev~r~l additional advantages are provide~ by the techn~que~ for forming the interconnect module according to this invention. For instance, injection molding technique~ can be used to produce integrally molded plastic interconnect modules with any desired topography, including geometries that can provida a ~ine pitch density o~ the conductive metal tr~ces. ~he combinatiOn o~

54~

-23~
1 in~ection ~olding ~n a desired configuration, with mekal plating ~n~ subsequent re~oval o~ the ~etal in ths desired ~reas, allow~ ~he fl~e pitch ~en~ity to be provided effectively ~rom the top ~urface, throu~h the xecessed por~ions of the ~ubstrate~ to the castellations on the -bottom of the ~cdule. The result i~ a leaded ca~t:ellated lnterconnect module without the disadvantages re.sulting from u~e o~ a separate metal leadframe. These technigues al~o are advantageous ~n providing an IC carrier with castellations in a ~esired pattern to ~atch the footprint pattern of ~he contacts on the PCB to whlch the carrier may be ~ounted.
Following plating and etching to form the pattern of conductors on the carrier 20, the IC chip 26 $s moun~ed to the recess in t~e carrier, and the chip i6 wire bonded to the conductlve ~etal traces. ThQ plastic lid 24 is then ;~ placed on the carrier and bonded to it with a resin su~h as an epoxy resin. The lld-glue combination encapsulates the IC chip.
Alternative Geometries of _Plated Plastic Castellated Interconnect FIG. 9 ~chematically illustrates ~urface mounting of the IC carrier to a PC~. The castellations 3Z at the base .2S of the ~ubstrate 22 project downwardly ~rom the bottom : ~ur~ace 34 of the ubs~rate ~or electrica~ connection to corresponding electrical contact~ 99 on a top ~urface 100 of a printed circuit board 102. The bottoms sf the castellations are electrlcally connected to the contacts on the board by eeparate 601der ~oints 104 or electrically conductive resins which are electrically separated from one another. FIG. 9 lllus~rates that each plated electrical conductor i8 electrically ~eparated from the ad~acent conductor and, due to its placement on the cor-responding castellation, it ~s ~paced away from the bottom ~L2~3S'~

~2~
1 Eide o~ the base. ~ a result, the carrier, including the ~ase, can be mounted to the PCB and ~oldered or glued to the contacts 99 on the board, while leaving the gap 106 between the bottom of the base and the top of the board.
Th$~ gap allow6 clean~ng under the ~ase an~ makes it easier to ~void electrical s~ort6 between the pl~ted electrical leads.
The Eur~a~e-mounted lntegrated clrcu$t c~rrier illus-trated in FIG. 9 depict6 dimension~ of a typical ~0 castellated plastic $nterconnect module that can be produced accordi~g to princ~ples of this invention. In the illustrated embodimentl the pro~ecting contacts 32 are spaced apart by an on-center dimension a of 0.025 ~nch.
Th2 lateral distance b between ad~acent castella~ions is ~- 15 0.010 inch. The lateral 6pacing c betwe~n adjacent ~oldered ~oint 104 i~ about 0.007 in~h. The wid~h d of each castellation ~s about 0.015 inch. The ~pacing e between the bottom 6urface of the integrated circuit oarrier 22 and the top urface o~ ~he printed circuit board i6 about 0.020 inch. The IC carrier o~ this lnvention can be produced with it~ metal lea~s ln a fine pitch density in the sense that conductors 46 can be ~paced apart by an on-center spacing of about 25 mils or less, with a spacing between conductors o~ ~bout ten mil or les~.
Although an I~ c~rrier with the lead densities ~escribe~ in xelation to FIG, 9 is use~ul for ~any applications, FIGS. 10 through 12 ~llustrate an alternative embodiment in which the carrier can be ~olded with a more intricate oonfiguration in order to ~ncrease lead densities. In the embodiment o~ FIGS. }0 through 12, there are two rows of alt~rnating, recessed conductive ~urface~ extending along each slde edge o~ an I~ carrier substrate 110. The recessed conductive surfaces face outwardly along each edge and a~ternate ~rom one row to ~zg3s~4 1 the next R0 as to form spaced ~part castellatio~s 112 extending laterally outwardly from each ~dge of the ~ubstrate. The outer faces o~ the~e aastellations are prePerably rece~sed ~nd ~re aligned in ~ common plane to form ~ first outer row of spaced ~part conductive - 6ur~aces. The gaps 114 left between the adiacent ca~tellations al60 have reces~ed conductive ~ur~aces to for~ ~ ~eoond inner row of spaced apart conductive ~urfaces. Plated conductive metal traces (schematically lllustrated at 116 in FIG. 10) fan outwardly in ~ pattern fro~ the vicinity o~ a central cavity 118 on the top ~urface of the substrate toward th~ ~irst and second rows of ~lternating recessed faces along ea~ edge o~ the ~ub~trate. Only a porti~n Or the fan ~haped pat~ern I5 plated conductors is shown in FIGo 10 for ~implicity.
~: FIGS. 11 and 12 illustrate castellations on ~ bottom surface o~ the substrate ~hown in FIGo 10~ In this e~bodiment, alternating castellagion~ 120 pro~ect downwardly ~rom th~ undersid~ o~ the ~irst row of castellations 112, and a 6econd row of castellations 122 pro;ect downwardly from the ~econd row of conductive ~ur~aces 11~. Thus, two parallel row~ of al~ernating castellations are ~ormed along the bottom periphery o~ the integrated circuit carrier, and all ~astellations extend :25 to a common plane. The electrically ~onductive traces 116 are plated on the lower portion~ of the ~rst and second row~ o~ alternating castellations, and the plating on each :: of the castellations i~ electr~cally separated ~rom the plating on the other castellations. The rear edges o~ the castellations oan either be concave as shown in FIG . 11 or ~tra~ght as ~hown in FIG. 12, These figures also illustrate how the castellations are molded so as to maintain physical ~eparation between the c:onductive ~urfaces o~ ad~acent castellations.

:lZ~3S~9~

, -2~-1 ~he e~bodiment of FIGS. 10 through 12 provides a ~ean~ ~or lncreaslng the lead pitch denslty of the integrated ~rcuit carrier i~asmu~ a~ add~tional condu¢tive traces are plated ln 6paces nor~ally o~cupied by wider electr$cally insulative surfa~es Eeparating a u ~ingle row of castellations.
. FIGS. 13 and 14 6chemat~cally illustrate a further ! embodiment o~ khe invention in wh~ch the plated plastic castellated interconnect is formed by plated thru-holes or ~, 10 via holes 124 in a plastio 6ubstrate 126. The thru-holes are arranged ~n ~ny desired pattern around th~ outer periphery of the substrate. In the illustrated embodiment,:the plated thru-holes alternate between two parallel rows inboard from each edge of the ubstrate.
'15 Bott~ castellations in the ~orm of ~eparate æpaced apart ;,integrally ~olded pads 12S are formed at the base of each o~ the plated thru-holes. ~he thru-holes open through a ~¦rounded bottom:portion o~ each ~olded pad. The pads ~old the substrate 126 ~paced above the top Eiurface of a ~econd component 6uch as a printed clrcu~t board 130. rhe pads 128 are bonded to ~ontacts on the board. ~eparate plated conductive metal traces 132 on the upper ~urface of the ~ubstrate form continuous electrical ~ondu~tors 6paced apart ~ro~ one another and extQnding through c~rresponding plated thru-holes to the bottoms o~ the stand-off pads.
Although the bottom ~ur~aces o~ the pads 128 can be plate~l, the 6eparate ~older ~oints 132 at the botto~ of each ~ated t~ru-ho~ proYide ~n e~ectrica~ connection between the interior o~ each plated thru-hole and the corresponding contact on th~ boar~.

~nter~ace_8etwee~ e~ S~ 8~_~~
FIGS. 15 through 17 ~llus rate further embodiments o~
the invention. In addition to the example shQwing use o~
th~ invention as an inter~ace between an IC carrier and a ~3S4~

-27~
1 PCB, the plated pla~tic ca~tellated interconn~ct can : provlde ~urface connection6 o~ other electr~cal components to a 6upport ~a~e such a~ a PCB or a hou~ing, for exampl~.
FIG. 15 illustrates use Qf t~e l~vention as an ~nterfa~e ~or ~n electrical ~ocket 134 sur~ace ~ounted to a PC~ 136.
(~he 601der ~oints are not shown in FIGS. 15 through 17 ~or simpl~city.) The 60cket i5 made from a molded plastic mater~al and ~or~s ~n upwardly ~acing cavity ~aving a ~lat base 137 and a peripheral ~ide wall 138. Rows of plastlc castellations 140, si~ilar to tho6e described in the pr2viou~ embodimente, project downwardly ~ro~ the underside of the ~ocXet. At e~ch castellation, a s~parate integrally molded plastic spring 142 t~n ~h~ Xorm of an inwardly projecting leaf ~pring type contactj i~ biased into ~prin~ contact with an IC pa~kage 144 carrying an IC
: chip 146. Spaced apart plated metal circuit traces 148 on the packa~e 144 make contact with corresponding continuous pl~ted metal circuit trace~ 150 extendinq ~rom the bottoms of the castellations 140 to the exterior ~f the ~pring contact 142.
FIG. 16 illustrates ~n alter~ative ~orm of a surfa~e mounted castallat~d plastic interconnect ~ocket 152. This ~ocket has row6 of integrally molded plastic cas~ellations 154 ~urface moun ed to a PCB 156. The ~ocket also 25 includes and upwardly facing cavity 158 for receiving an ' IC package 160 carrying an IC chip 162. In thi~ form of the ~ocket, separate metal s~?rings 162 are connected by pins 164 to plated thru-holes 166 in correspond.ing castellations 154, The ~prings includa inwardly projecting contacts 168 for making a ~pring-bia~ed electrical contact with corresponding plated meta'L circuit trace6 170 on the IC package 160~ The plated thru-hol~s 166 provide electrical contact ~rom the ~older ~olnts at ~he bottoms of the castellation~, through the plated thru-~35~4 1 holes~ to the pin~ 164 and to ~pring cvntacts 168, to the electrical c$rcuit traces 170 on the ~C package.
.
: Interface B~tween Carrier for a Pin Grid and PCB
FIG. 17 shows a further alternate embodiment of the ^- plated plastic c~stellated interconnect in the ~orm of a carrier 172 for a p~n grid 174. The oarrier 172 ha~
~ntegrally ~olded castellat~ons 176 w$th plated metal . circuit traces 178 electriaally connected to ~ PCB 180.
: 10 The pin grid 174 includes a plurality of downwardly facing : pins 182 extending ~nto corresponding plated thru-~oles ,: 184 in the castellations. Electrical connections from an ~: IC ch~p 186 on the carri~r 174 are ~ade through the ~ ~orresponding pins 182 to the sur~a~e ~ount connect$ons of :; ~ lS the ¢astellations to the contact~ on the ~CB.

~: Thus, the plated plastic castellated interconneck of ~. thi~ invention provides for ~ine lead pitches and :~. resulting higher lead counts than other prior art IC
~arrier~ 6uch as those using the metal leadframe, printed wiring b~ard, and ceramic IC ~arrier tech~ique~. The invention al60 eliminates the additlonal expense of using metal leadframe ~ech~iques or the additional manufacturing çosts and problems associated with ceramic IC carriers.
The ~olymeric ~ubstrate ~an be ~olded in various geometrles which can ~ncrease lead pitch densities, ~ncluding the ~ult;pl~ rows of spaced apart castellations ; at the bottom of the molded ~ubstrate. ~he molded plastic ca~tellatlons al~o can be ~ormad in a geometry and made ~ro~ ~ ~ubstance which can allow ~or a certain level of compliancy in 6ur~ace mount connections while ensuring good contact to a PCB to enhanca rellabili~:y of the electrlcal connection6. ~he module maintains alignment and planarity through standard IC testing, ~hipping and handllng. ~he module also all~ws ~or thorough cleaning of 3S~

fluxes ~nd conta~inants bstween khe bottom o~ t~e module ~nd the PCB in order to provide :rel$able connections without el~ctrical failures OI the assembled PCB.

. .

~.

:

Claims

1. A plated plastic castellated electrical interconnect comprising:
a substrate made from a molded polymeric material and rising first and second principal surfaces substantially parallel to each other;
a plurality of separate mutually spaced apart and individually compliant castellations integrally molded to the polymeric substrate and projecting from the second surface thereof to a substantially common plane spaced from the second surface; and a plurality of electrically separated metal conductors plated to the substrate by metal plating techniques r the substrate including spaced apart, recessed regions extending between the first and second surfaces and in which the castellations are aligned with corresponding recessed regions, each of the plated conductors extending continuously from the first surface along a corresponding recessed region to the common plane on a corresponding one of the castellations, the plated metal conductors being adapted for electrical connection to a first electrical component adjacent the first surface of the substrate and the conductors being arranged on the castellations for electrical connection to a second electrical component adjacent the second surface of the substrate.

2. The electrical interconnect according to claim 1 in which the recessed regions are formed by a portion of a hole extending through the entire depth of the substrate from the first surface to the second surface thereof.

3. The electrical interconnect according to claim 1 in which each castellation is immediately inboard from and aligned with a corresponding recessed region.

4. The electrical interconnect according to claim 1 including a cavity on the first surface of the substrate for accommodating the body of the first electrical component.

5. The electrical interconnect according to claim A in which the first electrical component comprises an integrated circuit chip.

6. The electrical interconnect according to claim 1 in which the bottoms of the castellations are rounded convexly in a direction substantially perpendicular to the side edge of the substrate.

7. The electrical interconnect according to claim 1 in which the metal conductors are plated directly to the substrate and bonded thereto in a continuous metal film whose thickness consists essentially of the plated conductive metal.

8. The electrical interconnect according to claim 1 in which the substrate has a substantially planar first surface.

9. The electrical interconnect according to claim 1 in which the substrate comprises a carrier having a cavity, and in which the first or second electrical component is disposed in the cavity.

10. The electrical interconnect according to claim 9 in which the substrate cavity accommodates an electrical component electrically connected to a carrier which, in turn, is electrically connected to conductors on the first surface of the substrate in a cavity-down configuration.

11. The electrical interconnect according to claim 1 in which the spaced apart recessed regions comprise alternating first and second rows of recessed surfaces spaced apart along a portion of the substrate, in which the first recessed surfaces are aligned along a first axis and the second recessed surfaces are aligned along a second axis spaced from and extending substantially parallel to the first axis; and including separate rows of first and second castellations molded to the second surface and positioned adjacent to corresponding first and second recessed surfaces along corresponding first and second axes, respectively, the separate conductors extending from the first surface, along the first and second recessed surfaces and then to said common plane on the first and second rows of castellations, for increasing the lead count of the integrated circuit carrier.

12. The electrical interconnect according to claim 1 including a printed circuit board having a footprint of electrically conductive contacts matching at least a portion of the castellations on the second surface of the substrate;
and means bonding the castellations to the contacts.

13. The electrical interconnect according to claim 1 in which the first or second electrical component comprises an integrated circuit chip.

14. The electrical interconnect according to claim 1 in which the castellations on the substrate are surface mounted to a support base comprising a printed circuit board.

15. The electrical interconnect according to claim l in which the substrate comprises an electrical socket.

16. The electrical interconnect according to claim 1 in which the substrate comprises an electrical connector for said electrical component.

17. A plated plastic castellated interconnect for electrical components comprising:
a substrate made from a molded polymeric material having first and second principal surfaces substantially parallel to each other, a plurality of separate mutually apart and individually compliant castellations integrally molded to the substrate and projecting from the second surface thereof to a substantially common plane spaced from the second surface, and a plurality of separate spaced recessed regions on the substrate and aligned with the castellations and extending from the frist surface to the second surface of the substrate; the substrate having a plurality of electrically separated metal conductors plated thereon by metal plating techniques, each of the conductors extending continuously from the first surface, along a surface of the recess and to the common plane on a corresponding one of the castellations.

18. The electrical interconnect according to claim 17, including:
a support base having a footprint of electrically conductive contacts matching at least a portion of the castellations on the second surface of the substrate, and means bonding the castellations to the contacts on the support base.

19. The electrical interconnect according to claim 18 in which the support base comprises a printed circuit board.

20. The electrical interconnect according to claim 17 in which the recessed regions are formed by a portion of a hole extending through the entire depth of the substrate from the first surface to the second surface.

21. The electrical interconnect according to claim 17 in which the castellations are immediately inboard from and aligned with each corresponding recess.

22. The electrical interconnect according to claim 17 in which the bottoms of the castellations are rounded convexly in a direction substantially perpendicular to the axis through the aligned recesses on one side of the substrate.

23. The electrical interconnect according to claim 17 in which the electrical conductors are plated directly to the substrate and bonded thereto in a continuous metal film whose thickness consists essentially of the plated conductive metal.

24. The electrical interconnect according to claim 17 in which the substrate has a cavity for receiving an electrical component mounted to the substrate in a cavity-down configuration.

25. The electrical interconnect according to claim 17 in which the substrate comprises an electrical socket.

26. The electrical interconnect according to claim 17 in which the substrate comprises a carrier for an integrated circuit chip, and in which the carrier is surface mounted to a printed circuit board.

27. The electrical interconnect according to claim 17 in which the spaced apart recessed regions comprise alternating first and second recessed surfaces spaced apart along a portion of the substrate, in which the first recessed surfaces are aligned along a first axis and the second recessed surfaces are aligned along a second axis spaced inwardly from and extending substantially parallel to the first axis; and including separate rows of first castellations and second castellations positioned adjacent to corresponding first and second recessed surfaces along corresponding substantially parallel first and second axes, the separated plated conductors extending from the first surface, along the first and second recessed surfaces, and to the first and second castellations to increase the lead density of the integrated circuit carrier.

28. A method for producing a castellated electrical interconnect comprising:
molding an electrically insulative substrate from a polymeric material to form on said substrate opposite first and second surfaces, one or more rows of spaced apart holes extending through the substrate from the first surface to the second surface thereof, and rows of separate spaced apart molded compliant castellations formed inboard from corresponding holes on the second surface of the substrate, the multiple castellations extending to a common plane spaced from the second surface of the substrate;
coating the molded substrate by a metal plating technique with a conductive metal for covering the first and second surfaces and the interior of the holes with a continuous fill of plated electrically conductive metal; and removing portions of the metal from the substrate to form separate plated metal conductors separated from one another by the electrically insulative substrate to form separate plated conductive circuit traces, each circuit trace extending continuously along the substrate from the first surface thereof, along a wall portion of the hole and to said common plane on the castellation corresponding to the plated hole surface, to provide spaced apart electrically conductive surfaces on the castellations arranged for surface connection to corresponding electrical contacts on a support base to which the substrate is mounted.

29. The method according to claim 28 in which the substrate is formed by injection molding techniques.

30. The method according to claim 28 in which the substrate is made from a polymeric material that produces compliant castellations.

31. The method according to claim 28 including the further step of severing the substrate along an axis through the row of holes to form a row of spaced apart recessed regions along an edge of the substrate in which the plated portions of the recessed regions are electrically insulated from adjacent recessed regions by intervening portions of the electrically insulative substrate body.

32. The electrical interconnect according to claim 1 in which the molded polymeric material comprises a thermoplastic material.

33. The electrical interconnect according to claim 1 in the individual castellations are compliant, on a microscopic level, so that the individual castellations are able to flex in three mutually orthogonal directions and thereby compensate for thermal expansion during use.

34. The electrical interconnect according to claim 19 in which the molded polymeric material comprises a thermoplastic material.

35. The electrical interconnect according to claim 17 in the individual castellations are compliant, on a microscopic level, so that the individual castellations are able to flex in three mutually orthogonal directions and thereby compensate for thermal expansion during use.

36. A plated plastic castellated electrical interconnect for surface connection of an electrical component to a support comprising:
a substrate made from a molded polymeric material and comprising first and second surfaces substantially parallel to each other;
a plurality of separate mutually spaced apart castellations integrally molded to the substrate and projecting from the second surface thereof to a substantially common plane spaced from the second surface; and a plurality of electrically separated metal conductors plated to the substrate, each of the conductors extending continuously from the first surface, around or through the substrate, to the common plane on a corresponding one of the castellations, the conductors being arranged on the castellations for surface connection to a support base and for electrical connection to an electrical component carried by substrate and electrically connected to the conductors on first surface of the substrate;
in which the substrate includes spaced apart recessed regions molded in the side edge of the substrate, and the castellations are aligned with corresponding recessed regions; and plated conductors extend along a corresponding recessed region to the surface of a corresponding castellation; and in which the spaced apart recessed regions comprise alternating first and second rows of recessed surfaces spaced apart along a portion of the substrate, in which the first recessed surfaces are aligned along a first axis and the and recessed surfaces are aligned along a second axis spaced from and extending substantially parallel to the first axis; and including separate rows of first and second castellations molded to the second surface and positioned adjacent to corresponding first and second recessed surfaces along corresponding first and second axes, respectively, so that the separate conductors extend from the first surface, along the first and second recessed surfaces and then to said common plane on the first and second rows of castellations, thereby increasing the lead count of the integrated circuit carrier.

37. A plated plastic castellated electrical interconnect comprising:
a substrate made from a molded polymeric material having first and second surfaces substantially parallel to each other, a plurality of separate mutually spaced apart castellations integrally molded to the substrate and projecting from the second surface thereof to a substantially common plane spaced from the second surface, and a plurality of separate spaced apart recessed regions molded in the substrate and aligned with the castellations and extending from the first surface to the second surface of the substrate;
the substrate having a plurality of electrically separated metal conductors plated thereon, each of the conductors extending continuously from the first surface, along a surface of the recess and to the common plane on a corresponding one of the castellations;
in which the spaced apart recessed regions comprise alternating first and second recessed surfaces spaced apart g a portion of the substrate, in which the first recessed surfaces are aligned along a first axis and the second recessed surfaces are aligned along a second axis spaced inwardly from and extending substantially parallel to the first axis; and including separate rows of first castellations second castellations positioned adjacent to corresponding first and second recessed surfaces along corresponding substantially parallel first and second axes, the separate plated conductors extending from the first surface, along the first and second recessed surfaces, and to the first and second castellations, to thereby increase the lead density of the integrated circuit carrier.