CA1250370A - METHOD AND DEVICE FOR ACCESSING A MEMORY BY TABLE TRANSFORMATIONS - Google Patents
METHOD AND DEVICE FOR ACCESSING A MEMORY BY TABLE TRANSFORMATIONSInfo
- Publication number
- CA1250370A CA1250370A CA000504551A CA504551A CA1250370A CA 1250370 A CA1250370 A CA 1250370A CA 000504551 A CA000504551 A CA 000504551A CA 504551 A CA504551 A CA 504551A CA 1250370 A CA1250370 A CA 1250370A
- Authority
- CA
- Canada
- Prior art keywords
- memory
- intelligent
- processor
- read
- data structures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Complex Calculations (AREA)
- Memory System (AREA)
- Multi Processors (AREA)
- Executing Machine-Instructions (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000583308A CA1262968A (en) | 1985-04-05 | 1988-11-16 | Method and apparatus for addressing a memory by array transformations |
| CA000583309A CA1264093A (en) | 1985-04-05 | 1988-11-16 | Method and apparatus for addressing a memory by array transformations |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US72033085A | 1985-04-05 | 1985-04-05 |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000583309A Division CA1264093A (en) | 1985-04-05 | 1988-11-16 | Method and apparatus for addressing a memory by array transformations |
| CA000583308A Division CA1262968A (en) | 1985-04-05 | 1988-11-16 | Method and apparatus for addressing a memory by array transformations |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA1250370A true CA1250370A (en) | 1989-02-21 |
| CA1262968C CA1262968C (enEXAMPLES) | 1989-11-14 |
Family
ID=24893595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000504551A Expired CA1250370A (en) | 1985-04-05 | 1986-03-19 | METHOD AND DEVICE FOR ACCESSING A MEMORY BY TABLE TRANSFORMATIONS |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0201174B1 (enEXAMPLES) |
| JP (1) | JPH0731629B2 (enEXAMPLES) |
| AU (2) | AU582632B2 (enEXAMPLES) |
| CA (1) | CA1250370A (enEXAMPLES) |
| DE (1) | DE3650754T2 (enEXAMPLES) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4882683B1 (en) * | 1987-03-16 | 1995-11-07 | Fairchild Semiconductor | Cellular addrssing permutation bit map raster graphics architecture |
| JP2690932B2 (ja) * | 1988-03-18 | 1997-12-17 | 株式会社日立製作所 | ディジタル信号処理プロセッサおよびディシタル信号処理プロセッサシステム |
| US6170046B1 (en) | 1997-10-28 | 2001-01-02 | Mmc Networks, Inc. | Accessing a memory system via a data or address bus that provides access to more than one part |
| GB0130534D0 (en) | 2001-12-20 | 2002-02-06 | Aspex Technology Ltd | Improvements relating to data transfer addressing |
| JP5811099B2 (ja) * | 2010-11-24 | 2015-11-11 | 日本電気株式会社 | メモリ制御装置、及びメモリ制御方法 |
| CN113282314B (zh) * | 2021-05-12 | 2024-04-12 | 聚融医疗科技(杭州)有限公司 | 一种超声扫描控制参数下发方法及系统 |
| US12105625B2 (en) * | 2022-01-29 | 2024-10-01 | Ceremorphic, Inc. | Programmable multi-level data access address generator |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4051551A (en) * | 1976-05-03 | 1977-09-27 | Burroughs Corporation | Multidimensional parallel access computer memory system |
| JPS6051732B2 (ja) * | 1978-08-31 | 1985-11-15 | 富士通株式会社 | デ−タ・ベ−スを有するデ−タ処理システム |
-
1986
- 1986-03-17 AU AU54860/86A patent/AU582632B2/en not_active Ceased
- 1986-03-19 CA CA000504551A patent/CA1250370A/en not_active Expired
- 1986-03-20 DE DE3650754T patent/DE3650754T2/de not_active Expired - Lifetime
- 1986-03-20 EP EP86302054A patent/EP0201174B1/en not_active Expired - Lifetime
- 1986-04-04 JP JP61078087A patent/JPH0731629B2/ja not_active Expired - Lifetime
-
1989
- 1989-05-15 AU AU34787/89A patent/AU602293B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP0201174A3 (en) | 1988-12-14 |
| AU5486086A (en) | 1986-10-09 |
| JPS61231639A (ja) | 1986-10-15 |
| JPH0731629B2 (ja) | 1995-04-10 |
| EP0201174B1 (en) | 2001-05-16 |
| EP0201174A2 (en) | 1986-11-12 |
| AU602293B2 (en) | 1990-10-04 |
| AU582632B2 (en) | 1989-04-06 |
| DE3650754T2 (de) | 2001-09-20 |
| DE3650754D1 (de) | 2001-08-02 |
| AU3478789A (en) | 1989-09-07 |
| CA1262968C (enEXAMPLES) | 1989-11-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR930006383B1 (ko) | 병렬처리방법 | |
| EP0242599A3 (en) | Method and apparatus for simulating memory arrays in a logic simulation machine | |
| DE69424370T2 (de) | Befehlscachespeicher mit Kreuzschienenschalter | |
| ES488841A1 (es) | Un sistema perfeccionado de tratamiento de datos. | |
| KR910010336A (ko) | 프로세서 및 메모리의 크로스바 링크를 갖는 멀티프로세서 시스템 및 이의 동작 방법 | |
| DE69033065D1 (de) | Mehrfachbefehlsdecoder | |
| EP0360527A3 (en) | Parallel computer system using a simd method | |
| HK82294A (en) | Programmed implementation of real-time multiresolution signal processing apparatus | |
| US5159690A (en) | Multidimensional cellular data array processing system which separately permutes stored data elements and applies transformation rules to permuted elements | |
| ES467326A1 (es) | Un controlador de linea general de canales en un sistema de tratamiento de datos. | |
| CA2146243A1 (en) | General analysis system | |
| EP0330226A3 (en) | Apparatus of and method for executing subprogram in bank switching data processing system | |
| DK170584B1 (da) | Pagineret lager til en databehandlingsenhed og fremgangsmåde til drift af denne | |
| CA1250370A (en) | METHOD AND DEVICE FOR ACCESSING A MEMORY BY TABLE TRANSFORMATIONS | |
| CA2216698A1 (en) | Method and apparatus for simultaneous shape-dependent access to picture data stored at a plurality of addresses | |
| EP0261751A3 (en) | Concurrent memory access system | |
| DE3687822T2 (de) | Vektorverarbeitungssystem. | |
| JPS56114063A (en) | Multiprocessor | |
| EP0321694A3 (en) | Method for a Data processing system using incompatible central processing unit/operating system combinations | |
| JPS56166614A (en) | Mixing console | |
| KR870001602A (ko) | 가변 페이지 rom | |
| JPS6459296A (en) | Data converter | |
| EP0380844A3 (en) | Method and means for interfacing a system control unit for a multi-processor system with the system main memory | |
| JPS6069758A (ja) | 多重ポ−トパイプライン構成プロセサ | |
| CA2003821A1 (en) | Process controller single memory chip shadowing technique |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |