CA1241753A - Analog/digital converter - Google Patents
Analog/digital converterInfo
- Publication number
- CA1241753A CA1241753A CA000480959A CA480959A CA1241753A CA 1241753 A CA1241753 A CA 1241753A CA 000480959 A CA000480959 A CA 000480959A CA 480959 A CA480959 A CA 480959A CA 1241753 A CA1241753 A CA 1241753A
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- digital
- signal
- analog
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- converter
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- 208000003251 Pruritus Diseases 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
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- 238000006243 chemical reaction Methods 0.000 description 1
- JCYWCSGERIELPG-UHFFFAOYSA-N imes Chemical class CC1=CC(C)=CC(C)=C1N1C=CN(C=2C(=CC(C)=CC=2C)C)[C]1 JCYWCSGERIELPG-UHFFFAOYSA-N 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/504—Analogue/digital converters with intermediate conversion to time interval using pulse width modulation
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- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Analog/Digital Converter Abstract of the Invention A digital integrator having a 16-bit output is followed by a first 12-bit digital/analog converter which is supplied with the output bits 1-11 and 16 of the integrator and which forms a first tracking loop with a first subtractor which forms a first dif-ference signal from the output signal, proportional to the input signal of the analog/digital converter, of a first amplifier and the output signal of the first digital/analog converter. A tracking circuit generates tracking signals for the integrator on the basis of the difference signal. To extend the dynamic range, a second 12-bit digital/analog converter is present which is supplied with bits 5-16 from the output of the integrator and which forms a second tracking loop with a second subtractor and a second amplifier, the gain factor of which is 1/16th of the gain factor of the first amplifier, to which loop a control logic switches over when the range which can be covered with the first digital/analog converter is exceeded. Switch-ing back takes place at the next zero crossing, that is to say, change of the most significant bit. The digital/analog converter is particularly suitable for processing the output signal of a current or voltage converter.
Description
The present invention relates to an analog/
digital converter.
A generic analog/digital converter is known (U.S. Patent Specification 4,296,412) in which all bits of the digital output signal are supplied to a single digital/analog converter which generates a cor-responding analog signal which is compared with a signal with is proportional with a fixed factor to the input signal.
A particular advantage of such a tracking type analog/digital converter consists in the extra-ordinarily rapid "data refresh" operationwhich occupies only one clock period under normal operating conditions.
The resolution of such an analog/digital conver-ter and thus the dynamic range with given requirementsfor the accuracy of conversion of the input signal even if the said requirements apply only to a part of the range swept by the latter, depends on the digital/analog converter used.
~0 The invention has the object of specifying a generic analog/digital converter which, compared with the known generic analog/digital converter comprising digital/analog converters of the same type, achieves a wider dynamic range but at the same time, for as ~5 long as the input signal moves within the range in which it could also be processed by the known generic analog/digital converter, converts this signal with at least the same accuracy as the latter. In this arrangement, the widening of the dynamic range should 3~ take place without loss of the rapid "data refresh"
facility.
The advantages which can be achieved by the invention can be seen especially in the fact that, if digital/analog converters of a given efficiency are used, the dynamic range can be considerably in-5~
creased as compared with known generic analog/digitalconverters without any increase in the quantisation error in the range which can be covered with known generic analog/digital converters or having to accept losses in speed.
Analog/digital converters according to the inven-tion are particularly sui-table for converting the output signal of a current or voltage converter, particularly of one which can simultaneously be used for measuring and protection purposes since it is not only the undis-turbed signal, which remains within a limited range, which can be converted with a high accuracy adequate for measuring purposes, but also high-amplitude distur-bances such as occur, for example, with short circuits, can be detected with an accuracy which is adequate at least for protection purposes.
According to the above object, from a broad aspect, the present invention provides an analog/digital converter which comprises a digital integrator, a first digital/analog converter which is supplied from the output of the digital integrator with a polarity bit, with a group of amount bits, immediately succeeding each other with respect to their significances. The group of amount bits includes the least significant amount bit. A first subtractor forms the difference between a signal proportional to the input signal of the analog/digital converter and the output signal of the first digital/analog converter. A tracking circuit is supplied with the output signal of the first subt~actor and generates a tracking signal for the digital integrator controlled by the output signal of the first subtractor for at least as long as the number formed by the group of amount bits supplied to the first digital/analog converter lies below an upper switching limit. The analog/digital converter - 2a -of the present invention is characterized in that it contains at least one further digital/analog converter which is supplied from the output of the integrator, in each case simultaneously with the polarity bit, with a group of amount bits which immediately succeed each other with respect to their significances. It is further characterized in that it contains for each further digital/analog converter one further subtractor which forms the difference between a signal proportional 1~ to the input signal of the analog/digital converter and the output signal of the further digital/analog converter. The lower limit and the upper limit of the significances of the amount bits fed to the further digital/analog converter are in each case greater than the lower limit or the upper limit of the significances of the amount bits fed to the preceding digital/analog converter. The lower limit of the significances of the amount bits fed to the further digital/analog con-verter lies in each case below the upper limit of the significances of the amount bits fed to the preceding digital/analog converter. The signal fed to a further subtractor and proportional to the input signal of the analog/digital converter differs from the signal fed to the first subtractor and proportional to the input signal by a scaling factor of 2 n 1, n being in each case equal to the lower limit of the signifi-cances of -the amount bits fed to the corresponding further digi-tal/analog converter. A control logic is provided which controls the tracking circuit as 3~ a function of the output signal of the digital inte-grator in such a manner that when the amount of the number represented by the group of the bits fed to one of the digital/analog converters reaches an upper switching limit, if necessary, a tracking signal gener-ated on the basis of the output signal of the respective ~V~ S~
- 2b -further subtractor is next fed to the integrator.
The control logic also controls the tracking circuit as a function of the output signal of a digital inte-grator in such a manner that when the amount of the number represented by the group of the bits fed to one of the further digital/analog converters reaches a lower switching limit, a tracking signal generated on the basis of the output signal of the respectively preceding subtractor is next fed to the integrator.
A tracking step induced on the basis of the output signal of one of the further subtractors differs by the inverse of the respective scaling factor, that is to say by 2n 1, from a tracking step induced on the basis of an equally large output signal of the first subtractor.
In the text which follows, the invention is explained in greater detail wi-th the aid of drawings, representing only one illustrative embodiment, and of some diagrams. In the drawings, Figure 1 shows a block diagram of an analog/
digital converter according to the invention, Figure 2 shows a detailed circuit diagram of a section of the analog/digital converter according to the invention according to Figure 1, and Figure 3 shows an illustrative variation over time of the input signal, respectively of the output signal corresponding to the input signal, of the analog/
digital converter according to the invention according to Figures 1 and 2 in analog representation and the variations over time of two bits of the output signal and other signals occurring in the analog/digital con-verter according to the invention.
In its basic configuration, the analog/digital converter shown in Figures 1 and 2 is provided with a digital integrator 1 having a 16-bit output, a first t75~
~ 2c -12-bit digital/analog converter 2a which follows inte-grator 1, a first subtractor 3a which forms a first difference signal from the output signal of a first amplifier 4a the input of which is connected to the input terminal 5 of the analog/digital converter and the output signal of the first digital/analog converter 2a an~ a tracking circuit 6 which precedes the inte-grator 1 and which is supplied with the said first difference signal. The tracking circuit contains a difference discrimina~or 7 comprising a first discriminator 8a ~hich determines ~hether the signal present at the input of the difference discriminator 7 lies bet~een a first lower limit value ~Ua and a first upper limit value +Ua and, if not, whe~her it is positive or negative. In this arrangement, the absol~te value Ua of the limit values is a little above one half of the voltage corresponding ~o a least significant bit. For temporary storage of the t~o items of information, the first discriminator 8a is follo~ed by two D-type flipflops 9, 9a which, like the in~egrator 1, are controlled by a clock generator 1~
According to the invention, the integrator 1 is follo~ed by a second 12-bit digital/analog converter 2b and a second subtracter 3b is present which forms from the output signal of a second amplifier 4b which is con-nected to the input terminal 5 and the gain factor of which is 1/lbth of the gain factor of the first amplifier 4a and from the output signal of the second digitallanalog converter 2b a second difference signal which i 5 also fed ZO to the tracking circuit 6. The digital integrator 1 is constructed as a four-stage cascade of 4~bit up/do~n coun~
ters 11a, b, c, d. The first digital/analog converter 2a is in each case supplied with the ele~en bits having signifio cances of 2 to 210 as amount bits and the polarity-determining most significant 16th bit, the second digitallanalog converter 2b is supplied with the bits having sig-nificances of 24 to 214 as amount bits and also the most significant 16th bit r The digital integrator used can also be a feedback type adder according to the prior art.
The tracking circuit 6 is provided ~ith an input selection switch 12 which can optionally apply the first or the second difference signal to the input of the dif-ference discriminator 7~
The difference discriminator 7 is also provided with two further discriminators 8b, 8c which are constructed as window discriminators and which in each case determine whether the difference signal applied to its input lies between a second lower limit value -Ub and a second upper '7S~
~, limit value +Ub or between a third lower limit ~alue ~Uc and a third upper limit value +Uc, respectiveLy.
The absolute values Ub~ Uc of the second and third limit values can be, for example~ 10-times and 15~-~imes the value of the voltage corresponding to a least signifi-cant bit, that is to say a little more than one half of the voltages corresponding to a bit having the significance of 24 and 28 The discrimina~ors 8b, c are followed by D-type flipflops 9b, c, controlled by the clock genera-1û tor 10, also for temporary storage of their outputsignals.
The difference discriminator 7 is follo~ed by a logic circuit 1~ which, of the output signals o~ the flipflops 9a~ 9b and 9c, passes only the signal having the highest priority to the integrator and inhibits all lower-priority signals, c having the highest and 9a ha~ing the~o~est priority.
The output of the tracking circuit ~ is connected to an output selection switch 14 which can apply output signals of the Log;c circuit 13 in each case optionally to the counting input of one of two successive 4-bit up/
do~n counters of the integrator 1. ~e input selection switch 12 and the output selection switch 14 are jointly controlled by a control logic 15 as a function of the out signals of the integrator 1. The control logic 15 contains a first EXOR gate 16 at the input of which the 16th and the 12th bits are present and the output of ~hich is connected to the in~erting set input of a first D-type flipflop 17 ~for example SN 74 LS 74) to the clock input of ~hich the output signal of a second EXOR gate 18 is fed to which the polarity-determining 16th bit is fed, once directly and one delayed by one clock period through a second D-type flip-flop 19, and the D-input of which is connected to ear~h.
In the text ~hich follows, the operation of the analog/digital converter according to Figures 1 and Figure
digital converter.
A generic analog/digital converter is known (U.S. Patent Specification 4,296,412) in which all bits of the digital output signal are supplied to a single digital/analog converter which generates a cor-responding analog signal which is compared with a signal with is proportional with a fixed factor to the input signal.
A particular advantage of such a tracking type analog/digital converter consists in the extra-ordinarily rapid "data refresh" operationwhich occupies only one clock period under normal operating conditions.
The resolution of such an analog/digital conver-ter and thus the dynamic range with given requirementsfor the accuracy of conversion of the input signal even if the said requirements apply only to a part of the range swept by the latter, depends on the digital/analog converter used.
~0 The invention has the object of specifying a generic analog/digital converter which, compared with the known generic analog/digital converter comprising digital/analog converters of the same type, achieves a wider dynamic range but at the same time, for as ~5 long as the input signal moves within the range in which it could also be processed by the known generic analog/digital converter, converts this signal with at least the same accuracy as the latter. In this arrangement, the widening of the dynamic range should 3~ take place without loss of the rapid "data refresh"
facility.
The advantages which can be achieved by the invention can be seen especially in the fact that, if digital/analog converters of a given efficiency are used, the dynamic range can be considerably in-5~
creased as compared with known generic analog/digitalconverters without any increase in the quantisation error in the range which can be covered with known generic analog/digital converters or having to accept losses in speed.
Analog/digital converters according to the inven-tion are particularly sui-table for converting the output signal of a current or voltage converter, particularly of one which can simultaneously be used for measuring and protection purposes since it is not only the undis-turbed signal, which remains within a limited range, which can be converted with a high accuracy adequate for measuring purposes, but also high-amplitude distur-bances such as occur, for example, with short circuits, can be detected with an accuracy which is adequate at least for protection purposes.
According to the above object, from a broad aspect, the present invention provides an analog/digital converter which comprises a digital integrator, a first digital/analog converter which is supplied from the output of the digital integrator with a polarity bit, with a group of amount bits, immediately succeeding each other with respect to their significances. The group of amount bits includes the least significant amount bit. A first subtractor forms the difference between a signal proportional to the input signal of the analog/digital converter and the output signal of the first digital/analog converter. A tracking circuit is supplied with the output signal of the first subt~actor and generates a tracking signal for the digital integrator controlled by the output signal of the first subtractor for at least as long as the number formed by the group of amount bits supplied to the first digital/analog converter lies below an upper switching limit. The analog/digital converter - 2a -of the present invention is characterized in that it contains at least one further digital/analog converter which is supplied from the output of the integrator, in each case simultaneously with the polarity bit, with a group of amount bits which immediately succeed each other with respect to their significances. It is further characterized in that it contains for each further digital/analog converter one further subtractor which forms the difference between a signal proportional 1~ to the input signal of the analog/digital converter and the output signal of the further digital/analog converter. The lower limit and the upper limit of the significances of the amount bits fed to the further digital/analog converter are in each case greater than the lower limit or the upper limit of the significances of the amount bits fed to the preceding digital/analog converter. The lower limit of the significances of the amount bits fed to the further digital/analog con-verter lies in each case below the upper limit of the significances of the amount bits fed to the preceding digital/analog converter. The signal fed to a further subtractor and proportional to the input signal of the analog/digital converter differs from the signal fed to the first subtractor and proportional to the input signal by a scaling factor of 2 n 1, n being in each case equal to the lower limit of the signifi-cances of -the amount bits fed to the corresponding further digi-tal/analog converter. A control logic is provided which controls the tracking circuit as 3~ a function of the output signal of the digital inte-grator in such a manner that when the amount of the number represented by the group of the bits fed to one of the digital/analog converters reaches an upper switching limit, if necessary, a tracking signal gener-ated on the basis of the output signal of the respective ~V~ S~
- 2b -further subtractor is next fed to the integrator.
The control logic also controls the tracking circuit as a function of the output signal of a digital inte-grator in such a manner that when the amount of the number represented by the group of the bits fed to one of the further digital/analog converters reaches a lower switching limit, a tracking signal generated on the basis of the output signal of the respectively preceding subtractor is next fed to the integrator.
A tracking step induced on the basis of the output signal of one of the further subtractors differs by the inverse of the respective scaling factor, that is to say by 2n 1, from a tracking step induced on the basis of an equally large output signal of the first subtractor.
In the text which follows, the invention is explained in greater detail wi-th the aid of drawings, representing only one illustrative embodiment, and of some diagrams. In the drawings, Figure 1 shows a block diagram of an analog/
digital converter according to the invention, Figure 2 shows a detailed circuit diagram of a section of the analog/digital converter according to the invention according to Figure 1, and Figure 3 shows an illustrative variation over time of the input signal, respectively of the output signal corresponding to the input signal, of the analog/
digital converter according to the invention according to Figures 1 and 2 in analog representation and the variations over time of two bits of the output signal and other signals occurring in the analog/digital con-verter according to the invention.
In its basic configuration, the analog/digital converter shown in Figures 1 and 2 is provided with a digital integrator 1 having a 16-bit output, a first t75~
~ 2c -12-bit digital/analog converter 2a which follows inte-grator 1, a first subtractor 3a which forms a first difference signal from the output signal of a first amplifier 4a the input of which is connected to the input terminal 5 of the analog/digital converter and the output signal of the first digital/analog converter 2a an~ a tracking circuit 6 which precedes the inte-grator 1 and which is supplied with the said first difference signal. The tracking circuit contains a difference discrimina~or 7 comprising a first discriminator 8a ~hich determines ~hether the signal present at the input of the difference discriminator 7 lies bet~een a first lower limit value ~Ua and a first upper limit value +Ua and, if not, whe~her it is positive or negative. In this arrangement, the absol~te value Ua of the limit values is a little above one half of the voltage corresponding ~o a least significant bit. For temporary storage of the t~o items of information, the first discriminator 8a is follo~ed by two D-type flipflops 9, 9a which, like the in~egrator 1, are controlled by a clock generator 1~
According to the invention, the integrator 1 is follo~ed by a second 12-bit digital/analog converter 2b and a second subtracter 3b is present which forms from the output signal of a second amplifier 4b which is con-nected to the input terminal 5 and the gain factor of which is 1/lbth of the gain factor of the first amplifier 4a and from the output signal of the second digitallanalog converter 2b a second difference signal which i 5 also fed ZO to the tracking circuit 6. The digital integrator 1 is constructed as a four-stage cascade of 4~bit up/do~n coun~
ters 11a, b, c, d. The first digital/analog converter 2a is in each case supplied with the ele~en bits having signifio cances of 2 to 210 as amount bits and the polarity-determining most significant 16th bit, the second digitallanalog converter 2b is supplied with the bits having sig-nificances of 24 to 214 as amount bits and also the most significant 16th bit r The digital integrator used can also be a feedback type adder according to the prior art.
The tracking circuit 6 is provided ~ith an input selection switch 12 which can optionally apply the first or the second difference signal to the input of the dif-ference discriminator 7~
The difference discriminator 7 is also provided with two further discriminators 8b, 8c which are constructed as window discriminators and which in each case determine whether the difference signal applied to its input lies between a second lower limit value -Ub and a second upper '7S~
~, limit value +Ub or between a third lower limit ~alue ~Uc and a third upper limit value +Uc, respectiveLy.
The absolute values Ub~ Uc of the second and third limit values can be, for example~ 10-times and 15~-~imes the value of the voltage corresponding to a least signifi-cant bit, that is to say a little more than one half of the voltages corresponding to a bit having the significance of 24 and 28 The discrimina~ors 8b, c are followed by D-type flipflops 9b, c, controlled by the clock genera-1û tor 10, also for temporary storage of their outputsignals.
The difference discriminator 7 is follo~ed by a logic circuit 1~ which, of the output signals o~ the flipflops 9a~ 9b and 9c, passes only the signal having the highest priority to the integrator and inhibits all lower-priority signals, c having the highest and 9a ha~ing the~o~est priority.
The output of the tracking circuit ~ is connected to an output selection switch 14 which can apply output signals of the Log;c circuit 13 in each case optionally to the counting input of one of two successive 4-bit up/
do~n counters of the integrator 1. ~e input selection switch 12 and the output selection switch 14 are jointly controlled by a control logic 15 as a function of the out signals of the integrator 1. The control logic 15 contains a first EXOR gate 16 at the input of which the 16th and the 12th bits are present and the output of ~hich is connected to the in~erting set input of a first D-type flipflop 17 ~for example SN 74 LS 74) to the clock input of ~hich the output signal of a second EXOR gate 18 is fed to which the polarity-determining 16th bit is fed, once directly and one delayed by one clock period through a second D-type flip-flop 19, and the D-input of which is connected to ear~h.
In the text ~hich follows, the operation of the analog/digital converter according to Figures 1 and Figure
2 will be explained in greater detail, occasionally using the assistance of Figure 3.
As long as the amount of the input signal is not ~ery large so that - an analog "û" corresponds to a binary number at the output of the in~egrator 1 at which the most significant ~6th bit is "1" and the other bi~s are "0"
- either9 with a positive input signaL, the 16th bit is "1"
and the bits from the 12th to ~he 15th bi~ are "~" or, ~i~h a negati~& input signal, the reverse is the case but in any case ~he bits from the 1Zth to ~he 15th bit differ from ~he 1Sth bit, the output signal S15 of the control logic 1~ is "û". The input selection sw;tch 12 then applies the first difference signal, formed from the output signal of the first ampli~ier 4a and that of the first digitaL/analog converter 2a, to the input of the dif~erence discriminator 7. As soon as the difference signal exceeds the first upper limit value Ua or drops below the first Lower l~imit value ~Ua, the first discriminator 8a responds and generates a counting signal which, stored in flipflop ~a at the next positive edge of the clock signal and, together w1th the polarity si~nal stored in the flipflop 9 passes as tracking signal via the logic circuit 13 and the output selection s~itch 14 as up- or down-counting signal to the first 4-bit up/down counter of the integrator 1 and at thenext negative clock edge causes a least significant bit to be added to or subtracted from~the binary number present at its outputo With a rapid change of the input signal, the difference signal can become so large that it exceeds the second upper limit value Ub or drops belo~
the second lower limit value -Ub. In this case, the second dis~riminator 8b responds and triggers a countir,g signal which is directly passed to the counting input of the second 4-bit up/down counter 11b and causes a bit having the significance of 24, corresponding to 16-times the value of a least significant bit, to be added or sub tracted. A counting signaL simultaneously triggered by the first discriminator 8a is then suppressed by the logic circuit 13. Correspondinyly, when the third discriminator 8c responds, a counting signal is fed to the counting in-put of the third 4-bit up/down counter 11c and a bit having the significance of 28, corresponding to 256-times the value of a least significant bit, is added or subtractedO
This makes it possible to reproduce the input signal even with very rapid changes~ although with a grea~er error than with slow changes but qualitatively correctly, which in the previously mentioned application of the analog/digital converter for processing the output signal of a curren~ or voltage converter, pernits the reproduction of transient disturbances which is important and also sufficien~ly qualitatively correct for protection purposes.
The second digital/analog converter 2b is in each case supplied wi~h the bits from the 5th to the 16th bit from the output of the integrator 1. These bits ~orm a binary number which corresponds to the binary number formed by all bits at the output of the integrator divided by 16, the remainder, the binary number formed by the four l;east significant bits, being omitted. Since the output si~nal of the first ampLifier 4a and that of the first digital/analog converter 2a are continuously calibrated, the output signal of the second amplifier 4b which~ of course, is in each case 1/16th of the output signal of the first amplifier 4a, and the output signal of the second digital/analog con~erter 2b are also continuousLy calibrated.
If then the amount of the input signal reaches an upper s~itching limit U~ at which th~12th bit B12 of the output signal, tracking the input signal, of ~he inte-grator 1 assumes a value uhich is equal to that of the 16th bit B16, if, for example, the output signal S~ -sho~n in analog form in Figure 3 - drops below -U+ so that the 12th bit ~12 at the output of the integrator 1 assumes the value "0", the range covered with the first digital/analog converter 2a is exceeded. The output signal S16 of the first EXOR gate 1~ changes to "0" and, fed to the inverting set input of the settable first D-type flip-flop 17 causes the output signal of the latter, which is simùltaneously the output signal S15 of the control logic 15, to be set to "1". The input selection switch 12 applies the second difference signal to the input of the difference discriminator 7. Simultaneously~ the output selection s~itch 14 is also switched over so that the counting signals coming from the first discriminator 8a now reach the coun-ting input of the second 4-bit up/down counter 11b and those 7~5 of the other discriminators 8b, c are also redirected to the respectively next-higher ~-bit up/down counters 11c and 11d which amounts to an enlargement of ~he ~racking steps by 16 times ~hiçh compensates the division, effected by the non-consideration of the first four bits by the second digitaL/analog converter 2b, o~ the output nurnber of the integrator 1 and the corresponding decrease in the analog signal with ~hich the divided output number is compared.
The switching described happens within one clock period without additional loss of timeO Althouyh it leads to a 16~fold increase in the quantisation error, it also has the consequence that a rapidly fluctuating input sig-nal can be tracked ~ith 16-times larger tracking steps.
Since in many applications the relative accuracy of the reproduction of the input signal is of special importance, the first factor is hardLy disadvantageous; since, on the other hand, the rates of change of the input signal occur-ring frequently correspond to the respectively occurring maximum si3nal amplitudes, the second factor is highly advantageous under certain circumstances~
During the next zero crossing~ the value of the polarity-determining 16th bit changes. Since the output signal S19 of the second D-type flipflop 19 follows it delayed by one clock period, the outpu~ signal S18 of the second E~OR gate 18 changes to "1" and retains this value for the duration of one clock period. Its positive edge causes the output signal of the first D-type flipflop 17, the D-input of which is connected to earth, that is to
As long as the amount of the input signal is not ~ery large so that - an analog "û" corresponds to a binary number at the output of the in~egrator 1 at which the most significant ~6th bit is "1" and the other bi~s are "0"
- either9 with a positive input signaL, the 16th bit is "1"
and the bits from the 12th to ~he 15th bi~ are "~" or, ~i~h a negati~& input signal, the reverse is the case but in any case ~he bits from the 1Zth to ~he 15th bit differ from ~he 1Sth bit, the output signal S15 of the control logic 1~ is "û". The input selection sw;tch 12 then applies the first difference signal, formed from the output signal of the first ampli~ier 4a and that of the first digitaL/analog converter 2a, to the input of the dif~erence discriminator 7. As soon as the difference signal exceeds the first upper limit value Ua or drops below the first Lower l~imit value ~Ua, the first discriminator 8a responds and generates a counting signal which, stored in flipflop ~a at the next positive edge of the clock signal and, together w1th the polarity si~nal stored in the flipflop 9 passes as tracking signal via the logic circuit 13 and the output selection s~itch 14 as up- or down-counting signal to the first 4-bit up/down counter of the integrator 1 and at thenext negative clock edge causes a least significant bit to be added to or subtracted from~the binary number present at its outputo With a rapid change of the input signal, the difference signal can become so large that it exceeds the second upper limit value Ub or drops belo~
the second lower limit value -Ub. In this case, the second dis~riminator 8b responds and triggers a countir,g signal which is directly passed to the counting input of the second 4-bit up/down counter 11b and causes a bit having the significance of 24, corresponding to 16-times the value of a least significant bit, to be added or sub tracted. A counting signaL simultaneously triggered by the first discriminator 8a is then suppressed by the logic circuit 13. Correspondinyly, when the third discriminator 8c responds, a counting signal is fed to the counting in-put of the third 4-bit up/down counter 11c and a bit having the significance of 28, corresponding to 256-times the value of a least significant bit, is added or subtractedO
This makes it possible to reproduce the input signal even with very rapid changes~ although with a grea~er error than with slow changes but qualitatively correctly, which in the previously mentioned application of the analog/digital converter for processing the output signal of a curren~ or voltage converter, pernits the reproduction of transient disturbances which is important and also sufficien~ly qualitatively correct for protection purposes.
The second digital/analog converter 2b is in each case supplied wi~h the bits from the 5th to the 16th bit from the output of the integrator 1. These bits ~orm a binary number which corresponds to the binary number formed by all bits at the output of the integrator divided by 16, the remainder, the binary number formed by the four l;east significant bits, being omitted. Since the output si~nal of the first ampLifier 4a and that of the first digital/analog converter 2a are continuously calibrated, the output signal of the second amplifier 4b which~ of course, is in each case 1/16th of the output signal of the first amplifier 4a, and the output signal of the second digital/analog con~erter 2b are also continuousLy calibrated.
If then the amount of the input signal reaches an upper s~itching limit U~ at which th~12th bit B12 of the output signal, tracking the input signal, of ~he inte-grator 1 assumes a value uhich is equal to that of the 16th bit B16, if, for example, the output signal S~ -sho~n in analog form in Figure 3 - drops below -U+ so that the 12th bit ~12 at the output of the integrator 1 assumes the value "0", the range covered with the first digital/analog converter 2a is exceeded. The output signal S16 of the first EXOR gate 1~ changes to "0" and, fed to the inverting set input of the settable first D-type flip-flop 17 causes the output signal of the latter, which is simùltaneously the output signal S15 of the control logic 15, to be set to "1". The input selection switch 12 applies the second difference signal to the input of the difference discriminator 7. Simultaneously~ the output selection s~itch 14 is also switched over so that the counting signals coming from the first discriminator 8a now reach the coun-ting input of the second 4-bit up/down counter 11b and those 7~5 of the other discriminators 8b, c are also redirected to the respectively next-higher ~-bit up/down counters 11c and 11d which amounts to an enlargement of ~he ~racking steps by 16 times ~hiçh compensates the division, effected by the non-consideration of the first four bits by the second digitaL/analog converter 2b, o~ the output nurnber of the integrator 1 and the corresponding decrease in the analog signal with ~hich the divided output number is compared.
The switching described happens within one clock period without additional loss of timeO Althouyh it leads to a 16~fold increase in the quantisation error, it also has the consequence that a rapidly fluctuating input sig-nal can be tracked ~ith 16-times larger tracking steps.
Since in many applications the relative accuracy of the reproduction of the input signal is of special importance, the first factor is hardLy disadvantageous; since, on the other hand, the rates of change of the input signal occur-ring frequently correspond to the respectively occurring maximum si3nal amplitudes, the second factor is highly advantageous under certain circumstances~
During the next zero crossing~ the value of the polarity-determining 16th bit changes. Since the output signal S19 of the second D-type flipflop 19 follows it delayed by one clock period, the outpu~ signal S18 of the second E~OR gate 18 changes to "1" and retains this value for the duration of one clock period. Its positive edge causes the output signal of the first D-type flipflop 17, the D-input of which is connected to earth, that is to
3~ say the output signal S15 of the control logic 15~ to be set to "~". Zero thus acts as the lower switching limit.
The input selection switch 12 and the output selec-tion switch 1~ are reset again, the difference discriminato 7 is again supplied with the output signal of the first suh~
tracter 3a. Since the first digital/analog converter 2a has been supplied for the whole time with the least significant 11 bits and the most significant 16th bit and the digital output signal has tracked the input signal with respect ~o the bits which are of higher significance than the fourth bit, the first digitaL/analog converter 2a is precalibrated, that is to say the difference betueen the output signal of the first amplifier 4a and that of the first digital/
analog converter 2a appearing at the output of the first S subtracter 3a normally has the order of magnitude, at the most, of the voltage corresponding to a bit having the significance of 24 during ~he switching.
It is obvious that the analog/digital converter described can be easily expanded to more than two s~itching stages and its dynamic range can be correspondingly further extended.
..~,~....,~ ....
~2~ 3 g List of Desi~ations 1 digital integrator 2a , b d i 9 ; tal/analog conver~er 3a,b subtracters 4a,b ampli f i ers input terminal 6 t ra cki ng ci rcui t 7 difference discriminator 8a,b,c discriminators 9,9a,b,c D-type flipflops clock generator 11a,b,c,d 4~bit up/down counters 12 input selection s~itch 1~3 logi c ci rcui t 14 output selection swi~ch control lo~ic 16, 18 EXOR gate 17, 19 D-type flipflops E input signal S1 output signal of 1 analog represent-ation U~ upper switching~ imit ~12 12th bit B1~ 16th bit S15, S16, S18~ S1g output signals of 15, 1~, 18, 19
The input selection switch 12 and the output selec-tion switch 1~ are reset again, the difference discriminato 7 is again supplied with the output signal of the first suh~
tracter 3a. Since the first digital/analog converter 2a has been supplied for the whole time with the least significant 11 bits and the most significant 16th bit and the digital output signal has tracked the input signal with respect ~o the bits which are of higher significance than the fourth bit, the first digitaL/analog converter 2a is precalibrated, that is to say the difference betueen the output signal of the first amplifier 4a and that of the first digital/
analog converter 2a appearing at the output of the first S subtracter 3a normally has the order of magnitude, at the most, of the voltage corresponding to a bit having the significance of 24 during ~he switching.
It is obvious that the analog/digital converter described can be easily expanded to more than two s~itching stages and its dynamic range can be correspondingly further extended.
..~,~....,~ ....
~2~ 3 g List of Desi~ations 1 digital integrator 2a , b d i 9 ; tal/analog conver~er 3a,b subtracters 4a,b ampli f i ers input terminal 6 t ra cki ng ci rcui t 7 difference discriminator 8a,b,c discriminators 9,9a,b,c D-type flipflops clock generator 11a,b,c,d 4~bit up/down counters 12 input selection s~itch 1~3 logi c ci rcui t 14 output selection swi~ch control lo~ic 16, 18 EXOR gate 17, 19 D-type flipflops E input signal S1 output signal of 1 analog represent-ation U~ upper switching~ imit ~12 12th bit B1~ 16th bit S15, S16, S18~ S1g output signals of 15, 1~, 18, 19
Claims (2)
1. Analog/digital converter comprising a digital integrator (1), a first digital/analog converter (2a) which is supplied from the output of the digital integrator in each case together with a polarity bit (B16), with a group of amount bits, immediately succeeding each other with respect to their significances, which group includes the least significant amount bit, a first sub tracter (3a) which forms the difference between a signal proportional to the input signal of the analog/digital converter and the output signal of the first digital/analog converter (2a) and a tracking circuit (6) which is supplied with the output signal of the first subtracter (3a) and generates the tracking signals for the digital integrator (1), controlled by the output signal of the first sub-tracter (3a) for at least as long as the number formed by the group of amount bits supplied to the first digital analog converter (2a) Lies below an upper switching limit (U+), characterised in that the analog/digital converter - contains at least one further digital/analog converter (2b) which is supplied from the output of the integrator (1), in each case simultaneously with the polarity bit, with a group of amount bits which immediately succeeded each other with respect to their significances, - contains for each further digital/analog converter one further subtracter (3b) which forms the difference between a signal proportional to the input signal of the analog/
digital converter and the output signal of the further digital/analog converter (2b), in which arrangement - the lower limit and the upper limit of the significances of the amount bits fed to a further digital/analog converter (2b) are in each case greater than the lower limit or the upper limit of the significances of the amount bits fed to the preceding digital/analog converter (2a), - the lower limit of the significances of the amount bits fed to a further digital/analog converter (2b) lies in each case below the upper limit of the significances of the amount bits fed to the preceding digital/analog converter (2a), - the signal fed to a further subtracter (3b) and pro-portional to the input signal of the analog/digital converter differs from the signal fed to the first sub-tracter (3a) and proportional to the input signal by a scaling factor of 2-n+1, n being in each case equal to the lower limit of the significances of the amount bits fed to the corresponding further digital/analog converter (2b), that furthermore, a control logic (15) is provided which controls the tracking circuit (6) as a function of the output signal of the digital integrator (1) in such a manner that - when the amount of the number represented by the group of the bits fed to one of the digital/analog converters 2a) reaches an upper switching limit (U+), if necessary a tracking signal generated on the basis of the output sig-nal of the respective further subtracter (3b) is next fed to the integrator (1), - when the amount of the number represented by the group of the bits fed to one of the further digital/analog con-verters (2b) reaches a lower switching limit, a tracking signal generated on the basis of the output signal of the respectively preceding subtracter (3a) is next fed to the integrator (1), in which arrangement a tracking step induced on the basis of the output signal of one of the further subtracters (3b) differs by the inverse of the respective scaling factor, that is to say by 2n-1, from a tracking step induced on the basis of an equally large output signal of the first subtracter (3a).
digital converter and the output signal of the further digital/analog converter (2b), in which arrangement - the lower limit and the upper limit of the significances of the amount bits fed to a further digital/analog converter (2b) are in each case greater than the lower limit or the upper limit of the significances of the amount bits fed to the preceding digital/analog converter (2a), - the lower limit of the significances of the amount bits fed to a further digital/analog converter (2b) lies in each case below the upper limit of the significances of the amount bits fed to the preceding digital/analog converter (2a), - the signal fed to a further subtracter (3b) and pro-portional to the input signal of the analog/digital converter differs from the signal fed to the first sub-tracter (3a) and proportional to the input signal by a scaling factor of 2-n+1, n being in each case equal to the lower limit of the significances of the amount bits fed to the corresponding further digital/analog converter (2b), that furthermore, a control logic (15) is provided which controls the tracking circuit (6) as a function of the output signal of the digital integrator (1) in such a manner that - when the amount of the number represented by the group of the bits fed to one of the digital/analog converters 2a) reaches an upper switching limit (U+), if necessary a tracking signal generated on the basis of the output sig-nal of the respective further subtracter (3b) is next fed to the integrator (1), - when the amount of the number represented by the group of the bits fed to one of the further digital/analog con-verters (2b) reaches a lower switching limit, a tracking signal generated on the basis of the output signal of the respectively preceding subtracter (3a) is next fed to the integrator (1), in which arrangement a tracking step induced on the basis of the output signal of one of the further subtracters (3b) differs by the inverse of the respective scaling factor, that is to say by 2n-1, from a tracking step induced on the basis of an equally large output signal of the first subtracter (3a).
2. Analog/digital converter according to claim 1, the tracking circuit of which contains a difference discrimi-nator (7) which is in each case supplied with one of the output signals of the subtracters (3a, 3b) and which - contains a first discriminator (8a) which compares the signal fed to the difference discriminator (7) with a posi-tive first upper limit value (Ua) and with a negative first lower limit value (-Ua) and - if the signal exceeds the first upper limit value (Ua) and drops below the first lower limit value (-Ua) generates in each case a corresponding tracking signal for incrementing or decrementing the number present at the output of the digital integrator (1), characterised in that the difference discriminator (4) - contains at least one further discriminator (8b, 8c) which compares the signal fed to the difference discriminator (7) with a further upper limit value (Ub; Uc) and with a further lower limit value (-Ub; -Uc), and - if the signal exceeds the further upper limit value (Ub; Uc) and drops below the further lower limit value (-Ub; -Uc) generates in each case a corresponding tracking signal for incrementing or decrementing the num-ber present at the output of the digital integrator (1), in which arrangement - the absolute value of a further upper limit value and a further lower limit value are in each case greater than the preceding upper limit value or the preceding lower limit value, - the absolute value of the number, by which the number present at the output of the digital integrator (1) is incremented or decremented because of the response of a further discriminator (8b; 8c), is greater in each case than the number added or subtracted because of the response of the preceding discriminator (8a; 8b).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH2378/84-4 | 1984-05-15 | ||
| CH237884 | 1984-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1241753A true CA1241753A (en) | 1988-09-06 |
Family
ID=4232378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000480959A Expired CA1241753A (en) | 1984-05-15 | 1985-05-07 | Analog/digital converter |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4590459A (en) |
| EP (1) | EP0162314A1 (en) |
| JP (1) | JPS60260230A (en) |
| CA (1) | CA1241753A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2543177B2 (en) * | 1989-03-24 | 1996-10-16 | 松下電器産業株式会社 | Clamping device and automatic gain control device |
| US6044162A (en) * | 1996-12-20 | 2000-03-28 | Sonic Innovations, Inc. | Digital hearing aid using differential signal representations |
| US5995036A (en) * | 1998-03-17 | 1999-11-30 | Sonic Innovations, Inc. | Passive switched capacitor delta analog-to-digital converter with programmable gain control |
| US6163287A (en) * | 1999-04-05 | 2000-12-19 | Sonic Innovations, Inc. | Hybrid low-pass sigma-delta modulator |
| US6445321B2 (en) | 1999-04-05 | 2002-09-03 | Sonic Innovations, Inc. | Hybrid low-pass sigma-delta modulator |
| US6408318B1 (en) | 1999-04-05 | 2002-06-18 | Xiaoling Fang | Multiple stage decimation filter |
| JP4178702B2 (en) * | 1999-12-28 | 2008-11-12 | ソニー株式会社 | Differential amplifier, comparator, and A / D converter |
| US6313773B1 (en) | 2000-01-26 | 2001-11-06 | Sonic Innovations, Inc. | Multiplierless interpolator for a delta-sigma digital to analog converter |
| WO2002019532A2 (en) * | 2000-08-31 | 2002-03-07 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. | Method and device for converting an analog input signal into a sequence of digital output values |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3786491A (en) * | 1972-07-05 | 1974-01-15 | Westinghouse Electric Corp | Digital integration apparatus and method |
| US3866131A (en) * | 1973-08-20 | 1975-02-11 | Coulter Electronics | Integerator system of wide range and pump circuit therefor |
| US4193066A (en) * | 1978-04-20 | 1980-03-11 | The United States Of America As Represented By The Secretary Of The Air Force | Automatic bias adjustment circuit for a successive ranged analog/digital converter |
| CH640379A5 (en) * | 1978-12-01 | 1983-12-30 | Bbc Brown Boveri & Cie | METHOD AND DEVICE FOR TRANSMITTING SIGNALS. |
| JPS5873231A (en) * | 1981-10-27 | 1983-05-02 | Shimadzu Corp | Analog-to-digital converter |
-
1985
- 1985-04-23 EP EP85104925A patent/EP0162314A1/en not_active Withdrawn
- 1985-05-07 CA CA000480959A patent/CA1241753A/en not_active Expired
- 1985-05-14 US US06/733,878 patent/US4590459A/en not_active Expired - Fee Related
- 1985-05-15 JP JP60101660A patent/JPS60260230A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US4590459A (en) | 1986-05-20 |
| JPS60260230A (en) | 1985-12-23 |
| EP0162314A1 (en) | 1985-11-27 |
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