WO2002019532A2

WO2002019532A2 - Method and device for converting an analog input signal into a sequence of digital output values

Info

Publication number: WO2002019532A2
Application number: PCT/EP2001/009750
Authority: WO
Inventors: Elmar Herzer; Hans-Peter Hohe
Original assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V.
Priority date: 2000-08-31
Filing date: 2001-08-23
Publication date: 2002-03-07
Also published as: AU2001282120A1; WO2002019532A3

Abstract

A method for converting an analog input signal (α) into a sequence of digital output values (θn) uses the formation of a first differential value (ϵ) between the current output value and the analog input signal (α). The method also provides for a check to determine whether the amount of the first differential value (ϵ) exceeds a predetermined amount (S). Should the amount of the first differential value (ϵ) exceed the predetermined amount, the method provides that the digital output value (θn) is re-adjusted using a certain adjustment value. Should the amount of the first differential value (ϵ) not exceed the predetermined amount, the method provides that a second differential value (δ) between the first difference (ϵ) and an integral value (Σ) consisting of the sum of first differential values (ϵ) occurring since the checking stage showed throughout that the amount of the first differential value (ϵ) does not exceed the predetermined amount is formed; and that the second differential value (δ) is compared with a predetermined threshold value and the digital output value (qn) is incremented or decremented according to the result of this comparison.

Description

Method and device for converting an analog input signal into a sequence of digital output values

description

The present invention relates to the conversion of an analog input signal into digital output values and in particular to the analog / digital conversion of position sensor signals when positioning machine tools.

Linear differential transformers (LVDT = Linear Variable Differential Transformer) or rotary differential transformers (RVDT = Rotational Variable Differential Transformer), which are called encoders or resolvers, or a special arrangement magnetoresistive, are used to measure a path or a rotation angle α in mechanical arrangements or machines Resistors or Hall sensors are used. These sensors deliver two output signals that vary depending on the mechanical position, so that the position can be determined from the signals.

Figure la and Figure lc show, for example, two different arrangements for measuring the linear position, while Figure lb shows an arrangement for measuring an angle of rotation.

Figure la shows an excitation coil 10 and two measuring coils 20 and 30 and a measurement object 40 with suitable material properties, such as a suitable magnetic susceptibility, which is arranged between the excitation coil 10 on one side and the measuring coils 20 and 30 on the other side , and is linearly movable along an axis 50. The arrangement is designed in such a way that a linear displacement Movement of the measurement object 40 or the excitation coil 10 causes a change in the coupling ratios between the excitation coil 10 and the measuring coil 20 and between the excitation coil 10 and the measuring coil 30. An excitation voltage on the excitation coil 10 therefore causes signals on the measuring coils 20 and 30 which are in quadrature with one another. The position of the measurement object 40 can be defined as an angle α, which determines the relationship between the two measurement signals, as will be explained in the following.

The arrangement shown in FIG. 1b corresponds to the arrangement shown in FIG. 1a except for the measurement object 40. In this case, the measurement object is formed by a rotatable body 50. By rotating the body 50, as in the arrangement in FIG. 1 a, the ratio between the measurement signals detected in the measuring coils 20 and 30 changes as a function of the angle of rotation α, as a result of which the angle of rotation α can be determined.

FIG. 1c shows an alternative arrangement to FIG. La with magnetoresistive sensors 60 and 70, a magnetic scale 80 serving as the linearly displaceable measurement object. The magnetic scale 80 has two suitably aligned magnetic areas, each of which generates opposite magnetic fields at the location of the magnetoresistive sensors 60 and 70, these areas being represented in FIG. 1c by four bar magnets 80a, 80b, 80c and 80d oriented in alternating directions , Moving the scale 80 along an axis 90 changes the magnetic field at the location of the magnetoresistive sensors 60 and 70 and thus the electrical resistance such that signals are measured at the sensors 60 and 70 which are in quadrature with one another. Consequently, the variation of these signals is characterized in that they are essentially quadrature with one another. 2 shows the relationship between the value α on the one hand and the measurement signals on the measuring coil 20 or the magnetoresistive sensor 60 (Usin) and on the measuring coil 30 or the magnetoresistive sensor 70 (Ucos) on the other hand as a function of an excitation voltage U ₀ . The following relationships between the excitation voltage U ₀ , the measured value, such as the angle of rotation, and the measurement signals Usin and Ucos result from FIG.

Usin = U ₀ sin (α)

Ucos = Uo cos (α)

Here U ₀ can be any DC or AC voltage and the general form of

U ₀ = ∑ Ui cos (ωt-i + ψi) i = 0

have, where Ui amplitudes, ψi the associated phases at time t = 0 and ω are the carrier frequency.

Since almost all controls and regulations of mechanical systems are increasingly digitally implemented, the analog output signals of the sensors must be digitized before they can be processed to control the machines. To determine a digital equivalence of the position Θ = o-di _g , the ratio of Usin to Ucos must be evaluated, whereby in general My following relationship between the angle of rotation α and the measurement signals Usin and Ucos applies:

U sin a = arctan

Ucos

An evaluation of the measurement signals must therefore be independent of the variation in U ₀ . Several methods for digitizing the measured value α are known from the prior art. In the systems with separate digitization, both measuring voltages Ucos and Usin are digitized separately, and the digital output value αdig is then digitally calculated.

Fig. 3 shows the block diagram of a device with separate digitization. The input signals Usin and Ucos are fed in at two channel inputs 100 and 110, respectively. Both inputs 100 and 110 are connected to series-connected low-pass filters 120 and 130 and analog / digital converters 140 and 150, which are connected in series. The low-pass filters 120 and 130 are connected upstream of the analog-digital converters 140 and 150 in order to comply with the Nyquist criterion when scanning within the converters _140 and 150. The demodulation of the digitized signals generated in this way is carried out by means of a multiplication 160 or 170 with a carrier frequency signal fed in at an input 180. The calculation of Θ by calculating the arctangent is done digitally in a computer block 190. The low-pass filters 120 and 130 and the analog-digital converters 140 and 150 must consequently be designed for processing signals with a carrier frequency, which means an increased outlay. A digital filter 200 is connected behind block 190 to effect interference suppression. All elements of the circuit shown in Fig. 3 are integrated monolithically or hybrid in a module. A disadvantage of this method is that the resolution and the conversion time cannot be set dynamically. In the event that a noise signal is superimposed on the input signal that is larger than the least significant bit, the resolution can be increased by Ni bits in the digital filter by averaging over 2 ^2Nl values. This is called dithering and results in an increase in the resolution proportional to the root of the averaged time period. The theoretical physical limit for measuring accuracy is characterized by a constant product of resolution and averaging time and is above all at higher resolutions, far from the results of this method.

Other methods known in the art evaluate the measurement signals according to a tracking method with a counter and various types of feedback. Implementers of this type are used, for example, in the assemblies of the company Data Device Cooperation (DDC) with the business address 105 Bill Ba Place, Bohemia, New York 11716-2482, from the company Analog Devices INC. with the business address one signality way, poBox. 9196, Northwest MA 02Ö62 - 9196, the company NAI and the company iC-House.

The tracking process is based on the tracking of the digital value Θ with the help of a control loop. The feedback error signal required is calculated by non-linear analog circuits.

FIG. 4 shows a conventional converter using the post-processing method, which is produced by iC-House, with a sine / digital converter. 4 comprises two inputs 200 and 210 to which the demodulated signals A x sin () and A x cos (α) are applied. The two inputs 200 and 210 are directly connected to two inputs of a switching device 240 via an inverter 220 and 230, respectively. The switching device 240 receives segment control information at an input 245, which will be explained in the following, and in accordance with this information either routes the non-inverted or inverted input signal of the input 200 to the non-inverting input of a comparator 250 or either the non-inverted or inverted input signal of the input 210 to a multiplier 260. The output of multiplier 260 is connected to the inverting input of comparator 250. The output of the comparator 250 is connected to an up / down counter 270, which receives information about the resolution to be achieved or signals for controlling hysteresis effects and a clock signal via three inputs 280, 290 and 295. The output of the up / down counter 270 is connected to the converter output 300 and in a feedback loop to the input of a digital / analog converter 310. The output of the digital / analog converter 310 is connected to an input of a calculation device 320 for calculating the tangent or the cotangent, the selection of the function on which the calculation is based being controlled via an input 330 by the segment control information. The output of the calculation device 320 is connected to a further input of the multiplier 260.

The mode of operation of the converter of FIG. Four will now be described. The digital conversion result or the current output value Θ is stored in the up / down counter 270 and is converted into an analog via the digital / analog converter 310 Voltage converted. This is multiplied by one of the two output signals of the switching device 240, the product being compared by the comparator 250 with the analog output signal. The output of the comparator 250 leads to the direction input of the counter 270. The counting direction for each clock signal 295 is maintained by the counter until the output voltage of the digital / analog converter 310 proportional to the output value corresponds to the value α of the input voltages.

In contrast to conventional analog / digital converters, the output value of the sine / digital converter is not proportional to the input voltage, but rather to its phase α. The phase is available at inputs 200 and 210 in the form of A x sin (α) and A x cos (α). The tangent function is formed from the initial value Θ in the feedback along the feedback loop, and the result is multiplied by cos (α). The end result is compared to sin (α). The following relationship is therefore obtained as a regulation for the regulation:

A sin (α) = A cos () tan (Θ)

Since the tangent function has pole positions and cannot be formed over a full period, a period is divided into eight segments. For certain segments, the input signals at inputs 200 and 210 are exchanged by the segment control, and the cotangent function is formed in the feedback instead of the tangent function. The sine-digital converter runs automatically on the shortest path into the segment and has therefore reached its operating point after a maximum of n / 2 clock cycles with a static input signal, where n corresponds to the resolution. The demodulation of possibly With the converter, th signals can be implemented by carrier-synchronous reversal of the segment control.

A disadvantage of the converter described above is that the resolution is determined internally by the number of counting steps and cannot be changed dynamically. In addition, the converter shown in FIG. 4 never comes to rest, since the counter continuously counts up or down the least significant bit of the output value even with a constant input signal, which must be prevented by hysteresis control. For this purpose, an area is spanned on both sides of the counter value and checked within two clock periods whether the input signal is still within this area. The output frequency is consequently only half of the clock frequency, and an additional circuit is necessary to prevent the output value from fluctuating with an otherwise constant input signal.

5 shows the block diagram of a further conventional converter according to the tracking method. This ratiometric converter is used, for example, in the modules of the RDC 19200 series from DDC or AD2S44 from ANALOG DEVICES. 5 shows, this converter comprises two inputs 400 and 410, at which the input signals Usin and Ucos are present. The two inputs 400 and 410 are connected to a device 420 for sin / cos multiplication and addition. Device 420 outputs an alternating signal error ε to an output 430 and to an input of a phase-sensitive demodulator (PSD) 440. The PSD also receives a signal at the carrier frequency via an input 450. The PSD 440 outputs a DC signal error E at an output 460 and at the input of an integrator 470. The integrator gives an integrated 480 and an input of a VCO 490 an error signal. The VCO 490 outputs clock signals clk and direction information to a counter 520 via two lines 500 and 510. The counter 520 is connected to the digital output 530 of the converter and to a further input of the device 420.

The operation of the converter of Fig. 5 will now be explained. First, the input signals to the

Inputs 400 and 410 are multiplied by device 420 by sin (Θ) and cos (Θ), and the results are then subtracted from one another. After demodulation by the PSD 440, an error signal E results which is proportional to (α-Θ) for small deviations from (α-Θ).

E = sin (α) cos (Θ) - cos (α) sin (Θ) = sin (α-Θ) «α-Θ

This signal E is integrated at least once, as a result of which a signal V (velocity) is obtained which is supposed to be proportional to the speed. Depending on the size and sign of V, the VCO controls the counter at the appropriate speed, forwards or backwards. By using the integrator, the conversion process suppresses interference. Typically, the blocks are all integrated into a hybrid module or an IC (IC = Integrated Circuit), although connections 540 and 550 to the outputs 560 and 580 must be arranged outside the module so that the control properties can be influenced.

A disadvantage of the circuit shown in FIG. 5 is that its behavior essentially depends on the external structure and the circuitry. In addition, the resolution is determined internally by the width of the counter word and can therefore be used during the Operating cannot be changed dynamically. In principle, it would be possible to adapt the resolution by means of a variable subsequent filter. For reasons of stability, however, the integration time of the analog integrator in practical use is longer than the averaging time of the digital filter. A shortening of the digital integration time does not lead to a higher dynamic with reduced resolution.

WO 93/22622 describes an interpolating converter which is used in module AD598 from ANALOG DEVICES. This converter converts LVDT signals into PWM-encoded digital signals. Instead of arctan (x) formation, only a quotient formation is carried out. This is done by linearly multiplying the input signals by the PWM signal. In principle, this converter is a single-bit sigma-delta converter with special single-bit feedback on the two input signals. However, this converter can only approximately evaluate resolver signals, since the sinusoidal shape of the modulation is not taken into account.

The following problems arise with the converter methods described above and known in the prior art: - ^!

The drives of modern machine tools are getting faster and faster and should position themselves more and more precisely. In order to be able to process the ever increasing speeds (in the case of resolvers) or higher linear speeds with fixed resolution, the carrier frequency and the input bandwidth of the evaluation circuits must become ever higher. This requires an ever faster regulation in the post-processing method or ever higher sampling rates of the analog / digital converter in the separate digitization, which in turn is high It places demands on the subsequent control electronics, which can only process the many, quickly generated position information with great effort.

If the loop control of a follower converter is high, the control system can also become slightly unstable. Multi-integrating systems, which are characterized by small static control deviations, are particularly susceptible in this regard. This also affects the user of the circuit, since it becomes difficult to integrate the converter module in a functioning system. In addition, the susceptibility to electromagnetic interference from other assemblies increases.

Therefore, although it would be desirable to monolithically integrate the entire converter system, the effort involved in the conventional methods is either very high or even impossible.

With ratiometric methods, integration is opposed, for example, to the offset of the integrator, the PSD and the VCO, which can lead to distortion or unstable behavior. In addition, the time constants of the VCO show a high degree of variation, and the PSD causes interference coupling and distortion. Another disadvantage is that the resolution depends on the multipliers used or the multiplying DACs and can hardly be reduced dynamically in favor of the speed. In addition, the counter always counts plus or minus one step of the maximum resolution and thus specifies the maximum speed da / dt, which means that the maximum conversion speed of the multiplying DAC cannot usually be fully utilized. In the case of the previously mentioned method of separate digitization, the integration arises with the problem that the chip area requirement for "long" digital filters and the exact arctan (x) calculation is large. It is also disadvantageous that the resolution depends on the resolution of the ADCs and is usually fixed.

EP0158841 AI describes an analog-to-digital converter in which a first discriminator compares the input voltage with the output voltage of a digital-to-analog converter connected downstream of a digital integrator and causes the digital integrator to count up or down by a least significant bit, if the input voltage is lower or higher by more than about half the voltage corresponding to a least significant bit. To improve the tracking, additional window discriminators are provided, which enable faster output signal feedback with rapid fluctuations in the input voltage.

DE 19540106 C2 describes a control unit for an electric motor with a position sensor with an analog output signal. An analog-digital converter is connected downstream of the position sensor, which in turn is followed by a computing circuit for determining position values. A correction formwork is provided in order to correct the time delay in the calculation of the position value.

EP 0169535 A2 describes an analog / digital converter in which a voltage generated by a built-in D / A converter is successively subtracted from an analog input signal and the digital code of the built-in D / A converter is derived as the digital output signal when between the voltage generated by the D / A converter and the ana- the input signal is determined by a comparator. The output of the comparator is fed back to be superimposed on the subtracted result and to be used to control the D / A converter.

UK 2242583 A describes a double reference angle encoder / digital converter in which a cosine and sine encoder signal is multiplied by an internal digital sine or cosine signal in a DAW, and the output signals are fed to an error amplifier, which generates an error signal which is digitized by a converter and demodulated by the encoder using a digitized reference signal. The output signal is demodulated in the demodulator and fed to a binary accumulator via a digital filter. The accumulator output signal is first used by a cosine look-up table to generate the cosine input signal for the DAW via a modulator, and secondly by a sine look-up table to generate the sine input signal for the DAW via a further modulator. The demudulator and modulators are connected to an internal digital reference synthesizer.

/

The object of the present invention is to provide a method and a device for converting an analog input signal in a sequence of digital output values, so that the dynamic properties of the conversion are improved and nevertheless high for static input signals

Resolutions can be achieved.

This object is achieved by a method according to claim 1 and an apparatus according to claim 9. The method according to the invention for converting an analog input signal into a sequence of digital output values comprises forming a first difference value between the current output value and the analog input signal. The method further includes checking whether the amount of the first difference value exceeds a predetermined amount, and if the amount of the first difference value exceeds the predetermined amount, the digital output value is readjusted using a specific control value. If the amount of the first difference value does not exceed the predetermined amount, forming a second difference value between the first difference and an integration value consisting of the sum of the negated first difference values since the check in the step of checking continuously revealed that the amount of the first difference value does not exceed the predetermined amount, comparing the second difference value with a predetermined threshold value and incrementing or decrementing the digital output value depending on the result of the comparison.

The device according to the invention for converting an analog input signal into a sequence of digital output values comprises a device for forming a first difference value between the current digital output value and the analog input signal and a device for checking whether the amount of the first difference value exceeds a predetermined amount. A device is provided for readjusting the digital output value using a predetermined control value if the amount of the first difference value exceeds the predetermined amount. The device further comprises means for forming a second difference value between the first difference value and one Integration value consisting of the sum of the first difference values since the means for checking continuously determined that the amount of the first difference value does not exceed the predetermined amount, for comparing the second difference value with a predetermined threshold value and for incrementing or decrementing the digital one Initial value depending on the result of the comparison if the amount of the first difference does not exceed the predetermined amount.

The present invention takes into account the knowledge that mechanical systems are subject to mechanical inertia, so that when a machine moves quickly, an evaluation of the current position of the machine with full resolution is not necessary. Only when the movement is relatively slow, when the machine has almost reached its destination, is the more precise position interesting. Here, the term "slow down" is to be understood relative to the electronic processing speed, in that a machine only needs a few milliseconds to slow down and a human observer describes this process as "stopping", ■. for integrated electronic systems but a few milliseconds mean a "long time".

In one exemplary embodiment according to the present invention, the readjustment of the output value, ie the rough quantization, is carried out by adding or subtracting a plurality of counter values to or from the current output value depending on the sign of the first difference value until the output value receives the input signal crosses or exceeds. After the output value has been adjusted or if the deviation of the current digital output When the input value is small from the value of the input signal, a fine quantization is carried out, in which it is checked whether the second difference value has crossed the threshold value and, if this is the case, the direction in which the second difference value has crossed the threshold value is determined , whereupon the current digital output value is incremented or decremented depending on the specific direction. In the case of a constant input signal, the resulting sequence of output values oscillates around the two digital values closest to the constant input signal. From the frequency of the occurrence of the values, subsequent averaging with respect to a variable number of successive output values of the sequence of output values enables a higher resolution to be achieved, for example when the machine approaches its target position and the output rate can consequently be lower. The averaging duration and thus the dead time of the control system can be set to a current travel speed or to a suitable output rate for the sequence of output values via the number of digital output values used for averaging.

According to a ^" special exemplary embodiment, the present invention is applied to signals which are quadrature with respect to one another, as arise when LVDTs and RVDTs or arrangements with magnetoresistive resistors or Hall sensors are used. This is a 4-quadrant adder which consists of two multiplying DACs and an adder are used to obtain the first difference value from the signals which are quadrature with respect to one another. The present invention is therefore suitable for processing a pair of signals of the same frequency and for determining a digitally represented value from the instantaneous amplitude, the one in the eye represented by a sensor. During digitization, the phase of the carrier contained in the input signals can be taken into account, as a result of which conversion and demodulation are carried out simultaneously.

An advantage of the present invention is that an integration of a converter according to the present invention is easier to implement than with the converters known in the prior art. In particular, integration into a standard CMOS technology is possible. The reason for this is that the subsequent linear interpolation between the output values can achieve a higher resolution than the resolution of the multiplying DACs of the 4-quadrant multiplier, which reduces the area required for the multipliers used and makes them faster , In addition, three comparators take over the task of the VCOs used in conventional converters, which are difficult to reproduce to integrate, and the lack of a PSD eliminates interference, signal distortions, increased chip area consumption, offset problems, etc., as occur in the prior art , so that less critical components have to be used overall.

Another advantage of the present invention is that better dynamic properties can be achieved with a high static resolution. Consequently, very fast machine controls can also be implemented digitally using the method or the device of the present invention. In particular, the resolution of the sequence of digital output values, as required in practice, depends on the dynamics of the input signal, with rapidly changing input signals being sampled at a high rate but with a low resolution, for example with a step size which is a multiple times the total resolution, and slowly changing input signals are sampled with high resolution.

Another advantage of the present invention is the speed and stability of the tracking of the digital output value, since the sequence of output values can react more quickly to a large change in the input signal and still has hardly any overshoot. The interference suppression and the elimination of the control deviation using the integration value are retained. In addition, the integration value sums up all previous conversion errors and consequently enables the subsequent interpolation of values between the values that can be set with the multiplier DACs. The resolution of a converter according to the invention can be increased by Ni bits with an interpolation filter of length 2 ^Nl .

Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the accompanying drawings:

Fig. La lb and lc schematic representations of sensor arrangements for position measurement with the generation of quadrature output signals according to the prior art;

2 shows a vector diagram to illustrate the relationship between output signals which are in quadrature with one another, an excitation signal and an angle of rotation;

3 shows a block diagram of a converter with separate digitization of the two input signals according to the prior art; 4 shows a block diagram of a converter with a sinus / digital converter according to the prior art;

5 shows a block diagram of a ratiometric converter according to the prior art;

6 shows a block diagram of a converter according to an exemplary embodiment of the present invention;

FIG. 7 is a block diagram illustrating the part of the converter of FIG. 6 that performs the rough quantization;

FIG. 8 is a block diagram of the part of the converter of FIG. 6 that carries out the fine quantization;

FIG. 9 shows a block diagram of the part of the converter from FIG. 6 that averages the sequence of output values; FIG.

Fig. 10 is a block diagram of the 4-quadrant adder of the converter shown in Fig. 6;

11a is a graph in which signal values are plotted against successive cycle steps, which occur in a first example sequence of the circuit of FIG. 6;

11b is a graph in which further signal values are plotted against successive cycle steps, which occur in the first example sequence of FIG. 11a; 11c is a graph in which signal values are plotted against successive cycle steps, which occur in a second example sequence of the circuit of FIG. 6;

FIG. 11d shows a graph in which further signal values are plotted against successive cycle steps, which occur in the second example sequence from FIG. 11c; and

12 shows a block diagram of a converter according to a special exemplary embodiment of the present invention.

6, a converter according to an embodiment of the present invention will first be described. In particular, FIG. 6 shows the block diagram of the converter, while FIGS. 7-10 show individual parts of the converter, on the basis of which the functioning of the converter of FIG. 6 is explained.

As shown in FIG. 6, the converter includes a 4-quadrant adder 610, an inverting integrator 620, an adder 630, three comparators 640, 650, 660 (H, L, I), control logic 670, an open / Down counter 680 and a customizable digital filter 690. An input of adder 610 is connected to input 700 of the converter to receive input signal α, the output of adder 610 being connected to the inputs of comparators 640 and 650 and the integrator 620 and an input of the adder 630 is connected. In addition to the output signal ε of the adder 610-, the adder 630 receives the integrated output signal Σ of the integrator 620. The output δ of the adder 630 is connected to an input of the comparator- tors 660 connected. The outputs of the comparators 640-660 are each connected to an input of the control logic 670. The control logic 670 is connected at three outputs to an input of the integrator 620, the up / down counter 680 and the adaptable digital filter 690. The output of the up / down counter 680 is connected to a further input of the adder 610 and to an input of the digital filter 690 and ^'outputs the conversion result and the current digital output value Θ _n of. The output of the adaptive filter 690 is connected to an output 710 of the converter in order to output the filtered conversion result.

After the circuit structure of the converter has been described with reference to FIG. 6, the mode of operation of the converter is explained with reference to FIGS. 7-10, it being pointed out that in FIGS. 7-10 for elements that are the same as in FIG 6 the same reference numerals are used, and an explanation of the interconnection of these elements is therefore omitted. Control logic 670 has also been omitted from FIG. 8 to simplify the illustration.

Fig. 7 shows the part of the circuit of - Fig. 6 which performs the rough quantization of the input signal α. This portion is formed by a feedback loop that includes 4-quadrant adder 610, comparators 640, 650, and 660, control logic 670, and up / down counter 680. In which

Adder 610 subtracts the current conversion result Θ _n stored in the up / down counter 680 from the analog input signal α, thereby generating an error signal ε = α - Θ _n at the output of the adder 610. The comparator 640 receives the error signal ε and checks whether the error signal ε exceeds a certain threshold value S. Corresponding The comparator 650 checks the error signal ε to determine whether it is less than the minus the threshold value S. Since the integrator 620 (FIG. 6) does not supply an output signal, the adder 630 (FIG. 6) passes on its input signal ε directly and can be omitted for this consideration. The comparator 660 checks whether the value of ε exceeds zero. Consequently, the three comparators 640, 650 and 660 cooperate in order to check whether the error signal ε lies outside a specific area surrounding the zero or whether the magnitude of the error signal ε exceeds the threshold amount and which sign ε has.

If the amount of the error signal ε exceeds the threshold amount, this means that the instantaneous digital value or the conversion result Θ _{n is} very far away from the analog input value α, with the respective comparator 640 or 650 sending a corresponding signal to the control logic 670 to effect that the instantaneous digital value, which is stored in the up / down counter 680, is adapted to the input signal α. The adaptation or readjustment of the instantaneous digital value is carried out by suitably adding or subtracting a control value, for example a certain number of counter values, the control loop operating in such a way that the current digital value is tracked until the converter result Θ _n corresponds to the analog input value α exceeds or crosses. This tracking is preferably carried out without a major time delay, for example using proportional control. For example, it can be provided that in the event that the magnitude of the error signal ε exceeds the specific threshold value, the up / down counter 680 the current digital value per control cycle by a certain amount adapted to the magnitude of the error signal ε Number of counter values increased or decreased. A lookup table could be used to determine the number of counter values depending on the error signal ε. Such an adjustment of the counter increment or the resolution takes into account the fact that machines have a mechanical inertia, so that it is not necessary to track the current digital value by individual counter values. This also enables faster machine movements to be tracked. However, it is also possible for the current digital value Θ _n in the up / down counter 680 to be tracked per cycle simply by adding or subtracting an individual counter value or incrementing or decrementing it.

It is optionally also possible not to wait until the end of the rough quantization until, _n α crosses over, but to proceed to the fine quantization immediately after the amount of ε falls below the threshold value S.

While the rough quantization described with reference to FIG. 7, the resolution of the conversion result Θ _n is limited by the digital width of the up / down counter 680, it is the case with a fine quantization that follows with reference to FIG. 8 will be described, possible by subsequent digital filtering to increase the resolution of the conversion result Θ _n . The part of the circuit of FIG. 6 that performs the fine quantization is shown in FIG. 8 and comprises in a control loop the 4-square adder 610, the inverting integrator 620, the adder 630, the comparator 660, the control logic 670 (FIG. 6 ) and 680. This section operates the up / down counter ^¬ the circuit to the fine quantization, in the case to carry out, that the actual conversion result Θ _n of the input signal α only slightly, e.g. only deviates by a maximum of 2 counter values. If this is the case, the integrator 620 is activated by the control logic 670 (FIG. 6), which is again not shown in FIG. 8 for reasons of clarity, and the fine quantization begins. If the fine quantization takes place during successive clock cycles, that is to say if the check of the error signal ε in the case of successive cycles shows that the current conversion result Θ _n differs from the input signal α by less than the determined threshold value S, the integrator 620 outputs an integration signal Σ at its output that corresponds to the integration of the inverted error signal -ε that has occurred so far since the time since the amount of the error signal ε was below the threshold amount for the last time. The adder 630 subtracts the integration value Σ from the current error signal ε and outputs the difference δ to the comparator 660. The comparator 660 compares the difference value output by the adder 630 with a comparison value and outputs the result of the comparison to the control logic 670. The control logic 670 (FIG. 6) controls the up / down counter 680 in such a way that the current digital value Θ _n is incremented by a counter value if δ is greater than the comparison value of the comparator 660, and Θ _n is otherwise decremented , As will become clear in the following, this regulation causes the conversion result Θ _n to fluctuate around the two digital values that are closest to the input signal α. The mode of operation of the fine quantization feedback is explained in more detail below with reference to Table 1. Table 1

Table 1 comprises 8 columns in which from left to right the control cycle n, the value of the input signal α in the control cycle n, the digital value Θ _n in the control cycle n, the error signal ε, the integration value Σ in the control cycle n, the difference value δ, which is output by the adder 630 in the control cycle n, the mean value of the last 1Q_ digital values Θ _n and the control action of the control logic 670 are given before and after the decision. The values of ε, Σ and δ are shown in FIG. 11a for easier illustration and in FIG. 11b the values of ^' α, Θ and the mean value of Θ are plotted over 10 steps on the y-axis, while on the x- In the example of Table 1, it is assumed that the digital resolution of the up / down counter 680 is limited to integer numbers, it is also assumed that the determined threshold value is 2 and the comparison value is 0. Therefore, the Fine quantization instead if the amount of the error signal ε is less than two is. Furthermore, it is assumed in the example of Table 1 that the input signal α is the angle of rotation of a machine and that the machine is at rest from a cycle n = -2.

In the cycles n = -2 to n = 0, the converter is in a rough quantization state, since the error signal ε = α-Θ _{n is} greater than two. In this case, the integrator is switched off, the integration value Σ is equal to zero and the difference value δ is equal to ε, since fine quantization is deactivated, and coarse quantization is activated in order to readjust the digital value Θ of the up / down counter 680 until the current digital value Θ _n the input signal exceeds α. As shown in Table 1, it is assumed that this process requires n0 = 3 cycles. In cycle 1, the current digital value Θ _n and the input signal α are close together, so that the fine quantization is carried out.

The integration value Σ is initialized to the value 0 by the control logic 670. The difference value δ generated by the adder 630 results in -0.3. Comparator 660 determines that this value is less than its comparison value. The control logic 670 decides that the counter 680 now decrements Θ to the value 14 ". When Um is switched, the ε and δ change abruptly to the value 0.7. Since the fine quantization begins here, the control logic 670 now gives the inverting integrator 620 The integrator time constant in this example is chosen such that Σ changes by ε after a step with the constant signal ε at the input of the integrator 620. By step n = 2, the integrator signal Σ has dropped to - 0.7 and the difference signal δ has risen to 1.4. Comparator 660 determines that the value of δ is now greater than its comparison value. The control logic 670 decides that the counter 680 Θ must increment to the value 15. When switching Θ, ε and δ change abruptly to the values -0.3 and 0.4.

Since ε is negative, the integrator signal Σ rises again and reaches the value -0.4 until step n = 3. δ has thus dropped to 0.1. Nevertheless, δ is still greater than the comparison value of the comparator 660. The control logic 670 decides that the counter 680 has to increment Θ again. Θ receives the value 16. When Um is switched, ε and δ change abruptly to the values -1.3 and -0.9.

Up to step n = 4, the integrator signal Σ continues to rise, up to the value 0.9. δ thus drops to -2.2 and is then smaller than the comparative value of the comparator 660. Θ is decremented to the value 15 and ε and δ jump to -0.3 and -1.2, respectively.

Up to the step n = 5, the integrator signal Σ continues to rise up to the value 1.2. δ thus drops to -1.5 and is again smaller than the comparative value of the comparator 660. Θ is decremented to the value 14 and ε and δ jump to 0.7 and -0.5, respectively.

Up to step n = 6, the integrator signal Σ falls again, down to the value 0.5. δ thus rises to 0.2 and is larger than that

Comparative value of the comparator 660. Θ is set to the value 15 incremented and the signals ε and δ jump to -0.3 and - 0.8, respectively.

The integrator signal Σ rises up to step n = 7, up to the value 0.8. δ thus drops to -1.1 and is then smaller than the comparative value of the comparator 660. Θ is decremented to the value 14. ε and δ jump to 0.7 and -0.1, respectively.

Up to step n = 8, the integrator signal Σ falls again, down to the value 0.1. δ thus rises to 0.6 and is larger than the comparison value of the comparator 660. Θ is incremented to the value 15 and the signals ε and δ jump to -0.3 and - 0.4, respectively.

This continues until step n = ll, where Θ is decremented at n = 9 and incremented at n = 10.

By step n = ll, the integrator signal Σ has reached the value 0.0 again. The situation corresponds to that of step n = 1. The table shows that from step n = ll to step n = 21 the states from ^" step n = 1 to step n = ll are repeated. This cyclical behavior with the period of ten steps in which the digital output value Θ fluctuating around those digital values that are closest to the input value α continues as long as α does not change.

In other words, the error signal ε is compared with the integrator signal Σ at each step. Θ oscillates between the two nearest α values - as in the

Steps n = 5 to n = 12 visible. If ε is rather positive on average, So Θ too small on average, Σ continues to decrease until Θ increases again from größereni ₊₂ from the larger of the two values - as in step n = 13 - because Σ becomes smaller than the smaller value of ε. As a result, Θ becomes too large on average, Σ rises again and Θ oscillates back and forth between the two α closest values © i <α and Θι + 1> α.

If α lies exactly between Θi and Θι + 1, Θ only oscillates between the two values.

If α> Θi + 0.5, the value Θ _± + 2 also occurs regularly to compensate. If α <Θi + 0.5, the value Θi - 1 also occurs regularly.

Overall, this fine quantization feedback process corresponds to the functioning of a SIGMA-DELTA converter. Interpolated intermediate values can be determined from the ratio of the frequency of the occurrence of the digital values by averaging over several steps in a digital filter, as will be explained in more detail with reference to FIG. 9. .

By forming the mean value over the last 10 values of Θ Ta beauty 1, SO is obtained after a settling time of at most 10 steps after the fine quantization employed, the ge ^¬ more accurate conversion result of 14.7, as in the seventh column table is applied, as occurs within a period once the value 16, five times the value of 15, and four times the value of 14 on ^¬.

Referring to Fig. 8 and Table 1, however, it should be noted that, although in the foregoing, the comparison value of the comparator 660 was zero, which can also be set to a different value. Accordingly, the initialization value of the integrator 620 can also be set to a value other than zero. It is also possible to add the error value ε to the initialization value immediately upon initialization. With reference to Table 1, it is pointed out in particular that the fine quantization control in discrete cycles has been described above, but that the actual digitization only takes place at the up / down counter 680, and that the integrator 620, the adder 630 and the comparator 660 represent analog components, and the integration value Σ and the difference value δ are analog signals. The values shown in Table 1 are only obtained by applying a suitable clock to the control logic and to the up / down counter.

The analog signal path up to the integrator 620 ensures that small disturbances which are superimposed on the input signal α are averaged by the integrator 620 and small or slow changes in the input signal are continuously taken into account by summing up all previous errors in the output signal mit.

Furthermore, it is pointed out that the switching behavior of the control logic 670 in this example represents a simple demonstration and that the integrator 620 and the up / down counter 680 can also be controlled with more complex decision criteria and thus other sequences of digital values are generated which but also correspond on average to the input signal α.

As an example, reference is made here to the sequence illustrated in Table 2 and shown in FIGS. 11c and 11d. The The structure of the columns of Table 2 corresponds to that of Table 1. In Fig. 11c the values of ε, Σ and δ and in Fig. 11d the values of α, Θ and the mean of Θ are plotted over 10 steps on the y-axis , while the cycle steps are plotted on the x-axis. The procedure shown is based on the same conditions as the procedure described with reference to Table 1. The only difference lies in the decision criterion for the up and down control of counter 680. Here, too, the counting direction is determined from the sign of δ.

Table 2

First, however, only one step is counted further and then, with the sign of δ remaining the same, at least a certain number n _w steps are waited until counting continues again in the same direction. In the present example, the number of serviceable steps n _w = 3. container δ longer time in the same sign, so ge in this direction ^¬ is one, since it must be assumed that has changed α. In this way it is ensured that sichergestellt _n only between the switches between the two closest α values Θi <α and Θi + 1> α.

As can be seen from Table 2, the mean value of the last 10 values of Θ _n again corresponds to the input value α = 14.7.

The part of the circuit of FIG. 6 that performs the averaging will now be described with reference to FIG. 9. This part comprises the control logic 670 and an adaptable or adaptive digital filter 690, which outputs the filtered conversion result at the output 710.

If the input signal α is constant for a longer period of time or changes very slowly, a digital value corresponding to the input signal α can be interpolated linearly with high accuracy between the durch _n values over a longer period of time. With a high traversing speed or rapid change in the input signal α, however, it makes sense to keep the averaging time short so that the dead time of the control system remains short. The adaptable digital filter 690 makes it possible to adapt the resolution and the dynamic course of the filtered conversion result Θ to the current travel speed. The control logic 670 receives the information about the travel speed, for example, via a further input from the outside or uses the comparator signals KI, KM and KL (FIG. 6) originating from the coarse and fine quantization, and controls the digital filter 690 accordingly. For this purpose, the control logic 690 dynamically controls the current filter length of the digital filter 690 or adjusts the same to the travel speed. In addition, it can be provided that the control logic 670 further information, such as resolution requirements specified by the user, e p- catches to control the adaptable digital filter 690 or its current filter length.

The structure of the 4-quadrant adder 610 of FIG. 6 will now be explained in more detail with reference to FIG. 10. However, it is pointed out in advance that any adder can be used in the circuit of FIG. 6 if the input signal α is already present as a single analog value. The 4-quadrant adder 610 is provided in order to determine the error signal ε from the current digital value und _n and the signals Usin and Ucos which are in quadrature with respect to one another, for example from a measuring arrangement as shown in FIGS , be generated.

As can be seen in FIG. 10, the 4-quadrant adder 610 comprises a sine 810 and a cosine multiplier 800 and an adder 820. An input of the cosine multiplier 800 is connected to an input 805 of the 4-quadrant Adder 610 connected to receive the input signal Usin, with another input being connected to an input 807 of the 4-quadrant adder 610 to receive the current digital value _ Θ _n . The output of the cosine multiplier 800 is connected to a non-inverting input of the adder 820 in order to output the result of the multiplication of Usin and cos (Θ _n ). An input of the sine multiplier 810 is connected to an input 815 of the 4-quadrant adder 610 to receive the input signal Ucos, and another input is connected to the input 807 of the 4-quadrant adder 610 to determine the "current" to receive digital value Θ _n. the output of the sine multiplier 810 is connected to an inverting input of the adder 820 to the result of multiplication of Ucos and sin (Θ _n) output. the adder 820 indicates a Output 830 the error signal small ε out. The value of the error signal ε consequently assumes the value ε = U ₀ (t) (sin (α) cos (Θ) - cos (α) sin (Θ)). Using the approximation

E = sin (α) cos (Θ) - cos (α) sin (Θ) = sin (α-Θ) »α-Θ

the resulting error signal is ε = U ₀ (t) • (α-Θ).

The 4-quadrant adder can be supplemented by a correction table 840, which also receives the current digital value Θ _n . Its output feeds the digital / analog converter 850, the output of which in turn is fed to the adder. The correction table 840 can also additionally receive the carrier synchronization signal 855 required for the demodulation described below.

With this arrangement, manufacturing tolerances of multipliers 800 and 810 can be compensated for. The correction table 840 generates a digital correction signal 860 from the digital value 807, which is converted into an analog signal in the digital / analog converter 850, which corrects the ε signal 1 by small values. This is particularly important if the demodulation described below is to be carried out and the factors of the multipliers 800 and 810 for Θ _n and -Θ _{n have to} match. -

Since Θ tracks the input signal α, a similarly large signal α can always be expected for a specific Θ _n in connection with a specific state of the carrier synchronizing signal 855, and the result ε is therefore always subject to the same error. A correction of ε is therefore sufficient; a correction of the factors of the multipliers 800 and 810 is not necessary. The phase-sensitive demodulation of a pair of signals modulated, for example, with U ₀ (t) = Uι-cos (ωt) can be easily accomplished by using statt _n instead of Θ _n in the steps in which the carrier signal Ui cos (ωt) is <0 -Θ _{n is} fed back. Due to the sinusoidal shape of the carrier, the achievable accuracy of the linear interpolation decreases with a constant filter length. It is also important to ensure that the averaging takes place over a whole number of periods of the carrier signal.

Referring now to FIG. 12, a converter according to a particular embodiment of the present invention will be described, FIG. 12 showing the block diagram of the converter. The converter is intended for use in the digitization of measurement signals, such as those generated by the measurement arrangements shown in FIGS. 1a-1c.

The converter of FIG. 12 comprises two inputs 900 and 905 for receiving the input signals Usin and Ucos which are quadrature with respect to one another and an input 910 for receiving a clock signal CLK. An input 915 is also provided, to which a signal U carrier with carrier frequency is coupled. The circuit further comprises an output 920, at which the filtered conversion result THETA_OUT is output, an output 925, at which the ^" voltage UEPSILON, which corresponds to the error signal ε, and an output 927, at which the voltage UINT is applied, The two inputs 900 and 905 are each connected to the input of a DAC (Digital Analog Converter = DAC) 930 and 935, the outputs of which are connected to an inverting and a non-inverting input of a summer 940 The output of the totalizer 940 is connected to the output 925 of the converter, an input of an inverting integrator 945 and an input of three comparators 950, 955 and 960. The output of the inverting integrator 945 is connected to the other input of the three comparators 950-960 and the output 927 of the converter. The outputs of the comparators 950-960 are connected to three inputs of a control logic 965 in order to output signals KI, KH and L to the control logic. In the control logic 965, a further input is connected to the input 910 of the converter for receiving a clock signal CLK, as well as an output with an input of the inverting integrator 945 for transmitting a reset signal RESET_INT to the same and a further output with a loop counter 970 for transmitting one Counter control signal CNT_CNTRL connected. Another input of the loop counter 970 is also connected to the input 910 in order to receive the clock signal CLK. The output of the loop counter 970 is connected to both a quadrant selector 975 and an input of a digital interpolation filter 980 and outputs the signal THETA_COUNT stored in the loop counter 970, which corresponds to the digital output value. The digital interpolation filter 980 outputs the filtered signal THETA_OUT to the output ^" 920, which corresponds to the filtered digital output value. Another input of the quadrant selector 975 is connected to the input 915, with a sign detector 985 being interposed therebetween for the sign of the signal Ucarrier output signal SYNCH_CMP to the quadrant selector 975. The quadrant selector 975 is connected at one output to another input of the DACs 930 and 935 in order to output the signals THETA_CDAC and THETA_SDAC to the same DACs 930, the Output THETA_SDAC connected to another input of DAC 935.

After the structure of the circuit has been described above with reference to FIG. 12, the mode of operation of the circuit is described below.

To demodulate the input signals Usin and Ucos, an additional factor (-1) should be taken into account, depending on the sign of U carrier. The two multiplying nonlinear DACs 930 and 935 are also identical and implement the multiplication in two of the four quadrants of a sine or. Cosine function. Since the control signals THETA_SDAC and THETA_CDAC of the two DACs only cover half the value range of THETA_COUNT, the resolution NDAC is necessary for THETA_SDAC and THETA_CDAC, however, the resolution NDAC + 1 is required for THETA_COUNT and therefore now depending on the sign of Ucarrier and depending on the value range of Θ Factors sin (Θ) and cos (Θ) or -sin (Θ) and -cos (Θ) can be set, the quadrant selector 975 THETA_SDAC and THETA_CDAC from THETA_COUNT must be determined appropriately.

An example is given below with reference to Table 3 for the determination of THETA_SDAC and THETA_CDAC from THETA_COUNT. Table 3 includes 6 columns, from left to right the THETA_COUNT, the size of the carrier, the factor desired for the DAC 930, the THETA_CDAC to be set for it, the factor desired for the DAC 935 and the THETA_SDAC to be set for it. It is assumed that the multipliers realize a factor cos (Θ) for 0 ° <Θ <180 °. The calculation of the THETA CDAC from THETA COUNT and U carrier results from the fourth column of table 3 and the calculation of THETA_SDAC from THETA_COUNT and U carrier according to the sixth column of the table.

Table 3

The two DACs 930 and 935 multiply the input signal Usin by +/- cos (THETA_COUNT) or the input signal Ucos by +/- sin (THETA_COUNT). In the summer 940, the signal UEPSILON is formed according to the following equation:

ε (t) = U ₀ (t) • sign (U carrier) ^■ (sin (α) cos (Θ) - cos (c-) sin ((3rd

This signal is output 950-960 from the time tr from, as the integrator is reset 945 by the signal RESET__INT from the control logic 965, integrated in the inverting integrator 945 and the result of integration as the signal UINT to the Kompara ^factors' becomes. The time dependence of the signal UINT is given by the following equation:

Here Ti represents the integration time constant of the integrator 945.

The comparators 950-960 compare UEPSILON with UINT. In particular, the comparator 950 compares the UINT signal with the UEPSILON signal and uses the digital output signal KI to indicate whether UEPSILON is greater than UINT. The comparator 950 checks whether UEPSILON is much larger than UINT and, if it does, activates the digital output signal KH. Correspondingly, the comparator 960 checks whether UEPSILON is much smaller than UINT and, if this is the case, activates the digital output signal KL.

The loop counter 970 can change its stored value on each active clock edge of the clock signal CLK. The control logic 965 controls the state of the counter 970 and the resetting of the integrator 945 by means of the signals RESET_INT and CNT_CNTRL after the next clock cycle as a function of the signals KI, KH and KL. In the present case, control logic 965 controls loop counter 970 such that if a) the signal KI is active, the loop counter 970 increments or otherwise decrements the stored loop counter value THETA_COUNT, as a result of which the signal THETA_COUNT assumes a sequence of values which correspond on average to the input signal.

b) the KL signal or the KH signal is active, i.e. the amount of the error signal ε is very large, the loop counter 970 subtracts or counts a certain number of counter values from the stored value THETA_COUNT, so that THETA_COUNT is tracked to the fine quantization range.

In the latter case, the control logic activates the RESET_INT signal since the integration is not required. This makes the loop for tracking THETA_COUNT faster.

Interpolation of intermediate values is carried out if necessary by averaging in the digital filter 980 in conjunction with the integrator 945. In the event that UEPSILON is too large for a few bars, but is not sufficient to switch AI, UINT continues to drop. The errors due to the multiplication of smaller resolution N _D AC in the DACs 930 and 935 are summed up in the integrator 945 and “until the signal KI switches. As a result, UEPSILON vi-el becomes smaller and in most cases negative. As a consequence, UINT increases until the signal K is switched again, in this way the digital signal THETA__COUNT, which has a fixed resolution of NDAC + 1, always oscillates around the two values closest to the input signal the occurrence of the values can, however, be averaged in the digital filter 980 Signal THETA_COUNT with a higher resolution than N _DAC +1 can be obtained.

Resetting the integrator 945 for large error signals UEPSILON, which occur when α changes rapidly, ensures that it is not overdriven and goes into saturation. In this case, the integrator 945 is immediately available again for interpolation as soon as the signal THETA_COUNT is again in the correct range or the fine quantization range. The signal THETA_COUNT contains the information about the input signal coded with the highest possible sampling rate of the system. As a result, the interpolation filter 980 can optionally determine the output signal THETA_OUT by reducing the sampling rate in the required resolution N = N _DAC + 1 + Nι _n ter _P , where ι _nte rp indicates the resolution obtained by the interpolation filter 980.

Having described the invention in the foregoing by way of example, it is pointed out that, although the apparatus and the method according to the present invention have been described above in relation to signals quadrature with respect to one another, the present invention applies to any analog Signals can be used, and the same can be used advantageously, in particular, if rapid changes in the input signal allow a coarser quantization, - while otherwise a high resolution is required. In this case, the 4-quadrant adder of Fig. 6 could be replaced with a normal adder.

In addition, it is possible to carry out the comparators belonging to the coarse quantization control circuit several times and with different comparison values that differ from one another in terms of amount distinguish, which can be adapted to the size of the error signal tracking.

Claims

claims

1. A method for converting an analog input signal (α) into a sequence of digital output values (Θ _n ), with the following steps:

a) Forming a first difference value (ε) between the current digital output value (Θ _n ) and the analog input signal (α).

b) checking whether the amount of the first difference value (ε) exceeds a predetermined amount (S);

c) if the amount of the first difference value (ε) exceeds the predetermined amount, readjusting the digital output value (Θ _n ) using a specific control value;

d) if the amount of the first difference value (ε) does not exceed the predetermined amount,

dl) forming a second difference value (δ) between the first difference value (ε) and an In ^; tegrationswert (Σ), which consists of the sum of the first difference values (ε), since the check in step d) consistently showed that the amount of the first difference value (ε) does not exceed the predetermined amount;

d2) comparing the second difference value ei with ^¬ nem predetermined threshold; d3) incrementing or decrementing the digital output value depending on the result of the comparison in step d2).

2. The method according to claim 1, wherein the step of readjusting in step (c) is the addition or subtraction of a plurality of predetermined counter values to or from the current digital output value (Θ _n ) depending on the sign of the first difference value (ε ) until the output value (Θ _n ) crosses the value of the input signal (α) or the amount of the first difference value (ε) falls below the predetermined amount (S).

3. The method according to claim 1 or 2, wherein step d3) has the following substeps:

d3a) if the second difference value (δ) is greater than the predetermined threshold value, incrementing the digital output value (Θ _n ); and

d3b) if the second difference value (δ) is smaller than the predetermined threshold value, decrementing the digital output value (Θ _n ).

4. The method according to claim 3, wherein step d3a) has the following substep:

Suppressing the increment for a predetermined number of times since the comparison in step d2) continuously showed that the second difference value (δ) is larger than the predetermined threshold value, and in which step d-jb) has the following substep:

Suppressing decrementing for a predetermined number of times since the comparison in step d2) continuously showed that the second difference value (δ) is smaller than the predetermined threshold value.

5. The method according to any one of claims 1 to 4, further comprising the step of:

Forming an average value with respect to a variable number of successive output values (Θ _n ); and

Output of the mean value as a filtered output value in the sequence of output values (Θ _n ) instead of the successive output values (Θ _n ).

6. The method of claim 5, further comprising the step of:

Adapting the variable number to a given output rate.

7. The method according to any one of the preceding claims, wherein step a) of forming the first difference value comprises the following steps:

Receiving a first and a second input signal (Usin, Ucos) which are in quadrature with one another;

Multiplying the first input signal (Usin) by the cosine of the digital output value (Θ _n ); Multiplying the second input signal (Ucos) by the sine of the digital output value (Θ _n );

Adding up the results of the multiplications; and

Output the sum as the first difference value (ε).

8. The method according to claim 7, in which the negative digital output value (Θ _n ) is used for multiplication if the carrier signal (U carrier) with which the first and second

Input signal (Usin, Ucos) is modulated, is less than zero.

9. Device for converting an analog input signal (α) into a sequence of digital output values (Θ _n ), with

means (610) for forming a first difference value (ε) between the current digital output value (Θ _n ) and the analog input signal (α);

means (640, 650; 655, 660) for checking whether the amount of the first difference value (ε) exceeds a predetermined amount (S);

means (670, 680; 965, 970) for readjusting the digital output value (Θ _n ) using a predetermined control value if the amount of the first difference value (ε) exceeds the predetermined amount (S);

means (620, 630; 945, 950) for forming a second difference value between the first difference value (ε) and an integration value (Σ), which consists of the sum of the first difference values (ε), since the check by the checking device (640, 650; 955, 960) consistently showed that the amount of the first difference value (ε ) does not exceed the predetermined amount (S), for comparing the second difference value with a predetermined threshold value, and for incrementing or decrementing the digital output value (Θ _n ) depending on the result of the comparison.

10. The device according to claim 9, wherein the device (670, 680; 965, 970) for readjusting a device for adding or subtracting a plurality of predetermined counter values to or from the current digital output value (Θ _n ) as a function of has the sign of the first difference value (ε) until the digital output value (Θ _n ) crosses the input signal (α) or the amount of the first difference value falls below the predetermined amount (S).

11. The device as claimed in claim 9 or 10, in which the device for incrementing or decrementing has the following features:

means for incrementing the digital output value (Θ _n ) if the second difference value (δ) is greater than the predetermined threshold value; and

means for decrementing the digital output value (Θ _n ) if the second difference value (δ) is less than the predetermined threshold value.

12. The apparatus of claim 11, wherein the means for incrementing comprises:

means for suppressing the increment for a predetermined number of times since the comparison by the means for comparison continuously revealed that the second difference value (δ) is greater than the predetermined threshold value,

and in which the device for decrementing has the following feature:

means for suppressing decrementing for a predetermined number of times since the comparison by the means for comparison continuously revealed that the second difference value (δ) is less than the predetermined threshold value.

13. The device according to one of claims 9 to 12, further comprising:

means (690; 980) for averaging a variable number of successive output values (Θ _n ) and for outputting the mean value as a filtered output value instead of the successive output values (Θ _n );

14. The apparatus of claim 13, further comprising:

Means (670) for adjusting the variable number of ^• a predetermined output rate.

15. Device according to one of claims 9 to 14, in which the device (610) for forming the first difference value (ε) receives a first and a second input signal (Usin, Ucos), which are in quadrature with one another, and has the following features:

a cosine multiplier (800) for receiving the first input signal (Usin) and multiplying it by the cosine of the digital output value (Θ _n );

a sine multiplier (810) for receiving the second input signal (Ucos) and for multiplying it by the sine of the digital output value (Θ _n ); and

an adder (820) receiving the results of multiplying the cosine and sine multiplier (800, 810) to add them and output the sum as the first difference value (ε).

16. The apparatus of claim 15, wherein the sine and cosine multiplier (800, 810) use the negative digital output value (Θ _n ) for multiplication when the carrier signal (U carrier) with which the first and second input signal (Usin , Ucos) is modulated, is less than zero.

17. The device according to one of claims 9 to 16, which is implemented in a standard CMOS technology.