CA1239707A - Tri-well cmos technology - Google Patents
Tri-well cmos technologyInfo
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Abstract
TRI-WELL CMOS TECHNOLOGY
Richard C. Joy Tarsaim Lal Batra ABSTRACT
A semiconductor structure having at least three types of wells which may be of different doping levels and methods of manufacturing such a structure, are disclosed.
In one method, regions which will become active devices are protected with a nitride layer as the associated well-regions are implanted. In another method, previously implanted wells are covered with thick oxide which in combination with the nitride layer provides automatic alignment of adjacent wells. In yet another method, implanted wells are covered with oxide while a last well is implanted with this last well being defined by both thick oxide and photoresist. All methods avoid a masking step and avoid the need for aligning the edge of a later photoresist mask with the edge of an earlier photoresist mask. The structures formed by these methods may have heavily-doped P wells, heavily-doped N wells, and lightly-doped P or N wells, or both, for forming higher breakdown voltage devices on the same chip with lower breakdown voltage devices.
Richard C. Joy Tarsaim Lal Batra ABSTRACT
A semiconductor structure having at least three types of wells which may be of different doping levels and methods of manufacturing such a structure, are disclosed.
In one method, regions which will become active devices are protected with a nitride layer as the associated well-regions are implanted. In another method, previously implanted wells are covered with thick oxide which in combination with the nitride layer provides automatic alignment of adjacent wells. In yet another method, implanted wells are covered with oxide while a last well is implanted with this last well being defined by both thick oxide and photoresist. All methods avoid a masking step and avoid the need for aligning the edge of a later photoresist mask with the edge of an earlier photoresist mask. The structures formed by these methods may have heavily-doped P wells, heavily-doped N wells, and lightly-doped P or N wells, or both, for forming higher breakdown voltage devices on the same chip with lower breakdown voltage devices.
Description
BACKGROUND OF TIE INVENTION
_____ _ This invention relates to a truly CMOS structure and method of manufacture which provides a-t least three kinds of active regions for device formation. The active regions may include lightly doped regions of either N or P type for the formation of devices having a high breakdown voltage, mod-irately to heavily doped P wells for N channel devices having a low breakdown voltage, and moderately to heavily doped N elm regions for P channel devices having a low breakdown voltage.
The background of the invention will be further discussed with reference to the accompanying drawings, in which:
Figure lo shows a prior art P well CMOS structure.
Figure lb shows a prior art twin-tub CMOS structure.
Figures pa and 2b show a prior art method of form-in windows for the subsequent formation of doped wells follow-Ed in series by separate masking of subsequent wells.
Figures pa and 3b show a prior art method of using an oxide region to define the edge of a well to be doped follow-Ed by growing an oxide or nitride mask over the doped region before removing the photo resist mask.
Figures pa and 4b show a prior art method of growing adjacent wells using a mask of heavily-doped oxide which imp plants do pants of one conductivity type while do pants of oppo-site conductivity type are implanted into an exposed adjacent area.
Figure 5 shows one embodiment of the truly CMOS
structure constructed in accordance with this invention.
Figure 6 shows a second embodiment of the truly CMOS structure constructed in accordance with this invention.
Figures pa through 7j show steps in forming three .,..~
_____ _ This invention relates to a truly CMOS structure and method of manufacture which provides a-t least three kinds of active regions for device formation. The active regions may include lightly doped regions of either N or P type for the formation of devices having a high breakdown voltage, mod-irately to heavily doped P wells for N channel devices having a low breakdown voltage, and moderately to heavily doped N elm regions for P channel devices having a low breakdown voltage.
The background of the invention will be further discussed with reference to the accompanying drawings, in which:
Figure lo shows a prior art P well CMOS structure.
Figure lb shows a prior art twin-tub CMOS structure.
Figures pa and 2b show a prior art method of form-in windows for the subsequent formation of doped wells follow-Ed in series by separate masking of subsequent wells.
Figures pa and 3b show a prior art method of using an oxide region to define the edge of a well to be doped follow-Ed by growing an oxide or nitride mask over the doped region before removing the photo resist mask.
Figures pa and 4b show a prior art method of growing adjacent wells using a mask of heavily-doped oxide which imp plants do pants of one conductivity type while do pants of oppo-site conductivity type are implanted into an exposed adjacent area.
Figure 5 shows one embodiment of the truly CMOS
structure constructed in accordance with this invention.
Figure 6 shows a second embodiment of the truly CMOS structure constructed in accordance with this invention.
Figures pa through 7j show steps in forming three .,..~
-2- 70128-99 wells of different compositions using the method of this invent lion in an embodiment where active devices will be formed after formation of the wells and where adjacent wells are not self-aligned.
inures pa through oh show steps in forming three wells of different composition using the method of this invent lion where adjacent wells are self-alignedO
Figures I and 8j show a device having two implanted, self-aligned welts and a third self-aligned high voltage region available for active device formation.
Figures 9 through 11 show steps of well known design used to form a device upon the substrate which was formed as shown in Figures pa through 7j or Figures pa through oh accord-in to the method of this invention.
A prior art P well COOS structure is illustrated in Figure lay P well 1 is diffused into a silicon substrate 2.
silicon substrate 2 has been moderately doped with N type do pants to a level within the range of approximately 2 x 1015 to 4 X10l5 : atoms/cm3. Source and drain regions 4 and 5 respectively of an N channel device 3 having a gate 6 are then formed in P well 1, and source and drain regions 8 and 9 of a P channel device 7 having a gate 10 are formed in N type substrate 2.
In practice, due to processing variations, there is some deviation between the actual doping levels achieved in the P well and the N substrate and their desired doping levels.
For control purposes, in order to render these deviations less significant, the doping of P well 1 is at least an order of magnitude greater than the doping of N substrate 2, thereby insuring that, regardless of processing variations, P well 1 will have a sufficiently high concentration of P type do pants.
CMP/5360-lCN
inures pa through oh show steps in forming three wells of different composition using the method of this invent lion where adjacent wells are self-alignedO
Figures I and 8j show a device having two implanted, self-aligned welts and a third self-aligned high voltage region available for active device formation.
Figures 9 through 11 show steps of well known design used to form a device upon the substrate which was formed as shown in Figures pa through 7j or Figures pa through oh accord-in to the method of this invention.
A prior art P well COOS structure is illustrated in Figure lay P well 1 is diffused into a silicon substrate 2.
silicon substrate 2 has been moderately doped with N type do pants to a level within the range of approximately 2 x 1015 to 4 X10l5 : atoms/cm3. Source and drain regions 4 and 5 respectively of an N channel device 3 having a gate 6 are then formed in P well 1, and source and drain regions 8 and 9 of a P channel device 7 having a gate 10 are formed in N type substrate 2.
In practice, due to processing variations, there is some deviation between the actual doping levels achieved in the P well and the N substrate and their desired doping levels.
For control purposes, in order to render these deviations less significant, the doping of P well 1 is at least an order of magnitude greater than the doping of N substrate 2, thereby insuring that, regardless of processing variations, P well 1 will have a sufficiently high concentration of P type do pants.
CMP/5360-lCN
3 Problems of scale emerged from the prior art structure
4 as the device density i.e., the number of devices per unit area, was increased For example, as the distance between 6 the P+ source and drain regions 8 and 9 of device 7 is 7 reduced, the doping of N substrate 2 must increase to obtain 8 appropriate electrical parameters, such as device threshold 9 voltage, in the shorter channel length P channel transistor 7. However, increasing the doping of N substrate 2 requires 11 a corresponding proportional increase in the doping level of 12 P well 1 for control purposes as explained above.
13 The increase in the doping level of P well 1 causes 14 increased junction capacitance between N+ source and drain regions 4 and 5 and P well 1. In fact, for a single-sided I junction under zero bias, the junction capacitance varies 17 directly as the square root of the Dupont concentration on 18 the lightly doped side of the junction, as shown in MOW
19 INTEGRATED CIRCUITS, pus. 45 and 46, Engineering Staff of American Micro-Systems, Robert E. Krueger Pub. Co., Malibu, 21 Flay (1979). In turn this increased capacitance has the I undesirable effect of reducing the switching speed of 23 transistor 3-24 In order to overcome these problems of scale, a twin-tub CMOS technology was developed by Purl, et at., in "TWIN-I TUB CMQS-A TECHNOLOGY FOR VLSI CIRCUITS", IEEE Tech. Dig., 27 Into Electron Device Meet., 1980, p. 752-755. Fig. lb 28 illustrates the Purl Twin-tub structure.
29 The Purl structure includes lightly doped epitaxial region 20 formed on an N+ substrate 21. The use of an 31 substrate reduces the substrate resistance and prevents 32 "latch-up") a term which refers to the turning on of 33 "parasitic" bipolar transistors within the structure shown 34 in Fig. lb as will be explained later.
Both a P well 23 and an N well 24 are then formed in the I epitaxial layer 20 by ion implantation. This is 37 accomplished in a self-aligned manner by first defining an CMP/5360-lCN ~39~7 oxide-nitride mask (not shown), implanting and selectively 1 oxiding N well 24, removing the remaining mask and implant 2 in P well 23 self-aligned to the oxide masked N well 24.
3 The P well 23 and N well 24 are doped independently in 4 order to optimize the performance characteristics of the active devices formed in P well 23 and N well 24, respectively. For example, the active devices may include 7 transistor 28 having gate 27, gate dielectric layer 33 and 8 source and drain regions 25 and 26, respectively, formed in 3 P well 23 and transistor 32 having gate 31, gate dielectric layer 33~ and source and drain regions 29 and 30 formed in N
11 well 24. Thus it can be seen that increasing the doping of 12 N well 24 to accommodate a decrease in the dimensional 13 parameters of the P channel device 32 no longer necessitates 14 a corresponding increase in the Dupont concentration of P
well 23. Of importance, parasitic bipolar transistors exist 16 within this twin well structure. For example, an NUN
Lo parasitic transistor is formed by N+ region Z6, P well 23, 18 and N+ substrate 21. However, the N+ substrate has low 19 resistivity and thus prevents "latch-up". Latch-up is a well-known problem, an analysis of which is presented in an 21 article entitled "Elimination of Latch-up in Bulk CMOSI', 22 IDIOM Paper 10.2, December 8-10, Washington, DO
23 Both N well 29 and P well 23 in the prior art twin-tub 24 structure described by Purl are heavily doped. Purl uses a Dupont concentration of about 1016 atoms/cm3 at the 26 surface of each well. Because of the relatively high doping 27 in both wells, this structure is not well suited to 28 integration with devices such as transistors, diodes, or 29 resistors which are designed to operate at high voltages, say greater than 20 volts. In particular the prior art 31 twin-tub structure is not suited for the integration of 32 erasable programmable read only memories PROMS or with 33 electrically erasable programmable read only memories 34 (EEPROMS) which require junction breakdown voltages greater than approximately 20 volts.
?
Sue l In addition to the need for providing both high and 2 low voltage devices on the same chip, and thus providing a 3 variety of doping levels for different wells, it is desire 4 able to develop methods for forming structures which are faster and less expensive, and allow for forming smaller 6 devices while retaining high yield. Various prior art 7 methods have been developed to accomplish the objective of 8 providing on the same chip different doping levels and 9 -do pants for different wells.
A method shown in Figures pa and 2b forms multiple I windows in a nitride/oxide layer, exposing the surface to 12 permit the subsequent formation of diffusion isolation 13 regions, base regions, and collector contact regions in 14 the semiconductor body. The areas are masked, exposed, and doped in a predetermined sequence. The original areas 16 of oxide/nitride, which were left between windows serve to 17 define the edges of the wells, and on these areas of I oxide/ni~ride the edges of successive footraces masks 19 are defined. Mask misalignment tolerances can be less I stringent because the edges of the masks are formed over 21 the previously formed areas of nitride/oxide and the I nitride/oxide serves to define the edge of the well. US.
23 Patent No. 3,928,081 to Manley, Jr., et at., shows such a 24 method for eliminating mask misalignment tolerances.
As shown in Figs. pa and 3b, US. Patent 4,450,021, 26 issued to Butter, et at., one of the coinventors of this I application, uses a mask 109 for defining regions 110 to 28 be doped and uses the same mask or depositing a protective 2g layer ill over the doped regions. With this arrangement, the alignment of the edge of the protective layer 111 is 31 assured, because the edge of the oxide defines the area to 32 be doped. When the mask is removed, the second regions 33 112 which are now exposed are automatically aligned to b 34 doped without interfering with the first regions which are covered by protective layer ill. By this method it is 36 possible to achieve doping of two wells with one masking 37 step, thus saving the time of applying and defining the ,.
..._ .
I
Jo mask and thus also achieving automatic self-alignment of the areas to be doped. The method shown in this prior art patent is described as being applicable to implanting 4 source and drain regions in the chip.
Thus, use of portions of the device as a mask for forming later portions is a well-known method ox prevent-7 in misalignment.
Cerofolini, et at., in US. Patent No. 4,277,291, 9 discloses a different method, shown in Fits. pa and 4b, 0 which could be used for forming adjacent, self-aligned N
and P wells in which a heavily N-doped oxide mask is in place during P-doping and diffusion. The N-doped oxide mask prevents doping of the masked portion during the P-doping step and then produces diffusion of the N-dopant from the doped oxide into the substrate at the same time 16 the P-doped region is being diffused into the substrate, 17 resulting in simultaneous formation of self-aligned N an 18 p wills-SUMMARY
21 The present invention provides a semiconductor struck 22 lure having at least three active regions for Davis formation formed in a lightly doped substrate, for example, 24 a first moderately to heavily doped well of the same conductivity type as the substrate, a second moderately to 26 heavily doped well having conductivity type opposite to 27 that of the substrate and a third lightly doped region of either type having a conductivity of the same order of 29 magnitude as the substrate. In one embodiment of the structure the third region is a portion of the substrate 31 itself.
32 The present invention also provides a method of 33 forming a semiconductor structure which rulers fewer 34 masking steps than the number of wells to be formed in the 35 substrate. Two embodiments of this method are described, to both achieving a truly substrate using only two photo-making steps. Both methods are appropriate for applications in which the multiple devices on a chip will be separated by a thick field oxide. With the first method adjacent wells are not self-aligned. The first method involves placing an oxide/nitride layer over regions which will become active devices and doping -through the nitride the substrate of the active device and the adjacent exposed field. The second method involves first de-fining an exposed region to be doped, then doping that region to form a well in which the field and active region of a device will be formed, then covering that region with a thick oxide layer. Using a second photo resist mask, another area of thin oxide/nitride is removed, with the newly formed thick oxide and/or the oxide/nitride serving to define edges of the second exposed area, and so on with subsequent regions. This order of formation causes subsequent well regions to be automatically self-aligned with previous well regions and also results in a process for forming successive well regions requiring fewer masking steps than the number of wells, in contrast to previous methods. This improvement in turn results in allowing a higher yield of smaller devices at a lower manufacturing cost. Neither method requires accurate alignment of a photo resist task with a previous photo resist mask. Alternative embodiments are also described.
: The invention may be summarized, according to a first broad aspect, as a semiconductor structure comprising: a substrate of a first conductivity type; a first well, formed within said substrate, of said first conductivity type having : greater conductivity than said substrate; a second well, formed within said substrate, of a second conductivity type opposite CMP/5360-lCN
1 said first conductivity type having greater conductivity 2 than said substrate; and a third well being a high voltage 3 region in said substrate of either said first conductivity 4 type or said second conductivity type having a conductivity
13 The increase in the doping level of P well 1 causes 14 increased junction capacitance between N+ source and drain regions 4 and 5 and P well 1. In fact, for a single-sided I junction under zero bias, the junction capacitance varies 17 directly as the square root of the Dupont concentration on 18 the lightly doped side of the junction, as shown in MOW
19 INTEGRATED CIRCUITS, pus. 45 and 46, Engineering Staff of American Micro-Systems, Robert E. Krueger Pub. Co., Malibu, 21 Flay (1979). In turn this increased capacitance has the I undesirable effect of reducing the switching speed of 23 transistor 3-24 In order to overcome these problems of scale, a twin-tub CMOS technology was developed by Purl, et at., in "TWIN-I TUB CMQS-A TECHNOLOGY FOR VLSI CIRCUITS", IEEE Tech. Dig., 27 Into Electron Device Meet., 1980, p. 752-755. Fig. lb 28 illustrates the Purl Twin-tub structure.
29 The Purl structure includes lightly doped epitaxial region 20 formed on an N+ substrate 21. The use of an 31 substrate reduces the substrate resistance and prevents 32 "latch-up") a term which refers to the turning on of 33 "parasitic" bipolar transistors within the structure shown 34 in Fig. lb as will be explained later.
Both a P well 23 and an N well 24 are then formed in the I epitaxial layer 20 by ion implantation. This is 37 accomplished in a self-aligned manner by first defining an CMP/5360-lCN ~39~7 oxide-nitride mask (not shown), implanting and selectively 1 oxiding N well 24, removing the remaining mask and implant 2 in P well 23 self-aligned to the oxide masked N well 24.
3 The P well 23 and N well 24 are doped independently in 4 order to optimize the performance characteristics of the active devices formed in P well 23 and N well 24, respectively. For example, the active devices may include 7 transistor 28 having gate 27, gate dielectric layer 33 and 8 source and drain regions 25 and 26, respectively, formed in 3 P well 23 and transistor 32 having gate 31, gate dielectric layer 33~ and source and drain regions 29 and 30 formed in N
11 well 24. Thus it can be seen that increasing the doping of 12 N well 24 to accommodate a decrease in the dimensional 13 parameters of the P channel device 32 no longer necessitates 14 a corresponding increase in the Dupont concentration of P
well 23. Of importance, parasitic bipolar transistors exist 16 within this twin well structure. For example, an NUN
Lo parasitic transistor is formed by N+ region Z6, P well 23, 18 and N+ substrate 21. However, the N+ substrate has low 19 resistivity and thus prevents "latch-up". Latch-up is a well-known problem, an analysis of which is presented in an 21 article entitled "Elimination of Latch-up in Bulk CMOSI', 22 IDIOM Paper 10.2, December 8-10, Washington, DO
23 Both N well 29 and P well 23 in the prior art twin-tub 24 structure described by Purl are heavily doped. Purl uses a Dupont concentration of about 1016 atoms/cm3 at the 26 surface of each well. Because of the relatively high doping 27 in both wells, this structure is not well suited to 28 integration with devices such as transistors, diodes, or 29 resistors which are designed to operate at high voltages, say greater than 20 volts. In particular the prior art 31 twin-tub structure is not suited for the integration of 32 erasable programmable read only memories PROMS or with 33 electrically erasable programmable read only memories 34 (EEPROMS) which require junction breakdown voltages greater than approximately 20 volts.
?
Sue l In addition to the need for providing both high and 2 low voltage devices on the same chip, and thus providing a 3 variety of doping levels for different wells, it is desire 4 able to develop methods for forming structures which are faster and less expensive, and allow for forming smaller 6 devices while retaining high yield. Various prior art 7 methods have been developed to accomplish the objective of 8 providing on the same chip different doping levels and 9 -do pants for different wells.
A method shown in Figures pa and 2b forms multiple I windows in a nitride/oxide layer, exposing the surface to 12 permit the subsequent formation of diffusion isolation 13 regions, base regions, and collector contact regions in 14 the semiconductor body. The areas are masked, exposed, and doped in a predetermined sequence. The original areas 16 of oxide/nitride, which were left between windows serve to 17 define the edges of the wells, and on these areas of I oxide/ni~ride the edges of successive footraces masks 19 are defined. Mask misalignment tolerances can be less I stringent because the edges of the masks are formed over 21 the previously formed areas of nitride/oxide and the I nitride/oxide serves to define the edge of the well. US.
23 Patent No. 3,928,081 to Manley, Jr., et at., shows such a 24 method for eliminating mask misalignment tolerances.
As shown in Figs. pa and 3b, US. Patent 4,450,021, 26 issued to Butter, et at., one of the coinventors of this I application, uses a mask 109 for defining regions 110 to 28 be doped and uses the same mask or depositing a protective 2g layer ill over the doped regions. With this arrangement, the alignment of the edge of the protective layer 111 is 31 assured, because the edge of the oxide defines the area to 32 be doped. When the mask is removed, the second regions 33 112 which are now exposed are automatically aligned to b 34 doped without interfering with the first regions which are covered by protective layer ill. By this method it is 36 possible to achieve doping of two wells with one masking 37 step, thus saving the time of applying and defining the ,.
..._ .
I
Jo mask and thus also achieving automatic self-alignment of the areas to be doped. The method shown in this prior art patent is described as being applicable to implanting 4 source and drain regions in the chip.
Thus, use of portions of the device as a mask for forming later portions is a well-known method ox prevent-7 in misalignment.
Cerofolini, et at., in US. Patent No. 4,277,291, 9 discloses a different method, shown in Fits. pa and 4b, 0 which could be used for forming adjacent, self-aligned N
and P wells in which a heavily N-doped oxide mask is in place during P-doping and diffusion. The N-doped oxide mask prevents doping of the masked portion during the P-doping step and then produces diffusion of the N-dopant from the doped oxide into the substrate at the same time 16 the P-doped region is being diffused into the substrate, 17 resulting in simultaneous formation of self-aligned N an 18 p wills-SUMMARY
21 The present invention provides a semiconductor struck 22 lure having at least three active regions for Davis formation formed in a lightly doped substrate, for example, 24 a first moderately to heavily doped well of the same conductivity type as the substrate, a second moderately to 26 heavily doped well having conductivity type opposite to 27 that of the substrate and a third lightly doped region of either type having a conductivity of the same order of 29 magnitude as the substrate. In one embodiment of the structure the third region is a portion of the substrate 31 itself.
32 The present invention also provides a method of 33 forming a semiconductor structure which rulers fewer 34 masking steps than the number of wells to be formed in the 35 substrate. Two embodiments of this method are described, to both achieving a truly substrate using only two photo-making steps. Both methods are appropriate for applications in which the multiple devices on a chip will be separated by a thick field oxide. With the first method adjacent wells are not self-aligned. The first method involves placing an oxide/nitride layer over regions which will become active devices and doping -through the nitride the substrate of the active device and the adjacent exposed field. The second method involves first de-fining an exposed region to be doped, then doping that region to form a well in which the field and active region of a device will be formed, then covering that region with a thick oxide layer. Using a second photo resist mask, another area of thin oxide/nitride is removed, with the newly formed thick oxide and/or the oxide/nitride serving to define edges of the second exposed area, and so on with subsequent regions. This order of formation causes subsequent well regions to be automatically self-aligned with previous well regions and also results in a process for forming successive well regions requiring fewer masking steps than the number of wells, in contrast to previous methods. This improvement in turn results in allowing a higher yield of smaller devices at a lower manufacturing cost. Neither method requires accurate alignment of a photo resist task with a previous photo resist mask. Alternative embodiments are also described.
: The invention may be summarized, according to a first broad aspect, as a semiconductor structure comprising: a substrate of a first conductivity type; a first well, formed within said substrate, of said first conductivity type having : greater conductivity than said substrate; a second well, formed within said substrate, of a second conductivity type opposite CMP/5360-lCN
1 said first conductivity type having greater conductivity 2 than said substrate; and a third well being a high voltage 3 region in said substrate of either said first conductivity 4 type or said second conductivity type having a conductivity
5 of the same order of magnitude as said substrate for the
6 formation of devices having high junction breakdown
7 voltages, and in which the edges of said first, second, and
8 third wells are automatically self-aligned.
9 According to a second broad aspect, the invention provides a method of forming wells in a semiconductor 11 substrate comprising: depositing a thin layer of oxide on 12 said substrate, depositing a layer of silicon nitride on 13 said thin layer of oxide, initiating a process to be 14 repeated at least two times in the stated order of:
applying a lyre of photo resist, removing portions of said 16 photo resist, thereby exposing portions of said silicon 17 nitride, removing exposed portions of said silicon nitride 18 and thin oxide, thus creating exposed portions of said I semiconductor substrate, implanting do pants of a selected conductivity type to a selected concentration into said 21 exposed portions of said semiconductor substrate, thereby 22 forming a well of said selected conductivity type having a 23 breakdown voltage determined by said selected concentration, 24 oxidizing said exposed portions of semiconductor substrate thus creating protective thick oxide over said exposed 26 portions and diffusing said do pants into said semiconductor 27 substrate, and after sufficient repetition of said process, 28 when the desired number of regions have been formed, 29 removing said protective thick oxide.
According to a third broad aspect, the invention 3]- provides a method of forming wells in a semiconductor 32 substrate comprising: depositing a thin layer of oxide on 33 said substrate, depositing a layer of silicon nitride on 34 said thin layer of oxide, I
-7b- 7012~-99 initiating a process to be repeated at least one time of:
applying a layer of photo resist, removing portions of said photo-resist, thereby exposing portions of said silicon nitride, no-moving exposed portions of said silicon nitride and thin oxide, thus creating exposed portions of said semiconductor substrate, implanting do pants of a selected conductivity type to a selected concentration into said exposed portions of said semiconductor substrate, thereby forming a well of said selected conductivity type having a breakdown voltage determined by said selected concentration, oxidizing said exposed portions of semiconductor substrate, thus creating protective thick oxide over said exposed portions and diffusing said do pants into said semiconductor substrate, and after sufficient repetition of said process, when one well region remains to be formed, applying a layer of photo resist, removing portions of said photo resist, thereby creating exposed portions of said silicon nitride, implanting through said exposed portions of silicon nitride and said thin layer of oxide do pants of a selected conductivity type to a selected concentration into said semiconductor substrate, there-by forming a well of said selected conductivity type having breakdown voltage determined by said selected concentration, diffusing said do pants of a selected conductivity type into said semiconductor substrate, removing said layer of silicon nitride and said thin and thick layers of oxide.
One embodiment of a structure constructed in accord dance with this invention is depicted in cross sectional view in Figure 5. The region 40 is a lightly doped P type semi con doctor substrate, typically silicon. Alternatively, region 40 is epitaxial semiconductor material formed on an underlying substrate. For simplicity, this specification will refer to region 40 as a substrate.
In this embodiment, substrate 40 is a P type sift-con semiconductor having a resistivity in the range of approxi~
, , :, I
CMP/5360-lCN
1 mutely 30 to 100 ohm-cm. For a P type silicon substrate, a 2 resistivity of approximately 30 to 100 ohm-cm corresponds to 3 an impurity concentration of approximately 1 x 1014 to 2.5 x 4 1014 P type atoms/cm3 in the substrate. This is shown in 5 Grove, Physics and Technology of Semiconductor Devices, pus.
6 111-113, John Wiley & Sons (1967). In general, the 7 resistivity of the substrate decreases as the impurity 8 concentration in the substrate increases.
9 Since resistivity, p, is the reciprocal of conductivity,
applying a lyre of photo resist, removing portions of said 16 photo resist, thereby exposing portions of said silicon 17 nitride, removing exposed portions of said silicon nitride 18 and thin oxide, thus creating exposed portions of said I semiconductor substrate, implanting do pants of a selected conductivity type to a selected concentration into said 21 exposed portions of said semiconductor substrate, thereby 22 forming a well of said selected conductivity type having a 23 breakdown voltage determined by said selected concentration, 24 oxidizing said exposed portions of semiconductor substrate thus creating protective thick oxide over said exposed 26 portions and diffusing said do pants into said semiconductor 27 substrate, and after sufficient repetition of said process, 28 when the desired number of regions have been formed, 29 removing said protective thick oxide.
According to a third broad aspect, the invention 3]- provides a method of forming wells in a semiconductor 32 substrate comprising: depositing a thin layer of oxide on 33 said substrate, depositing a layer of silicon nitride on 34 said thin layer of oxide, I
-7b- 7012~-99 initiating a process to be repeated at least one time of:
applying a layer of photo resist, removing portions of said photo-resist, thereby exposing portions of said silicon nitride, no-moving exposed portions of said silicon nitride and thin oxide, thus creating exposed portions of said semiconductor substrate, implanting do pants of a selected conductivity type to a selected concentration into said exposed portions of said semiconductor substrate, thereby forming a well of said selected conductivity type having a breakdown voltage determined by said selected concentration, oxidizing said exposed portions of semiconductor substrate, thus creating protective thick oxide over said exposed portions and diffusing said do pants into said semiconductor substrate, and after sufficient repetition of said process, when one well region remains to be formed, applying a layer of photo resist, removing portions of said photo resist, thereby creating exposed portions of said silicon nitride, implanting through said exposed portions of silicon nitride and said thin layer of oxide do pants of a selected conductivity type to a selected concentration into said semiconductor substrate, there-by forming a well of said selected conductivity type having breakdown voltage determined by said selected concentration, diffusing said do pants of a selected conductivity type into said semiconductor substrate, removing said layer of silicon nitride and said thin and thick layers of oxide.
One embodiment of a structure constructed in accord dance with this invention is depicted in cross sectional view in Figure 5. The region 40 is a lightly doped P type semi con doctor substrate, typically silicon. Alternatively, region 40 is epitaxial semiconductor material formed on an underlying substrate. For simplicity, this specification will refer to region 40 as a substrate.
In this embodiment, substrate 40 is a P type sift-con semiconductor having a resistivity in the range of approxi~
, , :, I
CMP/5360-lCN
1 mutely 30 to 100 ohm-cm. For a P type silicon substrate, a 2 resistivity of approximately 30 to 100 ohm-cm corresponds to 3 an impurity concentration of approximately 1 x 1014 to 2.5 x 4 1014 P type atoms/cm3 in the substrate. This is shown in 5 Grove, Physics and Technology of Semiconductor Devices, pus.
6 111-113, John Wiley & Sons (1967). In general, the 7 resistivity of the substrate decreases as the impurity 8 concentration in the substrate increases.
9 Since resistivity, p, is the reciprocal of conductivity,
10 a, (i.e./ a = l/p), one may equivalently specify the
11 corresponding conductivity of the substrate.
12 In turn the breakdown voltage for several important
13 classes of PUN junctions is inversely proportional to the
14 substrate impurity concentration. For example, a so-called one-sided step junction, which is an abrupt junction wherein I the impurity concentration in each of the P and N regions is 17 uniform throughout that region and wherein the concentration 18 of the impurity on one side of the junction is much larger 19 than on the other side of the junction, has the property that the junction breakdown voltage is inversely 21 proportional to the substrate Dupont concentration for a 22 constant critical field as shown in Grove, swooper, at pg.
23 194. Similar, very shallow diffused junctions behave very 24 much like one-sided step junctions. See Grove, swooper, at I pg. 159.
26 Thus low P type impurity concentrations in the substrate 27 40 and region 43, typically of the order of 1 x 1014 to 2.5 28 x 1014 atoms/cm3, permit the formation of active devices in 29 region 43 having high junction breakdown voltages (greater than 20 volts). In another embodiment, region 43 is simply 31 a portion of the substrate 40.
32 N well 41 it an N type region formed in substrate 40, 33 typically by ion implantation, having moderate to heavy 34 Dupont levels of an N type material, for example, within the range of approximately 8 x 1014 to 3 x 1016 atoms/cm3.
36 Alternatively, well known diffusion processes can be used 37 for form N well 41. The N well 41 is suitable for the I
g 1 formation of low voltage devices, for example P channel 2 transistors resistors or diodes (not shown).
3 P well 42 is a region of moderate to heavily doped P
4 type semi conductive material formed (typically by ion S implantation or diffusion) in the substrate 40. The P
type Dupont concentration in P well 42 ranges from approxi-7 mutely 8 x oily to 3 x 1016 atoms/cm3. P well 42 is 8 suitable for the formation of low voltage devices, for 9 example resistors, diodes, or N channel transistors P well 42 and N well 41 of Fig. 5 are doped indepen-11 deftly to achieve desired electrical characteristics, e.g.
12 threshold voltages, which depend on Dupont levels, of the I P channel and N channel devices formed therein. Region 43 14 s a lightly doped region of P type semi conductive material Typically the Dupont level in region 43 is within the 16 range of approximately 1 x 1014 to 4 x 1014 or more P type 17 atoms/cm3 and is thus suitable for the formation of devices 18 having high junction breakdown voltages (greater than 20 19 Yolks) in close proximity to the low voltage devices formed in P well 42 and N well 41.
21 The above embodiment uses a type substrate. An N
22 type substrate can also be used, where well region 43 is 23 of P type conductivity. However when an N type substrate 24 it used, it should be noted that generally lower impurity I concentrations produce the same resistivity, as shown in 26 Grove, swooper, at page 113. For example, a substrate 27 resistivity of 10 to 50 ohm-cm corresponds to an N type 28 impurity concentration of approximately 4 x 1014 to 29 1 x oily atoms/cm3.
It is also important to note that the arrangement of 31 the regions 41, 42, and 43 shown in Fig. 5 is not critical.
32 For example in another embodiment, as shown in Fig. 6, 33 N well 51 and region 53 are separated by P well 52. In 34 this embodiment, region So has the same conductivity type as the substrate So and a conduc~iviky of the same order 36 of magnitude as substrate 50.
...._ CMP/5360-lCN
One process for forming a truly CMOS structure according to the present invention is illustrated in Figs. pa through 7j. Another begins with Fig. pa and moves 4 to Figs. aye. In either case, the process begins with a lightly doped substrate 60 of either N type or P type. When 6 substrate 60 is P type, a Dupont concentration of 8 approximately 1x101~ atoms/cm3 is typical. An N type substrate would have a lower Dupont concentration.
9 Fig pa shows a lightly doped semiconductor structure with a base oxide layer and a nitride layer formed 11 thereon. Base oxide layer 61 is formed on substrate 60 to a 12 thickness within the range of approximately 500 to Lowe, 13 for example by thermal oxidation at approximately 100CC for 14 approximately 45 to 75 minutes in an atmosphere of 2 + 3 HAL.
16 Nitride layer 62 is formed on base oxide layer 61 using, 17 for example, low pressure chemical vapor deposition (LPCVD) I to a thickness of approximately ls00A. Oxide 61 separates 19 nitride 62 from substrate 60 and thus allows nitride 62 to be completely removed at a later stage.
22 First Embodiment 23 According to one method for forming the separately 24 implanted well regions of this invention, base oxide 61 and nitride layer 62 shown in Fig. pa are then patterned to 26 define the active regions of the device shown in Fig. 7b.
27 The active regions remain covered by oxide 61 and nitride 62 while the adjacent field regions are exposed. This patterning is accomplished by spinning photo resist 81 onto nitride 62 which is then soft baked. The field mask is then 31 aligned to the wafer flat and the portions of photo resist 32 exposed by the mask are subjected to actinic radiation.
33 Exposed portions of photo resist 81 are then removed by 3 development. Photo resist 81 is then hard baked so that it is not affected by the enchants used to remove the unmasked I regions of nitride and oxide. Typically, plasma etching is used to remove the unmasked regions of CMP/5360-lCN
nitride and buffered HO is used to remove the regions of 2 oxide. The remaining portions of photo resist 81 are removed 3 after the etching step in order to produce the structure 4 shown in Fig. 7c. As will be appreciated by those of ordinary skill in the art, if desired, the photo resist 81 and masking to define active area live.; those areas located 7 in substrate 60 beneath portions of oxide 61 and nitride 62 8 which remain in the structure of Fig. 7c) can be postponed 9 until after formation of all desired well regions A P well mask of photo resist 82 is formed on the 11 structure of Fig. 7c which exposes the P well (N channel) 12 field and active regions 65. At this stage, the field 13 regions are fully exposed and the active regions are partly 14 protected by the nitride/oxide sandwich 61, 62 as shown in Fig. Ed.
16 A field implant of P type do pants is then accomplished 17 using boron at a dosage of approximately 3X1013 ions/cm2 and I an energy level of approximately 25 Key. This step implants 19 a shallow boron charge into the field regions which raises the field inversion potential, hence preventing parasitic 21 field devices.
22 Next, a P-well implant is performed using Boron at a 23 dosage of approximately 6X1012 ions/cm2 at an energy level 24 of approximately 120 Key, which is sufficient that the P
I well is implanted through the nitride/oxide layer.
26 As shown in Fig. ye, similarly, an N well mask of 27 photo resist is used to expose N well UP channel) field and active regions 71. A field implant of N type do pants is 29 then accomplished using phosphorus. The N well implant is performed using phosphorus at a dosage of approximately 31 2X1012 ions/cm2 at an energy of approximately 150 Key.
32 A high voltage region mask need not be formed when the 33 lightly doped substrate itself serves as the high voltage 34 region. However, if it is desired to adjust the Dupont type or the Dupont concentration in the high voltage region, a 36 high voltage region mask (not shown) is formed using 37 photo resist in order to expose field and active 1 regions 68 for high voltage devices. This step is follow-2 Ed by a high voltage region implant using a selected 3 impurity type. For example, for a P type high voltage 4 region, a Dupont concentration of approximately 1x1014 to 4xlol4 P type atoms/cm3 is used. In one embodiment, the 6 field implant for the high voltage region is performed together wit either the N type or P type field implant 8 described above, as appropriate, depending on the Dupont 9 type of the high voltage region.
Figure ye illustrates the semiconductor structure I after the formation of the N well mask, N well implant, 12 and removal of the N well mask; formation of the P well 13 mask, P well implant, and removal of the P well mask, and 14 formation of the high voltage region mask, high voltage region implant, and removal of the high voltage region 16 mask.
17 As shown in Fig. of, the do pants in the N well and P
18 well and high voltage region implants are then diffused 19 into substrate 60 by subjecting the wafer to an oxygen atmosphere at about 1150C for approximately 8 to 12 21 hours, which also forms a field oxide layer 101 with a 22 thickness of about Lowe. The field oxide 101 is then 23 further grown in a wet oxygen ambient at approximately 24 1000C for approximately 2 to 4 hours to a final thickness of about 6,000 to Lowe. Field oxide 101 serves as 26 electrical isolation between adjacent active areas formed 27 within substrate 60. Fig. of shows the semiconductor 28 structure after field oxidation with N well 71, high 29 voltage resin 68 and P well 65 formed in the substrate.
30 The dotted line around the high voltage region 68 in Fig.
31 I indicates that this region may be the substrate itself 32 if no high voltage region implant is employed.
33 Nitride layer 62 is then removed, for example using a 34 phosphoric acid wet etch or a CF4 plasma etch, in order to 35 form the semiconductor structure in Fig. 7g with nitride 36 layer 62 removed from the active areas. The base oxide 61 37 is then stripped from the active regions, for example by I
etching with buffered HO, and a layer of gate oxide 102 is formed over the entire semiconductor structure to a thick-3 news within the range of approximately AYE as shown 4 in Fig. oh, for example by thermal oxidation in dry oxygen with approximately 3% Hal at approximately 900C for 6 approximately 90 minutes. If desired, after formation of 7 gate oxide layer 102, appropriate threshold adjustment 8 implants are pexfonmed, as is well known in the art.
9 Polycrystalline silicon layer 103 (shown in Fig. I) 0 is then deposited to a thickness of approximately AYE
over the entire semiconductor structure, for example by low pressure chemical vapor deposition. Polycrystalline 13 silicon layer 103 serves as electrical interconnect, 4 device gate areas, and capacitor electrodes. Polycrys-Tulane silicon layer 103 is doped with phosphorous to 16 decrease sheet resistance to approximately 20 to 30 ohms/
17 square-18 As shown infix 7j, using photo resist and well-known 19 photolithigraphic and etching techniques (for example etching with CF4 plasma), gates 121, 122 and 123 for 21 active devices in the N well 71, high voltage region 68, 22 and P well 65 and doped polycrystalline silicon intercom-23 newts snot shown) are then formed.
I
Second Embodiment v, According to a second method for forming the separately 27 implanted well regions of this invention in which adjacent 28 well regions are automatically self-aligned, base oxide 29 layer 61 and nitride Lowry shown in Fig. pa are then 30 patterned to define one of the well regions of the device.
31 Referring to jig. pa, this patterning is accomplished by 32 spinning onto nitride layer 62 photo resist 63 which is 33 then soft baked. The first well region mask is then aligned 34 to the wafer and the portions of photo resist exposed by -the 35 mask are subjected to actinic radiation. Exposed portions 36 64 of the photo resist are then removed as shown in fig. pa.
37 Photo resist 63 it then hard baked so that it is not .
. ,..
~3~'7~'7 I
1 affected by the enchants which will be used to remove the 2 unmasked regions of nitride and oxide. Typically, plasma 3 etching is then used to remove the unmasked regions of -4 nitride, and buffered HO is used to remove the regions of oxide as shown in Fig. 8b.
6 A p well implant 65 is performed using boron at a 7 dosage of approximately 6X1012 ions/cm2 at an energy level 8 of approximately 120 Cove 9 As shown in Fig. 8c, photo resist I is then removed.
As shown in Figure Ed, following the doping of P well 11 65, a layer of oxide 66 is formed on the exposed region 12 and the do pants in P-well 65 are simultaneously slightly 13 diffused into substrate 60 by subjecting the wafer to an 14 oxygen atmosphere within the range of approximately 900 to 1000C for approximately 1-3 hours, which forms oxide 16 layer 66 to a thickness of approximately OKAY.
17 As shown in Figure ye, after formation of oxide 66, a 18 second layer of photo resist aye and 67b is applied and 19 patterned Jo expose the area where the second well region will be foxed. The exposed portions of nitride 62 and 21 oxide 61 are removed (in a manner such as has been pro-22 piously described), exposing the area which will become a 23 second well 68.
24 The formation of this second well demonstrates a significant feature of this self aligned method. On one 26 side, oxide layer 66 rather than the second layer of 27 photo resist 67b serves to define the edge of the second 28 well. Therefore, the edge of the second well 68 is per-29 fectly aligned with the edge of the first well 65 without depending on perfect alignment of photo resist 67b. Thus, 31 problems with prior art alignment of adjacent wells are 32 overcome and yet the process remains simple and inexpensive.
33 In this embodiment, the second well is doped for 34 forming a high voltage device. A high voltage region need not be wormed when the lightly-doped substrate itself has 36 the desired characteristics to serve as the high voltage 37 region. However, if it is desired to adjust the Dupont ...
23 194. Similar, very shallow diffused junctions behave very 24 much like one-sided step junctions. See Grove, swooper, at I pg. 159.
26 Thus low P type impurity concentrations in the substrate 27 40 and region 43, typically of the order of 1 x 1014 to 2.5 28 x 1014 atoms/cm3, permit the formation of active devices in 29 region 43 having high junction breakdown voltages (greater than 20 volts). In another embodiment, region 43 is simply 31 a portion of the substrate 40.
32 N well 41 it an N type region formed in substrate 40, 33 typically by ion implantation, having moderate to heavy 34 Dupont levels of an N type material, for example, within the range of approximately 8 x 1014 to 3 x 1016 atoms/cm3.
36 Alternatively, well known diffusion processes can be used 37 for form N well 41. The N well 41 is suitable for the I
g 1 formation of low voltage devices, for example P channel 2 transistors resistors or diodes (not shown).
3 P well 42 is a region of moderate to heavily doped P
4 type semi conductive material formed (typically by ion S implantation or diffusion) in the substrate 40. The P
type Dupont concentration in P well 42 ranges from approxi-7 mutely 8 x oily to 3 x 1016 atoms/cm3. P well 42 is 8 suitable for the formation of low voltage devices, for 9 example resistors, diodes, or N channel transistors P well 42 and N well 41 of Fig. 5 are doped indepen-11 deftly to achieve desired electrical characteristics, e.g.
12 threshold voltages, which depend on Dupont levels, of the I P channel and N channel devices formed therein. Region 43 14 s a lightly doped region of P type semi conductive material Typically the Dupont level in region 43 is within the 16 range of approximately 1 x 1014 to 4 x 1014 or more P type 17 atoms/cm3 and is thus suitable for the formation of devices 18 having high junction breakdown voltages (greater than 20 19 Yolks) in close proximity to the low voltage devices formed in P well 42 and N well 41.
21 The above embodiment uses a type substrate. An N
22 type substrate can also be used, where well region 43 is 23 of P type conductivity. However when an N type substrate 24 it used, it should be noted that generally lower impurity I concentrations produce the same resistivity, as shown in 26 Grove, swooper, at page 113. For example, a substrate 27 resistivity of 10 to 50 ohm-cm corresponds to an N type 28 impurity concentration of approximately 4 x 1014 to 29 1 x oily atoms/cm3.
It is also important to note that the arrangement of 31 the regions 41, 42, and 43 shown in Fig. 5 is not critical.
32 For example in another embodiment, as shown in Fig. 6, 33 N well 51 and region 53 are separated by P well 52. In 34 this embodiment, region So has the same conductivity type as the substrate So and a conduc~iviky of the same order 36 of magnitude as substrate 50.
...._ CMP/5360-lCN
One process for forming a truly CMOS structure according to the present invention is illustrated in Figs. pa through 7j. Another begins with Fig. pa and moves 4 to Figs. aye. In either case, the process begins with a lightly doped substrate 60 of either N type or P type. When 6 substrate 60 is P type, a Dupont concentration of 8 approximately 1x101~ atoms/cm3 is typical. An N type substrate would have a lower Dupont concentration.
9 Fig pa shows a lightly doped semiconductor structure with a base oxide layer and a nitride layer formed 11 thereon. Base oxide layer 61 is formed on substrate 60 to a 12 thickness within the range of approximately 500 to Lowe, 13 for example by thermal oxidation at approximately 100CC for 14 approximately 45 to 75 minutes in an atmosphere of 2 + 3 HAL.
16 Nitride layer 62 is formed on base oxide layer 61 using, 17 for example, low pressure chemical vapor deposition (LPCVD) I to a thickness of approximately ls00A. Oxide 61 separates 19 nitride 62 from substrate 60 and thus allows nitride 62 to be completely removed at a later stage.
22 First Embodiment 23 According to one method for forming the separately 24 implanted well regions of this invention, base oxide 61 and nitride layer 62 shown in Fig. pa are then patterned to 26 define the active regions of the device shown in Fig. 7b.
27 The active regions remain covered by oxide 61 and nitride 62 while the adjacent field regions are exposed. This patterning is accomplished by spinning photo resist 81 onto nitride 62 which is then soft baked. The field mask is then 31 aligned to the wafer flat and the portions of photo resist 32 exposed by the mask are subjected to actinic radiation.
33 Exposed portions of photo resist 81 are then removed by 3 development. Photo resist 81 is then hard baked so that it is not affected by the enchants used to remove the unmasked I regions of nitride and oxide. Typically, plasma etching is used to remove the unmasked regions of CMP/5360-lCN
nitride and buffered HO is used to remove the regions of 2 oxide. The remaining portions of photo resist 81 are removed 3 after the etching step in order to produce the structure 4 shown in Fig. 7c. As will be appreciated by those of ordinary skill in the art, if desired, the photo resist 81 and masking to define active area live.; those areas located 7 in substrate 60 beneath portions of oxide 61 and nitride 62 8 which remain in the structure of Fig. 7c) can be postponed 9 until after formation of all desired well regions A P well mask of photo resist 82 is formed on the 11 structure of Fig. 7c which exposes the P well (N channel) 12 field and active regions 65. At this stage, the field 13 regions are fully exposed and the active regions are partly 14 protected by the nitride/oxide sandwich 61, 62 as shown in Fig. Ed.
16 A field implant of P type do pants is then accomplished 17 using boron at a dosage of approximately 3X1013 ions/cm2 and I an energy level of approximately 25 Key. This step implants 19 a shallow boron charge into the field regions which raises the field inversion potential, hence preventing parasitic 21 field devices.
22 Next, a P-well implant is performed using Boron at a 23 dosage of approximately 6X1012 ions/cm2 at an energy level 24 of approximately 120 Key, which is sufficient that the P
I well is implanted through the nitride/oxide layer.
26 As shown in Fig. ye, similarly, an N well mask of 27 photo resist is used to expose N well UP channel) field and active regions 71. A field implant of N type do pants is 29 then accomplished using phosphorus. The N well implant is performed using phosphorus at a dosage of approximately 31 2X1012 ions/cm2 at an energy of approximately 150 Key.
32 A high voltage region mask need not be formed when the 33 lightly doped substrate itself serves as the high voltage 34 region. However, if it is desired to adjust the Dupont type or the Dupont concentration in the high voltage region, a 36 high voltage region mask (not shown) is formed using 37 photo resist in order to expose field and active 1 regions 68 for high voltage devices. This step is follow-2 Ed by a high voltage region implant using a selected 3 impurity type. For example, for a P type high voltage 4 region, a Dupont concentration of approximately 1x1014 to 4xlol4 P type atoms/cm3 is used. In one embodiment, the 6 field implant for the high voltage region is performed together wit either the N type or P type field implant 8 described above, as appropriate, depending on the Dupont 9 type of the high voltage region.
Figure ye illustrates the semiconductor structure I after the formation of the N well mask, N well implant, 12 and removal of the N well mask; formation of the P well 13 mask, P well implant, and removal of the P well mask, and 14 formation of the high voltage region mask, high voltage region implant, and removal of the high voltage region 16 mask.
17 As shown in Fig. of, the do pants in the N well and P
18 well and high voltage region implants are then diffused 19 into substrate 60 by subjecting the wafer to an oxygen atmosphere at about 1150C for approximately 8 to 12 21 hours, which also forms a field oxide layer 101 with a 22 thickness of about Lowe. The field oxide 101 is then 23 further grown in a wet oxygen ambient at approximately 24 1000C for approximately 2 to 4 hours to a final thickness of about 6,000 to Lowe. Field oxide 101 serves as 26 electrical isolation between adjacent active areas formed 27 within substrate 60. Fig. of shows the semiconductor 28 structure after field oxidation with N well 71, high 29 voltage resin 68 and P well 65 formed in the substrate.
30 The dotted line around the high voltage region 68 in Fig.
31 I indicates that this region may be the substrate itself 32 if no high voltage region implant is employed.
33 Nitride layer 62 is then removed, for example using a 34 phosphoric acid wet etch or a CF4 plasma etch, in order to 35 form the semiconductor structure in Fig. 7g with nitride 36 layer 62 removed from the active areas. The base oxide 61 37 is then stripped from the active regions, for example by I
etching with buffered HO, and a layer of gate oxide 102 is formed over the entire semiconductor structure to a thick-3 news within the range of approximately AYE as shown 4 in Fig. oh, for example by thermal oxidation in dry oxygen with approximately 3% Hal at approximately 900C for 6 approximately 90 minutes. If desired, after formation of 7 gate oxide layer 102, appropriate threshold adjustment 8 implants are pexfonmed, as is well known in the art.
9 Polycrystalline silicon layer 103 (shown in Fig. I) 0 is then deposited to a thickness of approximately AYE
over the entire semiconductor structure, for example by low pressure chemical vapor deposition. Polycrystalline 13 silicon layer 103 serves as electrical interconnect, 4 device gate areas, and capacitor electrodes. Polycrys-Tulane silicon layer 103 is doped with phosphorous to 16 decrease sheet resistance to approximately 20 to 30 ohms/
17 square-18 As shown infix 7j, using photo resist and well-known 19 photolithigraphic and etching techniques (for example etching with CF4 plasma), gates 121, 122 and 123 for 21 active devices in the N well 71, high voltage region 68, 22 and P well 65 and doped polycrystalline silicon intercom-23 newts snot shown) are then formed.
I
Second Embodiment v, According to a second method for forming the separately 27 implanted well regions of this invention in which adjacent 28 well regions are automatically self-aligned, base oxide 29 layer 61 and nitride Lowry shown in Fig. pa are then 30 patterned to define one of the well regions of the device.
31 Referring to jig. pa, this patterning is accomplished by 32 spinning onto nitride layer 62 photo resist 63 which is 33 then soft baked. The first well region mask is then aligned 34 to the wafer and the portions of photo resist exposed by -the 35 mask are subjected to actinic radiation. Exposed portions 36 64 of the photo resist are then removed as shown in fig. pa.
37 Photo resist 63 it then hard baked so that it is not .
. ,..
~3~'7~'7 I
1 affected by the enchants which will be used to remove the 2 unmasked regions of nitride and oxide. Typically, plasma 3 etching is then used to remove the unmasked regions of -4 nitride, and buffered HO is used to remove the regions of oxide as shown in Fig. 8b.
6 A p well implant 65 is performed using boron at a 7 dosage of approximately 6X1012 ions/cm2 at an energy level 8 of approximately 120 Cove 9 As shown in Fig. 8c, photo resist I is then removed.
As shown in Figure Ed, following the doping of P well 11 65, a layer of oxide 66 is formed on the exposed region 12 and the do pants in P-well 65 are simultaneously slightly 13 diffused into substrate 60 by subjecting the wafer to an 14 oxygen atmosphere within the range of approximately 900 to 1000C for approximately 1-3 hours, which forms oxide 16 layer 66 to a thickness of approximately OKAY.
17 As shown in Figure ye, after formation of oxide 66, a 18 second layer of photo resist aye and 67b is applied and 19 patterned Jo expose the area where the second well region will be foxed. The exposed portions of nitride 62 and 21 oxide 61 are removed (in a manner such as has been pro-22 piously described), exposing the area which will become a 23 second well 68.
24 The formation of this second well demonstrates a significant feature of this self aligned method. On one 26 side, oxide layer 66 rather than the second layer of 27 photo resist 67b serves to define the edge of the second 28 well. Therefore, the edge of the second well 68 is per-29 fectly aligned with the edge of the first well 65 without depending on perfect alignment of photo resist 67b. Thus, 31 problems with prior art alignment of adjacent wells are 32 overcome and yet the process remains simple and inexpensive.
33 In this embodiment, the second well is doped for 34 forming a high voltage device. A high voltage region need not be wormed when the lightly-doped substrate itself has 36 the desired characteristics to serve as the high voltage 37 region. However, if it is desired to adjust the Dupont ...
-15-type or the Dupont concentration in the high voltage region, exposed high voltage region 68 may be implanted 3 using a selected impurity type as shown in Fig. ye. For 4 example, for a P-type high voltage region, a final Dupont concentration of approximately 1x1014 to 4X1014 atoms/cm3 6 is used.
As shown in Figure of, after implantation, as with 8 the P well do pants, high voltage region do pants are slightly I diffused and oxide 69 grown on the exposed area. The same lo conditions described above for growing oxide on the P well 11 will result in fast growth of oxide on the exposed high 2 voltage region and much slower thickening of the existing 3 oxide above the P well. This is because oxide growth is 14 highly nonlinear, depending on the proximity of silicon atoms and oxygen atoms to each other.
As shown in Figure of, after implantation, as with 8 the P well do pants, high voltage region do pants are slightly I diffused and oxide 69 grown on the exposed area. The same lo conditions described above for growing oxide on the P well 11 will result in fast growth of oxide on the exposed high 2 voltage region and much slower thickening of the existing 3 oxide above the P well. This is because oxide growth is 14 highly nonlinear, depending on the proximity of silicon atoms and oxygen atoms to each other.
16 As shown in Figure 8g, oxide and nitride are then
17 removed from the area adjacent to high voltage well 68
18 where N well 71 is to be formed. An N-type Dupont such as
19 phosphorus is then used to provide a low energy implant at a dosage of approximately 5 x 1012 ions/cm2 at an energy 21 level of approximately 25 Key. The do pants in well regions 22 65, 68 and 71 are now diffused to their desired junction 23 depth of approximately 3 to 6 microns, for example by heat-24 in the wafer in a dry oxygen atmosphere at approximately 1150C or approximately 8 to 12 hours, thus forming oxide I 72 to a thickness of approximately Lowe.
27 Alternatively, if desired, portions of oxide 61 and 28 nitride 52 need not be removed from the area adjacent to I high voltage well 68 where N well 71 is to be formed. In this event, an N type Dupont such as phosphorous is used 31 to provide an implant through oxide 61 and nitride 62 I covering to be formed N well 71. At this time, thick 33 oxide layers 66 and 69 serve as a mask. After implantation, 34 the device is heated in order to diffuse the do pants to form N well 71 as shown in Figure oh. Since nitride layer 36 62 remains, thick oxide layer 72 shown in Figure oh is not 37 formed above well region 71. Using appropriate and well I
. .
., ,, _ . .
known techniques, nitride layer 62 and oxide layers 61, 69 and 66 are then removed, and further processing as described 3 below provides the structure shown in Figure 9.
4 Note that three types of wells have thus been formed using only two photo resist masks 63 and Ahab, and that it 6 was not necessary to align the edge of one photo resist mask with the edge of a previous mask. Thus, a simpler manufacturing process with automatic self-alignment has 9 been achieved.
Optionally, oxide 72 may be grown to diffuse well 71 11 to the depth of wells 68 and 65. Oxide layers 66, 64 and 12 72 are then removed, leaving a truly substrate for 13 device formation having good plenarily and sharply defined 14 well regions.
Fig. oh shows the semiconductor structure after 16 oxidation, leaving N well 71, high voltage region 68 and P
I well 65 formed in the substrate. The dotted line around 18 the high voltage region 68 in Fig. oh indicates that this 19 region may be the substrate itself if no high voltage region implant is employed Oxide layers 66, 69 and 72 I are then removed using, for example, buffered HO, and devices are formed in well regions 65, 68 and 71 in a 23 well-known manner.
24 An alternative embodiment shown in Figure 8j provides a structure having two implanted and diffused wells 65, 26 68, and which uses substrate 60 as the high voltage region I without requiring an implant in the high voltage region.
28 In this alternative embodiment, after forming oxide layer 29 66 as shown in Figure Ed, and applying photo resist aye, I 67b, as shown in Figure ye, implantation is then performed 31 through oxide nitride layers 61 and 62 to form implanted 32 well region 68 as shown in Figure I. Well 68 is automatic 33 gaily self aligned with well 65. Subsequent heating to a 34 temperature of approximately 1,150C for approximately 8 35 to 12 hours diffuses implanted well 68. The layers of 36 nitride 62, thick oxide 66 and thin oxide 61 are then 37 removed to produce the substrate of Figure 8j having three .... .
I
~17-1 regions for forming active devices: implanted well 65, 2 implanted well 68, and substrate region 60 which is appear-3 private for high voltage devices.
4 As will also be appreciated by those who are skilled in the art in light of the teachings of this invention, it 6 is also possible to implant well region 68 by first removing 7 nitride layer 62. In this event, during the diffusion ox implanted do pants in well region 68, an additional thick 9 oxide layer is formed over N well 68. This thick oxide is then simultaneously removed with the removal of thick 11 oxide layer I
13 Device Formed Using This Invention 14 Regardless of which embodiment is used, oxides foxed over well regions and the substrate itself are removed, 16 as is any remaining nitride. A new base oxide layer ~200 17 Jo AYE thick) and a layer of nitride (AYE) is formed 18 thereon. An active area mask, which defines the active 19 regions, is used followed by field implantation and the formation of field oxide (typically Luke thick), as 21 is known in the art. The initial base oxide/nitride layer 22 is removed, and a gate dielectric is formed.
23 Figs. 9-11 show formation of a portion of a typical 24 circuit using the truly substrate just described after 2$ formation by any of the method embodiments which have been 26 described in detail. Thick oxide 101 is formed at the 27 boundaries between one well and the next to prevent format I lion of parasitic current paths between one active device 29 and the next. A thinner portion of oxide 102 for insular 30 lion purpose is formed over the centers of each well 31 region.
32 A polycrystalline silicon layer is then deposited as 33 described earlier and gates 121, 122 and 123 for active 34 devices in N well 71, high voltage region 68, and P well 65 and doped polycrystalline silicon interconnects (not 36 shown) are then formed.
.... _ l Source and drain regions 145 (shown in Fig. lo are 2 formed in N well 71 by forming a P type source/drain 3 mask 130 (shown in Fig. 9) of photo resist which exposes 4 the regions where P type boron ions are to be implanted to form source/drain regions. The boron implant is performed 6 using a dosage of 3xlol5 ions/cm2 at an energy level of 7 approximately 50 Rev. If the high voltage region 68 is 8 also N-type, boron mask 130 also expose; the high voltage 9 region.
Similarly, N+ source and drain regions are formed in 11 p well 65 by forming an N+ source/drain mask of photo-12 resist snot shown) which exposes the regions where No type 13 ions are to be implanted. The N+ implant can be performed 14 using a dosage of approximately 5xlol5 phosphorous ions/cm2 at an energy level of approximately 75 Key. If the high 16 voltage region 68 is also P type, the N+ source/drain 17 implant for -the high voltage region 68 is accomplished at 18 the same time that the No source/drain regions are formed 19 yin P well 65.
After the source and drain implants, the wafer is 21 subjected to an 2 ambient at approximately 900C to 22 1000C to achieve appropriate junction depth of approxi-23 mutely 0.3 microns. During this process approximately 24 AYE of oxide is grown on the source/drain regions. The resulting semiconductor structure shown in Fig. 9, has Pi 26 N well source and drain regions 145, N+ P well source and 27 drain regions 146 and source and drain regions 147 of a 28 selected conductivity type in high voltage region 68.
29 Standard processing techniques are employed to come 30 plate the formation of active devices on regions I 68, 31 and 71 to produce a device such as shown in Fig. lo with 32 first metal contact layer AL-l, second metal layer AL-2, 33 first POX layer PVX~l and second POX layer PVX-2.
34 The above embodiments are intended to be exemplary 35 and not limiting, and in view of the above disclosure, 36 many substitutions and modifications will be obvious to 37 one of average skill in the art without departing from the 9 -) I
l spirit and scope of the invention. As but one example, as 2 will be readily recognized by one of ordinary skill in the 3 art in light of the teachings of this invention, the well 4 regions can be formed first, and the field implants formed thereafter. As another example, it would of course be 6 possible to form more than three regions, providing, for 7 one example, two high voltage regions of opposite conduct 8 tivity type. us yet another example, the second well can 9 be formed not adjacent to the first well, photo resist serving to mark both boundaries of the second well. After 11 forming of thick oxide on this second well; thick idea 12 over the first and second wells then defines both boundaries 13 of a third well.
16 I`
I
26 .
I
27 Alternatively, if desired, portions of oxide 61 and 28 nitride 52 need not be removed from the area adjacent to I high voltage well 68 where N well 71 is to be formed. In this event, an N type Dupont such as phosphorous is used 31 to provide an implant through oxide 61 and nitride 62 I covering to be formed N well 71. At this time, thick 33 oxide layers 66 and 69 serve as a mask. After implantation, 34 the device is heated in order to diffuse the do pants to form N well 71 as shown in Figure oh. Since nitride layer 36 62 remains, thick oxide layer 72 shown in Figure oh is not 37 formed above well region 71. Using appropriate and well I
. .
., ,, _ . .
known techniques, nitride layer 62 and oxide layers 61, 69 and 66 are then removed, and further processing as described 3 below provides the structure shown in Figure 9.
4 Note that three types of wells have thus been formed using only two photo resist masks 63 and Ahab, and that it 6 was not necessary to align the edge of one photo resist mask with the edge of a previous mask. Thus, a simpler manufacturing process with automatic self-alignment has 9 been achieved.
Optionally, oxide 72 may be grown to diffuse well 71 11 to the depth of wells 68 and 65. Oxide layers 66, 64 and 12 72 are then removed, leaving a truly substrate for 13 device formation having good plenarily and sharply defined 14 well regions.
Fig. oh shows the semiconductor structure after 16 oxidation, leaving N well 71, high voltage region 68 and P
I well 65 formed in the substrate. The dotted line around 18 the high voltage region 68 in Fig. oh indicates that this 19 region may be the substrate itself if no high voltage region implant is employed Oxide layers 66, 69 and 72 I are then removed using, for example, buffered HO, and devices are formed in well regions 65, 68 and 71 in a 23 well-known manner.
24 An alternative embodiment shown in Figure 8j provides a structure having two implanted and diffused wells 65, 26 68, and which uses substrate 60 as the high voltage region I without requiring an implant in the high voltage region.
28 In this alternative embodiment, after forming oxide layer 29 66 as shown in Figure Ed, and applying photo resist aye, I 67b, as shown in Figure ye, implantation is then performed 31 through oxide nitride layers 61 and 62 to form implanted 32 well region 68 as shown in Figure I. Well 68 is automatic 33 gaily self aligned with well 65. Subsequent heating to a 34 temperature of approximately 1,150C for approximately 8 35 to 12 hours diffuses implanted well 68. The layers of 36 nitride 62, thick oxide 66 and thin oxide 61 are then 37 removed to produce the substrate of Figure 8j having three .... .
I
~17-1 regions for forming active devices: implanted well 65, 2 implanted well 68, and substrate region 60 which is appear-3 private for high voltage devices.
4 As will also be appreciated by those who are skilled in the art in light of the teachings of this invention, it 6 is also possible to implant well region 68 by first removing 7 nitride layer 62. In this event, during the diffusion ox implanted do pants in well region 68, an additional thick 9 oxide layer is formed over N well 68. This thick oxide is then simultaneously removed with the removal of thick 11 oxide layer I
13 Device Formed Using This Invention 14 Regardless of which embodiment is used, oxides foxed over well regions and the substrate itself are removed, 16 as is any remaining nitride. A new base oxide layer ~200 17 Jo AYE thick) and a layer of nitride (AYE) is formed 18 thereon. An active area mask, which defines the active 19 regions, is used followed by field implantation and the formation of field oxide (typically Luke thick), as 21 is known in the art. The initial base oxide/nitride layer 22 is removed, and a gate dielectric is formed.
23 Figs. 9-11 show formation of a portion of a typical 24 circuit using the truly substrate just described after 2$ formation by any of the method embodiments which have been 26 described in detail. Thick oxide 101 is formed at the 27 boundaries between one well and the next to prevent format I lion of parasitic current paths between one active device 29 and the next. A thinner portion of oxide 102 for insular 30 lion purpose is formed over the centers of each well 31 region.
32 A polycrystalline silicon layer is then deposited as 33 described earlier and gates 121, 122 and 123 for active 34 devices in N well 71, high voltage region 68, and P well 65 and doped polycrystalline silicon interconnects (not 36 shown) are then formed.
.... _ l Source and drain regions 145 (shown in Fig. lo are 2 formed in N well 71 by forming a P type source/drain 3 mask 130 (shown in Fig. 9) of photo resist which exposes 4 the regions where P type boron ions are to be implanted to form source/drain regions. The boron implant is performed 6 using a dosage of 3xlol5 ions/cm2 at an energy level of 7 approximately 50 Rev. If the high voltage region 68 is 8 also N-type, boron mask 130 also expose; the high voltage 9 region.
Similarly, N+ source and drain regions are formed in 11 p well 65 by forming an N+ source/drain mask of photo-12 resist snot shown) which exposes the regions where No type 13 ions are to be implanted. The N+ implant can be performed 14 using a dosage of approximately 5xlol5 phosphorous ions/cm2 at an energy level of approximately 75 Key. If the high 16 voltage region 68 is also P type, the N+ source/drain 17 implant for -the high voltage region 68 is accomplished at 18 the same time that the No source/drain regions are formed 19 yin P well 65.
After the source and drain implants, the wafer is 21 subjected to an 2 ambient at approximately 900C to 22 1000C to achieve appropriate junction depth of approxi-23 mutely 0.3 microns. During this process approximately 24 AYE of oxide is grown on the source/drain regions. The resulting semiconductor structure shown in Fig. 9, has Pi 26 N well source and drain regions 145, N+ P well source and 27 drain regions 146 and source and drain regions 147 of a 28 selected conductivity type in high voltage region 68.
29 Standard processing techniques are employed to come 30 plate the formation of active devices on regions I 68, 31 and 71 to produce a device such as shown in Fig. lo with 32 first metal contact layer AL-l, second metal layer AL-2, 33 first POX layer PVX~l and second POX layer PVX-2.
34 The above embodiments are intended to be exemplary 35 and not limiting, and in view of the above disclosure, 36 many substitutions and modifications will be obvious to 37 one of average skill in the art without departing from the 9 -) I
l spirit and scope of the invention. As but one example, as 2 will be readily recognized by one of ordinary skill in the 3 art in light of the teachings of this invention, the well 4 regions can be formed first, and the field implants formed thereafter. As another example, it would of course be 6 possible to form more than three regions, providing, for 7 one example, two high voltage regions of opposite conduct 8 tivity type. us yet another example, the second well can 9 be formed not adjacent to the first well, photo resist serving to mark both boundaries of the second well. After 11 forming of thick oxide on this second well; thick idea 12 over the first and second wells then defines both boundaries 13 of a third well.
16 I`
I
26 .
I
Claims (23)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor structure comprising:
a substrate of a first conductivity type;
a first well, formed within said substrate, of said first conductivity type having greater conductivity than said substrate;
a second well, formed within said substrate, of a second conductivity type opposite said first conductivity type having greater conductivity than said substrate; and a third well being a high voltage region in said substrate of either said first conductivity type or said second conductivity type having a conductivity of the same order of magnitude as said substrate for the formation of devices having high junction break-down voltages, and in which the edges of said first, second and third wells are automatically self-aligned.
a substrate of a first conductivity type;
a first well, formed within said substrate, of said first conductivity type having greater conductivity than said substrate;
a second well, formed within said substrate, of a second conductivity type opposite said first conductivity type having greater conductivity than said substrate; and a third well being a high voltage region in said substrate of either said first conductivity type or said second conductivity type having a conductivity of the same order of magnitude as said substrate for the formation of devices having high junction break-down voltages, and in which the edges of said first, second and third wells are automatically self-aligned.
2. Structure in Claim 1 wherein said third well is of said first conductivity type.
3. Structure in Claim 1 wherein said third well is of said second conductivity type.
4. Structure in Claim 1 wherein said third well is a portion of said substrate.
5. Structure in Claim 1 wherein the resistivity of -20a-said substrate is in the range of approximately 30 to 100 ohm-cm.
6. Structure in Claim 1 further comprising a first transistor having a gate, and having a source and a drain formed in said first well;
a second transistor having a gate, and having a source and a drain formed in said second well; and a third transistor having a gate, and having a source and a drain formed in said third well.
a second transistor having a gate, and having a source and a drain formed in said second well; and a third transistor having a gate, and having a source and a drain formed in said third well.
7. Structure in Claim 1 wherein said substrate is silicon and contains approximately 1 x 1014 to 2.5 x 1014 atoms/cm3 of P type dopants, said first well contains a concentration of approximately 8 x 1014 to 3 x 1016 atoms/cm3 of P type dopants, said second well contains a concentration of approximately 8 x 1014 to 3 x 1016 atoms/cm3 of N type dopants and said third well contains approximately 1 x 1014 to 4 x 1014 atoms/cm3 of P type dopants.
8. Structure in Claim 7 wherein said high junction breakdown voltages are greater than approximately 20 volts.
9. A method of forming wells in a semiconductor substrate comprising:
depositing a thin layer of oxide on said substrate, depositing a layer of silicon nitride on said thin layer of oxide, initiating a process to be repeated at least two times in the stated order of:
applying a layer of photoresist, removing portions of said photoresist, thereby expos-ing portions of said silicon nitride, removing exposed portions of said silicon nitride and thin oxide, thus creating exposed portions of said semiconduc-tor substrate, implanting dopants of a selected conductivity type to a selected concentration into said exposed portions of said semiconductor substrate, thereby forming a well of said selected conductivity type having a breakdown voltage determined by said selected concentration, oxidizing said exposed portions of semiconductor substrate thus creating protective thick oxide over said exposed portions and diffusing said dopants into said semiconductor substrate, and after sufficient repetition of said process, when the desired number of regions have been formed, removing said protective thick oxide.
depositing a thin layer of oxide on said substrate, depositing a layer of silicon nitride on said thin layer of oxide, initiating a process to be repeated at least two times in the stated order of:
applying a layer of photoresist, removing portions of said photoresist, thereby expos-ing portions of said silicon nitride, removing exposed portions of said silicon nitride and thin oxide, thus creating exposed portions of said semiconduc-tor substrate, implanting dopants of a selected conductivity type to a selected concentration into said exposed portions of said semiconductor substrate, thereby forming a well of said selected conductivity type having a breakdown voltage determined by said selected concentration, oxidizing said exposed portions of semiconductor substrate thus creating protective thick oxide over said exposed portions and diffusing said dopants into said semiconductor substrate, and after sufficient repetition of said process, when the desired number of regions have been formed, removing said protective thick oxide.
10. A method for forming wells in a semiconductor substrate as in Claim 9, where said process to be repeated at least two times is repeated three times.
11. A method for forming wells in a semiconductor substrate as in Claim 9, wherein said first conductivity type is N and said second conductivity type is P.
12. A method for forming wells in a semiconductor substrate as in Claim 9 wherein said first conductivity type is P and said second conductivity type is N.
13. A method for forming wells in a semiconductor substrate as in Claim 11 wherein said dopants of said first conductivity type are phosphorous and said dopants of said second conductivity type are boron.
14. A method for forming wells in a semiconductor substrate as in Claim 12 wherein said dopants of said first conductivity type are boron and said dopants of said second conductivity type are phosphorous.
15. A method for forming wells in a semiconductor substrate as in Claim 9 where in subsequent repetitions of said process, said step of removing portions of said photoresist may also expose portions of said protective thick oxide, thus providing automatic alignment of adjacent wells.
16. A method of forming wells in a semiconductor substrate comprising:
depositing a thin layer of oxide on said substrate, depositing a layer of silicon nitride on said thin layer of oxide, initiating a process to be repeated at least one time of:
applying a layer of photoresist, removing portions of said photoresist, thereby exposing portions of said silicon nitride, removing exposed portions of said silicon nitride and thin oxide, thus creating exposed portions of said semiconductor substrate, implanting dopants of a selected conductivity type to a selected concentration into said exposed portions of said semiconductor substrate, thereby forming a well of said selected conductiv-ity type having a breakdown voltage determined by said selected concentration, oxidizing said exposed portions of semicon-ductor substrate, thus creating protective thick oxide over said exposed portions and diffusing said dopants into said semiconductor substrate, and after sufficient repetition of said process, when one well region remains to be formed, applying a layer of photoresist, removing portions of said photoresist, thereby creating exposed portions of said silicon nitride, implanting through said exposed portions of silicon nitride and said thin layer of oxide dopants of a selected conductivity type to a selected concentration into said semiconductor substrate, thereby forming a well of said selected conductivity type having a breakdown voltage determined by said selected concentration, diffusing said dopants of a selected conduc-tivity type into said semiconductor substrate, removing said layer of silicon nitride and said thin and thick layers of oxide.
depositing a thin layer of oxide on said substrate, depositing a layer of silicon nitride on said thin layer of oxide, initiating a process to be repeated at least one time of:
applying a layer of photoresist, removing portions of said photoresist, thereby exposing portions of said silicon nitride, removing exposed portions of said silicon nitride and thin oxide, thus creating exposed portions of said semiconductor substrate, implanting dopants of a selected conductivity type to a selected concentration into said exposed portions of said semiconductor substrate, thereby forming a well of said selected conductiv-ity type having a breakdown voltage determined by said selected concentration, oxidizing said exposed portions of semicon-ductor substrate, thus creating protective thick oxide over said exposed portions and diffusing said dopants into said semiconductor substrate, and after sufficient repetition of said process, when one well region remains to be formed, applying a layer of photoresist, removing portions of said photoresist, thereby creating exposed portions of said silicon nitride, implanting through said exposed portions of silicon nitride and said thin layer of oxide dopants of a selected conductivity type to a selected concentration into said semiconductor substrate, thereby forming a well of said selected conductivity type having a breakdown voltage determined by said selected concentration, diffusing said dopants of a selected conduc-tivity type into said semiconductor substrate, removing said layer of silicon nitride and said thin and thick layers of oxide.
17. A method for forming wells in a semiconductor substrate as in claim 16, where said process to be repeated at least one time is repeated one time.
18. A method for forming wells in a semiconductor substrate as in claim 16, where said process to be repeated at least one time is repeated two times.
19. A method for forming wells in a semiconductor substrate as in claim 16, where said first conductivity type is N and said second conductivity type is P.
20. A method for forming wells in a semiconductor substrate as in claim 16, wherein said first conductivity type is P and second conductivity type is N.
21. A method for forming wells in a semiconductor substrate as in claim 19, wherein said dopants of said first conductivity type are phosphorous and said dopants of said second conductivity type are boron.
22. A method for forming wells in a semiconductor substrate as in claim 20, wherein said dopants of said first conductivity type are boron and said dopants of said second conductivity type are phosphorous.
23. A method for forming wells in a semiconductor substrate as in claim 16, where said steps of removing portions of said photoresist thereby exposing portions of said silicon nitride may also expose portions of said protective thick oxide, thus providing automatic alignment of adjacent wells.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US1985/000990 WO1985005736A1 (en) | 1984-05-25 | 1985-05-22 | Tri-well cmos technology |
| US85/00990 | 1985-05-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1239707A true CA1239707A (en) | 1988-07-26 |
Family
ID=22188700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000486486A Expired CA1239707A (en) | 1985-05-22 | 1985-07-09 | Tri-well cmos technology |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1239707A (en) |
-
1985
- 1985-07-09 CA CA000486486A patent/CA1239707A/en not_active Expired
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