CA1182582A - Semiconductor chip package - Google Patents

Semiconductor chip package

Info

Publication number
CA1182582A
CA1182582A CA000404784A CA404784A CA1182582A CA 1182582 A CA1182582 A CA 1182582A CA 000404784 A CA000404784 A CA 000404784A CA 404784 A CA404784 A CA 404784A CA 1182582 A CA1182582 A CA 1182582A
Authority
CA
Canada
Prior art keywords
conductors
substrate
pattern
chip mounting
mounting surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000404784A
Other languages
English (en)
French (fr)
Inventor
William E. Dougherty
Stuart E. Greer
William T. Norris
William J. Nestork
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1182582A publication Critical patent/CA1182582A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/401Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
CA000404784A 1981-07-22 1982-06-09 Semiconductor chip package Expired CA1182582A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28572581A 1981-07-22 1981-07-22
US285,725 1981-07-22

Publications (1)

Publication Number Publication Date
CA1182582A true CA1182582A (en) 1985-02-12

Family

ID=23095459

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000404784A Expired CA1182582A (en) 1981-07-22 1982-06-09 Semiconductor chip package

Country Status (4)

Country Link
EP (1) EP0070533B1 (enExample)
JP (1) JPS5818951A (enExample)
CA (1) CA1182582A (enExample)
DE (1) DE3277890D1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4674007A (en) * 1985-06-07 1987-06-16 Microscience Corporation Method and apparatus for facilitating production of electronic circuit boards
JPS63245952A (ja) * 1987-04-01 1988-10-13 Hitachi Ltd マルチチップモジュ−ル構造体

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3370203A (en) * 1965-07-19 1968-02-20 United Aircraft Corp Integrated circuit modules
FR1540051A (fr) * 1966-09-21 1968-09-20 Rca Corp Microcircuit et son procédé de fabrication
EP0006444B1 (de) * 1978-06-23 1982-12-22 International Business Machines Corporation Vielschichtiges, dielektrisches Substrat
JPS5612760A (en) * 1979-07-10 1981-02-07 Nec Corp Multi chip lsi package

Also Published As

Publication number Publication date
EP0070533A2 (de) 1983-01-26
DE3277890D1 (en) 1988-02-04
EP0070533A3 (en) 1985-01-30
EP0070533B1 (de) 1987-12-23
JPS5818951A (ja) 1983-02-03
JPS62583B2 (enExample) 1987-01-08

Similar Documents

Publication Publication Date Title
US5935687A (en) Three dimensional package and architecture for high performance computer
US5093708A (en) Multilayer integrated circuit module
US4320438A (en) Multi-layer ceramic package
US5611876A (en) Method of making a multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses
EP0708484B1 (en) Three-dimensional integrated circuit stacking
US4602271A (en) Personalizable masterslice substrate for semiconductor chips
CA1310099C (en) Customizable circuitry
US7045901B2 (en) Chip-on-chip connection with second chip located in rectangular open window hole in printed circuit board
KR100637008B1 (ko) 리세스된 플립-칩 패키지를 위한 인터포저
US5744862A (en) Reduced thickness semiconductor device with IC packages mounted in openings on substrate
US5585675A (en) Semiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs
US4254445A (en) Discretionary fly wire chip interconnection
US4417392A (en) Process of making multi-layer ceramic package
US6297460B1 (en) Multichip module and method of forming same
JP4592122B2 (ja) パッケージ層の数を削減したフリップチップ・パッケージ
JPH0527985B2 (enExample)
US4907128A (en) Chip to multilevel circuit board bonding
US20030165051A1 (en) Modular integrated circuit chip carrier
WO1996002071A1 (en) Packaged integrated circuit
JPH07297354A (ja) 集積回路及び集積回路のピン割り当て方法及び実装方法
CN1268245A (zh) 封装集成电路的系统和方法
US4866841A (en) Integrated circuit chip carrier
EP0166289B1 (en) High density module for semiconductor device chips
CA1182582A (en) Semiconductor chip package
KR20000022977A (ko) 리세스된 플립 칩 패키지를 위한 자동 중계기

Legal Events

Date Code Title Description
MKEC Expiry (correction)
MKEX Expiry