CA1182582A - Semiconductor chip package - Google Patents
Semiconductor chip packageInfo
- Publication number
- CA1182582A CA1182582A CA000404784A CA404784A CA1182582A CA 1182582 A CA1182582 A CA 1182582A CA 000404784 A CA000404784 A CA 000404784A CA 404784 A CA404784 A CA 404784A CA 1182582 A CA1182582 A CA 1182582A
- Authority
- CA
- Canada
- Prior art keywords
- conductors
- substrate
- pattern
- chip mounting
- mounting surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
AN IMPROVED SEMICONDUCTOR CHIP PACKAGE
A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring.
The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by persona-lized surface wiring and preset subsurface conduc-tors.
AN IMPROVED SEMICONDUCTOR CHIP PACKAGE
A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring.
The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by persona-lized surface wiring and preset subsurface conduc-tors.
Description
~L ~
AN IMPROVED SE~IICONDUCTOR CHIP PACK~GE
BAC~GROU~ OF T~IE INVENTION
Thi~ invention relates ~o pack~ging o ~emicon-ductor ahlp~, and more particularly, to a chlp package wherein ~he sub~trate i9 prorided wlth a repea~ing pa~tern of ~onductor ends, with each pattern defining ~ites to p~rmit the reception of a varlety o~ different chip~. The ~onductor ends are wlred to connect both within the ~ame pattern and with adjacent pattern~O Thi~ permits ~he personali-zation o~ a common sub~trate to receive many d~~er ~nt co~bination~ of chip~.
In the evolutlon of semiconductor technology, packag~ng of the chip~ ha~ taken on increasing 1~ lmpoxtanc~. The number o~ circuit3 that can be placed on a chip ha~ drama~ically lncreased a~ has the number of ~unctlon3 o~ any given chipo Thera are chlp~ which are primarily memory, tho~e which are prima.rily logic, and those which are mixed logic and memory. A~ miniaturlzation progres3~s it i5 becomlng increa3lngly de~irable ~o placs a number of dif~erent chip , ana different comblnations of chips onto a ~lngls ~ub~tra~e. Thi~ ~hip/subs~rate pack~ge can bs lnserted a~ a unlt into various piece~ of equipment.
However, wlth prior art t2chnology each module having a di~er~nt combination o~ chlp~ had to h~e a juDstrate designed speci~ically for each combina tion o~ chlps. Indaed, even in a ~ingl~ chip module, each different chip re~uirad a different ~u~3~.rate uni~e to the given ship. Prior art examples o~
~U-9~ 0~7 technolo~y or providing a substrate .or a glven chlp or specific combination of chips i8 repra~ented in U~ S. Patents 4,202,007 and 4"193,802 which xepresent one technology ~or making ~ubstrate~ with buried wiring~ and }B~ Technisal Disclo~ure Bulletin, Vol. 22, i~o. 5 dated Qctober 1979, at pagss 1841-1842, which xepre~ent~ a different technolocJy. This prior art, however J show~ only a technigue for forming substra~e~ which will accept predetermined 0 chip9 OX chip combination~. The nece~sity of design-in~, producing and stoc~piling a different substrate for each chip and ~ach dif~rent combination of chips i~ ~ery expensîve and adds ~igni~icantly to tllf~ cos~ .
SU~ARY OF T~ ~NTIO~L~
According to the pre~ent invention/ a sub~krate ~or packaging semiconductor chip~ i~ provided havlng a chip mounting ~ur~ace. The substrate i5 ~truc-tured with conductors having opposite end~ termina-~ing at ~aid moun~ing sur~ace with intermecl.iateportions connectinrJ the end3 o~ t~e conductor3. Tile encls of the conductor~ are arranged ln repeating pattPrn~ longitudinally along the 3ub~trate separated by ortho~onal strips on the ~urface which are free of conductor ends ~o allow for d~n~e ~urface wlring, The intermediate portions o~ some conductors connect end3 within a pattern and of 30me conductor3 connect end~ in ad~acent pattexns. The conductor ends in each pattern are ~ositioned ~o delinea~e a pluralit~
of chip mounting site3 ha~ing qufficient pacinq between the conductor end3 to per~it the positioning *Registered Trade Mark ~U-9~81~007 of chip mounting means which may be electrically connected to tne end~ of the conductor~ ~y surrace me allization.
In this way a ~ingle 3ub trate can be pexsonal-ized ~o accep~ a plurality of different chlpq at a~ygiven pattern loca~lon and to utili2e two or more locations to mount chip3 with a~propriate connec-kions betwe~n.
The sub~trate of the present lnvention utilize3 subsurface conductor3 to pxovide basic interconnec-~lon within each pattern and be~ween adjacen~ pa~texns and 3urface wlrlng or the uni~ue personalized chip mounting and wiringt DE~CRIPTON OF TH~ DRA~INGS
FIG. l i~ a plan view of a chip pac~age of thi~
invontion ~howing the substrate and chips mounted thereon;
PIG. 2 i3 a ~ectional view taXen ~ub~tantially along the plane designated by line 2-2 o~ FIG. l;
FIG. 3 i3 a ~ectional vi~w taken sub3tantially along the plan~ dQsignated by the line 3-3 o FIG. l;
FIG. 4 1~ a ~ectional vlaw taken sub tantially along the plane designated by the llne 4-4 o~ ~IG. l;
and FIG. 5 i~ a per~pective exploded YieW o ~ome of the laminae utilized to form the ~ub~t~ate oE
FIG. l.
~U-9 81-007 5~
D~SCRIPTI0~ OF T~E PRE~ERR~D ~ODL~NT
Referring now to the drawing, a substrata having two repeating patterns of suxface ter~lnation of conductors i~ sho~n~ I~ is to be under3tood that 5 the substrate could be made lo~ger with additional repeating pattern~, but two are shown for ~he pur~ose of illu.stration.
The su~trate, designatad by the refere~ce charac~er 10, is ~ormed ~rom a plurality of differ ent lam~nae, 12a, 12b, 12c, 12d, some of which are shown ln FIG~ 5. Tha laminae ar~ hin 3hee~s s~f green (uncured~ ceramic or other dielectric material.
Differen~ lamlnae 12a, 12c, and 12d have o~med on their faces ~31ec~rical conduc:tors 14a, 14c, 14 d, respectively. The conduc~ors 14a and l~c are in a pattern that ~tart~ a~ the top edcJe o:f -the lamlna, extends along the a ::e below the top surfacs and xe turn~ again to the top sur~ace. The conductors l~d extend frolll the top surface of the lamlna along 20 ~he ~ace to the bottom surf~ce. Some of the lamillae represented by laminae 12b may have no conductor~
and are to control lateral 3paclng of the end~ of t~e corlduc:tors7 The re :auired nurlber of the lam~nae, both with conductoxs an~ without, are assembl~d in face~to-face relationship wi~h the conductor sides oriented in the s~me dix2ction to for~ the ~ubstratP tO ~th heir top edges forming a chip mo~nting surface 16 and their opposite edges forming a rPverse surface 18. The assembl~d ceramic lamlnaa are cured in a conYentional manner to form a unitary structure.
.BTJ~9~81--007 The method of foxming the laminae and the substrate from the lamunae is well known in the art and descxibed in said U. S. Pate~t~ 4, 202,007 and 4,193,082 commonly assigned.
A~ seen i~ the drawing, the completed sub3tra_e ha~ on it~ top ~urface two patterns of conductor ends 20 separated by an area or strip 22 free of conductor end~. In the drawiny ~le ends of the conductor~ on the chip mounting surface are shown as dashe~ ( ) which roughly approximates their shape.
~Yhen surface rletallization connects to the conductor end~, as will be describe~ infra, thi~ connection i~
~hown by a circle around the dash. The respective conducto~3 are designated in FIG. 1 by the reference 15 characters 14a, 14c, and 14d at the left hand sida.
~ach da~h on the ame horizontal line is on the same lamina. The interconnect pattern can be determined from FIGS. 2, 3 and 4. ~ith this technique al~er-nate patterns and conductor ~ree strip~ can be repeated many times.
The spaciny o~ the conductor end within each of the pattern~ 20 i~ so arranged that there i~
space provided within the pattexnR ~o provide for chip mounting ~ikes. Th se ~ites can accommodate chip mounting metal pads 24 which are ~uitable for flip chip bonding o~ semicondu~tor chips as well as surface metalli~ation or wiring 26 for connecting chip pad3, and/or conductor end3. ~This arrangement can also be ~tili2ed for wire bonding, or o~her types o~ chip bonding.) Tllese pads 24 can be arranged within ~he ~ite to accommodate ~elected chips which are to be mDUn Pd on the sub~trate and intercon-nected thereto by conventional flip chip solde.r ~u-s-al-007 bonding tec}~iques. It will be apparent that many dirferen configurations or chip mounting pad3 24 or wi~ing metalli~a~ion could be applied at each of the pattexns to accommodate tne requisite selection of chip mix which i3 to ~e u~ed on the substrate. Thi3 then allows for the personalization of a single subætrate to accommodate a wide var~eky and mi~ of chip~. Four possible chips in two adjacent patternq axe 5hown, the chips bei~g designated 2~, 30, 32, and 34.
A com~ination of the subsurface conductors 14a, l~c, 14d, and mounting 3urface wiring 26 inter~
connect the variou~ chip~ 28, 30, 32, and 34 togethar, and to input~output (I/O) pins 36 are attached to the rear surface 18 of the subs~rate. In ~ome casas other types o~ I/O connections such as edge connec-tions or "bump" connections may be emplo~Ied rathar than I/O pins. ~s can be seen in FIGS. 1, 2 and 3, the configuration of the conductor~ 14a and 14c provide 3ub~urface connection between various poin~s on the chip mounti~g surface. For example, the conductors 14a provide wiri.ng connbction between one extreme ~ide of a pattern and the other side, while the conductors 14c provide wiring connections wi~hin each pattern as well as subsurface co~nection 'oetween one pattern and the next adjacent pattern benea~h ~he strip 22 on the mou~ting sur~ac~.
The strip 2~ on the mounting surfaca provides a relatively large surface area free of ~h4 ends of conductor to accom~odate a large amoun~ of surface wiring which may re~uire long ortnogonal segments, and wnich wiring connect~ both co~ductor end in the same pattern as well as co~ductor ends f~om one ~U-3-81-007 pattern across the strip ~2 to the conductor ends ln tha next pattern. Thus by the u~e or repeating conductor end patterrs on the surfac~ interconnected by ~ub~urface conductorq together with space~ between the repeating pattern for wiring having long ortho~
gonal segmen~3 a single sub~trate can be used for many combinat~.on~ o chip~.
It ~hould be noted that the figure3 are some-what ~implified in several respect~ from conven~
tional actual phy~lcal e~bodimsnt~ for the 2~rpose of clarification. The modiflcation~ inclu~e showing only a few laminae forming a ~u~str~te whereas many ~ore coul~ be used to provide denser connection ~nd/or a ~w~der ~ub~trate. A1 op only a sele_ted sample of ~urface conne~tions and wlring i5 ~hown, and this wiring could be mu~h ~enser~ Also, mo~t chips would hav~ more qolder connection ?oint~ ~han those sho~ we~er, ~'ox the sake o clarlty, ~
minimal showing o~ these vPriou3 el~enk3 i3 made ~o illu~trate the invention, Th~ abov~ desoribed tec.~niqu~ of for~ny the substrate ~rom lamina9 utillzing the e~.ge~ thereo~
to form the chlp ~ounting surface 1~ the ~referred technolo~y. ~o~.~ever, the technolo~r ustr.g la~.inae bonded together ln 42ce ~to-face relattonshi~ .~ith the face of one lz~na as ~he surface as ~t sclo3ed ln said I~M TQChn~Ca1 Disclo~urs ~ullQtin, ~701. 22, ~o. 5, Oc~ober 1979, a~ page~ 1841 1842 could also be used.
AN IMPROVED SE~IICONDUCTOR CHIP PACK~GE
BAC~GROU~ OF T~IE INVENTION
Thi~ invention relates ~o pack~ging o ~emicon-ductor ahlp~, and more particularly, to a chlp package wherein ~he sub~trate i9 prorided wlth a repea~ing pa~tern of ~onductor ends, with each pattern defining ~ites to p~rmit the reception of a varlety o~ different chip~. The ~onductor ends are wlred to connect both within the ~ame pattern and with adjacent pattern~O Thi~ permits ~he personali-zation o~ a common sub~trate to receive many d~~er ~nt co~bination~ of chip~.
In the evolutlon of semiconductor technology, packag~ng of the chip~ ha~ taken on increasing 1~ lmpoxtanc~. The number o~ circuit3 that can be placed on a chip ha~ drama~ically lncreased a~ has the number of ~unctlon3 o~ any given chipo Thera are chlp~ which are primarily memory, tho~e which are prima.rily logic, and those which are mixed logic and memory. A~ miniaturlzation progres3~s it i5 becomlng increa3lngly de~irable ~o placs a number of dif~erent chip , ana different comblnations of chips onto a ~lngls ~ub~tra~e. Thi~ ~hip/subs~rate pack~ge can bs lnserted a~ a unlt into various piece~ of equipment.
However, wlth prior art t2chnology each module having a di~er~nt combination o~ chlp~ had to h~e a juDstrate designed speci~ically for each combina tion o~ chlps. Indaed, even in a ~ingl~ chip module, each different chip re~uirad a different ~u~3~.rate uni~e to the given ship. Prior art examples o~
~U-9~ 0~7 technolo~y or providing a substrate .or a glven chlp or specific combination of chips i8 repra~ented in U~ S. Patents 4,202,007 and 4"193,802 which xepresent one technology ~or making ~ubstrate~ with buried wiring~ and }B~ Technisal Disclo~ure Bulletin, Vol. 22, i~o. 5 dated Qctober 1979, at pagss 1841-1842, which xepre~ent~ a different technolocJy. This prior art, however J show~ only a technigue for forming substra~e~ which will accept predetermined 0 chip9 OX chip combination~. The nece~sity of design-in~, producing and stoc~piling a different substrate for each chip and ~ach dif~rent combination of chips i~ ~ery expensîve and adds ~igni~icantly to tllf~ cos~ .
SU~ARY OF T~ ~NTIO~L~
According to the pre~ent invention/ a sub~krate ~or packaging semiconductor chip~ i~ provided havlng a chip mounting ~ur~ace. The substrate i5 ~truc-tured with conductors having opposite end~ termina-~ing at ~aid moun~ing sur~ace with intermecl.iateportions connectinrJ the end3 o~ t~e conductor3. Tile encls of the conductor~ are arranged ln repeating pattPrn~ longitudinally along the 3ub~trate separated by ortho~onal strips on the ~urface which are free of conductor ends ~o allow for d~n~e ~urface wlring, The intermediate portions o~ some conductors connect end3 within a pattern and of 30me conductor3 connect end~ in ad~acent pattexns. The conductor ends in each pattern are ~ositioned ~o delinea~e a pluralit~
of chip mounting site3 ha~ing qufficient pacinq between the conductor end3 to per~it the positioning *Registered Trade Mark ~U-9~81~007 of chip mounting means which may be electrically connected to tne end~ of the conductor~ ~y surrace me allization.
In this way a ~ingle 3ub trate can be pexsonal-ized ~o accep~ a plurality of different chlpq at a~ygiven pattern loca~lon and to utili2e two or more locations to mount chip3 with a~propriate connec-kions betwe~n.
The sub~trate of the present lnvention utilize3 subsurface conductor3 to pxovide basic interconnec-~lon within each pattern and be~ween adjacen~ pa~texns and 3urface wlrlng or the uni~ue personalized chip mounting and wiringt DE~CRIPTON OF TH~ DRA~INGS
FIG. l i~ a plan view of a chip pac~age of thi~
invontion ~howing the substrate and chips mounted thereon;
PIG. 2 i3 a ~ectional view taXen ~ub~tantially along the plane designated by line 2-2 o~ FIG. l;
FIG. 3 i3 a ~ectional vi~w taken sub3tantially along the plan~ dQsignated by the line 3-3 o FIG. l;
FIG. 4 1~ a ~ectional vlaw taken sub tantially along the plane designated by the llne 4-4 o~ ~IG. l;
and FIG. 5 i~ a per~pective exploded YieW o ~ome of the laminae utilized to form the ~ub~t~ate oE
FIG. l.
~U-9 81-007 5~
D~SCRIPTI0~ OF T~E PRE~ERR~D ~ODL~NT
Referring now to the drawing, a substrata having two repeating patterns of suxface ter~lnation of conductors i~ sho~n~ I~ is to be under3tood that 5 the substrate could be made lo~ger with additional repeating pattern~, but two are shown for ~he pur~ose of illu.stration.
The su~trate, designatad by the refere~ce charac~er 10, is ~ormed ~rom a plurality of differ ent lam~nae, 12a, 12b, 12c, 12d, some of which are shown ln FIG~ 5. Tha laminae ar~ hin 3hee~s s~f green (uncured~ ceramic or other dielectric material.
Differen~ lamlnae 12a, 12c, and 12d have o~med on their faces ~31ec~rical conduc:tors 14a, 14c, 14 d, respectively. The conduc~ors 14a and l~c are in a pattern that ~tart~ a~ the top edcJe o:f -the lamlna, extends along the a ::e below the top surfacs and xe turn~ again to the top sur~ace. The conductors l~d extend frolll the top surface of the lamlna along 20 ~he ~ace to the bottom surf~ce. Some of the lamillae represented by laminae 12b may have no conductor~
and are to control lateral 3paclng of the end~ of t~e corlduc:tors7 The re :auired nurlber of the lam~nae, both with conductoxs an~ without, are assembl~d in face~to-face relationship wi~h the conductor sides oriented in the s~me dix2ction to for~ the ~ubstratP tO ~th heir top edges forming a chip mo~nting surface 16 and their opposite edges forming a rPverse surface 18. The assembl~d ceramic lamlnaa are cured in a conYentional manner to form a unitary structure.
.BTJ~9~81--007 The method of foxming the laminae and the substrate from the lamunae is well known in the art and descxibed in said U. S. Pate~t~ 4, 202,007 and 4,193,082 commonly assigned.
A~ seen i~ the drawing, the completed sub3tra_e ha~ on it~ top ~urface two patterns of conductor ends 20 separated by an area or strip 22 free of conductor end~. In the drawiny ~le ends of the conductor~ on the chip mounting surface are shown as dashe~ ( ) which roughly approximates their shape.
~Yhen surface rletallization connects to the conductor end~, as will be describe~ infra, thi~ connection i~
~hown by a circle around the dash. The respective conducto~3 are designated in FIG. 1 by the reference 15 characters 14a, 14c, and 14d at the left hand sida.
~ach da~h on the ame horizontal line is on the same lamina. The interconnect pattern can be determined from FIGS. 2, 3 and 4. ~ith this technique al~er-nate patterns and conductor ~ree strip~ can be repeated many times.
The spaciny o~ the conductor end within each of the pattern~ 20 i~ so arranged that there i~
space provided within the pattexnR ~o provide for chip mounting ~ikes. Th se ~ites can accommodate chip mounting metal pads 24 which are ~uitable for flip chip bonding o~ semicondu~tor chips as well as surface metalli~ation or wiring 26 for connecting chip pad3, and/or conductor end3. ~This arrangement can also be ~tili2ed for wire bonding, or o~her types o~ chip bonding.) Tllese pads 24 can be arranged within ~he ~ite to accommodate ~elected chips which are to be mDUn Pd on the sub~trate and intercon-nected thereto by conventional flip chip solde.r ~u-s-al-007 bonding tec}~iques. It will be apparent that many dirferen configurations or chip mounting pad3 24 or wi~ing metalli~a~ion could be applied at each of the pattexns to accommodate tne requisite selection of chip mix which i3 to ~e u~ed on the substrate. Thi3 then allows for the personalization of a single subætrate to accommodate a wide var~eky and mi~ of chip~. Four possible chips in two adjacent patternq axe 5hown, the chips bei~g designated 2~, 30, 32, and 34.
A com~ination of the subsurface conductors 14a, l~c, 14d, and mounting 3urface wiring 26 inter~
connect the variou~ chip~ 28, 30, 32, and 34 togethar, and to input~output (I/O) pins 36 are attached to the rear surface 18 of the subs~rate. In ~ome casas other types o~ I/O connections such as edge connec-tions or "bump" connections may be emplo~Ied rathar than I/O pins. ~s can be seen in FIGS. 1, 2 and 3, the configuration of the conductor~ 14a and 14c provide 3ub~urface connection between various poin~s on the chip mounti~g surface. For example, the conductors 14a provide wiri.ng connbction between one extreme ~ide of a pattern and the other side, while the conductors 14c provide wiring connections wi~hin each pattern as well as subsurface co~nection 'oetween one pattern and the next adjacent pattern benea~h ~he strip 22 on the mou~ting sur~ac~.
The strip 2~ on the mounting surfaca provides a relatively large surface area free of ~h4 ends of conductor to accom~odate a large amoun~ of surface wiring which may re~uire long ortnogonal segments, and wnich wiring connect~ both co~ductor end in the same pattern as well as co~ductor ends f~om one ~U-3-81-007 pattern across the strip ~2 to the conductor ends ln tha next pattern. Thus by the u~e or repeating conductor end patterrs on the surfac~ interconnected by ~ub~urface conductorq together with space~ between the repeating pattern for wiring having long ortho~
gonal segmen~3 a single sub~trate can be used for many combinat~.on~ o chip~.
It ~hould be noted that the figure3 are some-what ~implified in several respect~ from conven~
tional actual phy~lcal e~bodimsnt~ for the 2~rpose of clarification. The modiflcation~ inclu~e showing only a few laminae forming a ~u~str~te whereas many ~ore coul~ be used to provide denser connection ~nd/or a ~w~der ~ub~trate. A1 op only a sele_ted sample of ~urface conne~tions and wlring i5 ~hown, and this wiring could be mu~h ~enser~ Also, mo~t chips would hav~ more qolder connection ?oint~ ~han those sho~ we~er, ~'ox the sake o clarlty, ~
minimal showing o~ these vPriou3 el~enk3 i3 made ~o illu~trate the invention, Th~ abov~ desoribed tec.~niqu~ of for~ny the substrate ~rom lamina9 utillzing the e~.ge~ thereo~
to form the chlp ~ounting surface 1~ the ~referred technolo~y. ~o~.~ever, the technolo~r ustr.g la~.inae bonded together ln 42ce ~to-face relattonshi~ .~ith the face of one lz~na as ~he surface as ~t sclo3ed ln said I~M TQChn~Ca1 Disclo~urs ~ullQtin, ~701. 22, ~o. 5, Oc~ober 1979, a~ page~ 1841 1842 could also be used.
Claims (10)
1. A substrate for mounting a plurality of semiconductor chips at variable locations thereon comprising:
an insulating block of material having a chip mounting surface and a reverse surface, said substrate having a plurality of con-ductors each having spaced opposite ends, one of which ends is on said mounting surface, with inter-mediate portions extending beneath said surface, and wherein some of said conductors have intermediate portions extending entirely through said substrate with their opposite ends terminating on the reverse surface to provide for I/O attachment sites and wherein the intermediate portion of some of the conductors return to the chip mounting surface to provide both ends on the mounting surface;
said ends of said conductors on said mounting surface being arranged in a plurality of longitudinal repeating patterns separated by repeat-ing orthogonally extending surface strips free of said conductor ends;
said conductors being arranged such that some of said intermediate portions extend between opposite ends in the same patterns and some extend between ends in adjacent patterns;
the ends of said conductor in each pattern being positioned to delineate a plurality of chip mounting sites having sufficient spacing between said ends to permit the positioning of chip mounting means which may be electrically connected to the ends of said conductor leads and to a semiconductor chip;
whereby a plurality of different chips may be mounted on each pattern and connected to chips in the same pattern and an adjoining pattern by both surface and surface conductors.
an insulating block of material having a chip mounting surface and a reverse surface, said substrate having a plurality of con-ductors each having spaced opposite ends, one of which ends is on said mounting surface, with inter-mediate portions extending beneath said surface, and wherein some of said conductors have intermediate portions extending entirely through said substrate with their opposite ends terminating on the reverse surface to provide for I/O attachment sites and wherein the intermediate portion of some of the conductors return to the chip mounting surface to provide both ends on the mounting surface;
said ends of said conductors on said mounting surface being arranged in a plurality of longitudinal repeating patterns separated by repeat-ing orthogonally extending surface strips free of said conductor ends;
said conductors being arranged such that some of said intermediate portions extend between opposite ends in the same patterns and some extend between ends in adjacent patterns;
the ends of said conductor in each pattern being positioned to delineate a plurality of chip mounting sites having sufficient spacing between said ends to permit the positioning of chip mounting means which may be electrically connected to the ends of said conductor leads and to a semiconductor chip;
whereby a plurality of different chips may be mounted on each pattern and connected to chips in the same pattern and an adjoining pattern by both surface and surface conductors.
2. The invention as defined in Claim 1 wherein said substrate is comprised of a plurality of dielectric laminae, the face portions of which define the location of the interior conductors of the substrate and the edge portions define said mounting surface and reverse surface.
3. The invention as defined in Claim 2 wherein the conductors are deposited on the face or said laminae terminating at the edges thereof.
4. The invention as defined in Claim 3 wherein the conductors formed on the face of each of said lamanae are formed in repeating identical patterns.
5. The invention as defined in Claim 1 wherein pins are affixed to the ends of at least some of said conductors on the reverse surface.
6. An electronic module comprising a substrate mounting a plurality of semiconductor chips at variable locations thereon;
said substrate comprising an insula-ting block of material having a chip mounting surface and a reverse surface, said substrate having a plurality of conductors each having spaced opposite ends one of which ends is on said mounting surface, with intermediate portion extending beneath said surface, and wherein some of said conductors have intermediate portions extending entirely through said substrate with their opposite end terminating on the reverse surface to provide for I/O attachment sites and wherein the intermediate portions of some of said conductors return to the chip mounting surface to provide both ends on the mounting surface;
said spaced opposite ends of said conductors being arranged in a plurality of longi-tudinal repeating patterns separated by repeating orthogonally extending surface strips free of said conductor ends;
said conductors being arranged such that some of said intermediate portions extend between opposite ends in the same patterns and some extend between ends in adjacent patterns;
a plurality of chip mounting means located on the chip mounting surface in each pattern delineating a plurality of chip mounting sites, said chip mounting means being electrically connected by surface wiring to the ends of some of said conductor leads; and a plurality of different chips each mounted on one of said sites in each pattern and connected to chips in the same pattern and an adjoin-ing pattern by both surface and subsurface conductors.
said substrate comprising an insula-ting block of material having a chip mounting surface and a reverse surface, said substrate having a plurality of conductors each having spaced opposite ends one of which ends is on said mounting surface, with intermediate portion extending beneath said surface, and wherein some of said conductors have intermediate portions extending entirely through said substrate with their opposite end terminating on the reverse surface to provide for I/O attachment sites and wherein the intermediate portions of some of said conductors return to the chip mounting surface to provide both ends on the mounting surface;
said spaced opposite ends of said conductors being arranged in a plurality of longi-tudinal repeating patterns separated by repeating orthogonally extending surface strips free of said conductor ends;
said conductors being arranged such that some of said intermediate portions extend between opposite ends in the same patterns and some extend between ends in adjacent patterns;
a plurality of chip mounting means located on the chip mounting surface in each pattern delineating a plurality of chip mounting sites, said chip mounting means being electrically connected by surface wiring to the ends of some of said conductor leads; and a plurality of different chips each mounted on one of said sites in each pattern and connected to chips in the same pattern and an adjoin-ing pattern by both surface and subsurface conductors.
7. The invention as defined in Claim 6 wherein said substrate is comprised or a plurality of dielectric laminae, the face portion of which define the location of the interior conductors of the substrate, and the edge portions define said mounting surface and reverse surface.
8. The invention as defined in Claim 7 wherein the conductors are deposited on the faces of said laminar terminating at the edge thereof.
9. The invention as defined in Claim 8 wherein the conductors formed on the face of each of said lamanae are formed in repeating identical patterns.
10. The invention as defined in Claim 6 wherein pins are affixed to the ends of at least some of said conductors on the reverse surface.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US28572581A | 1981-07-22 | 1981-07-22 | |
| US285,725 | 1981-07-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1182582A true CA1182582A (en) | 1985-02-12 |
Family
ID=23095459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000404784A Expired CA1182582A (en) | 1981-07-22 | 1982-06-09 | Semiconductor chip package |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0070533B1 (en) |
| JP (1) | JPS5818951A (en) |
| CA (1) | CA1182582A (en) |
| DE (1) | DE3277890D1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4674007A (en) * | 1985-06-07 | 1987-06-16 | Microscience Corporation | Method and apparatus for facilitating production of electronic circuit boards |
| JPS63245952A (en) * | 1987-04-01 | 1988-10-13 | Hitachi Ltd | Multichip module structure |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3370203A (en) * | 1965-07-19 | 1968-02-20 | United Aircraft Corp | Integrated circuit modules |
| FR1540051A (en) * | 1966-09-21 | 1968-09-20 | Rca Corp | Microcircuit and its manufacturing process |
| DE2964342D1 (en) * | 1978-06-23 | 1983-01-27 | Ibm | Multi-layer dielectric substrate |
| JPS5612760A (en) * | 1979-07-10 | 1981-02-07 | Nec Corp | Multi chip lsi package |
-
1982
- 1982-05-20 JP JP8409182A patent/JPS5818951A/en active Granted
- 1982-06-09 CA CA000404784A patent/CA1182582A/en not_active Expired
- 1982-07-16 DE DE8282106401T patent/DE3277890D1/en not_active Expired
- 1982-07-16 EP EP19820106401 patent/EP0070533B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE3277890D1 (en) | 1988-02-04 |
| EP0070533B1 (en) | 1987-12-23 |
| EP0070533A3 (en) | 1985-01-30 |
| JPS62583B2 (en) | 1987-01-08 |
| EP0070533A2 (en) | 1983-01-26 |
| JPS5818951A (en) | 1983-02-03 |
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