CA1181528A - Micro computer adapted for use with crt display - Google Patents
Micro computer adapted for use with crt displayInfo
- Publication number
- CA1181528A CA1181528A CA000405102A CA405102A CA1181528A CA 1181528 A CA1181528 A CA 1181528A CA 000405102 A CA000405102 A CA 000405102A CA 405102 A CA405102 A CA 405102A CA 1181528 A CA1181528 A CA 1181528A
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- central processing
- bus
- bit address
- data
- bit
- Prior art date
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-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
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- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microcomputers (AREA)
- Controls And Circuits For Display Device (AREA)
- Debugging And Monitoring (AREA)
- Digital Computer Display Output (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
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Microcomputer apparatus includes a Z80A-CPU central processing unit operable with 8-bit data and 15-bit address information; an upper 8-bit address bus; a lower 8-bit address bus; an 8-bit data bus; a ROM for storing a monitor program and/or a BASIC interpreter and connected to the central processing unit through the address buses and the data bus; a first RAM for a work area connected to the central processing unit through the address buses and the data bus; a second separate video buffer RAM for video display connected to the central processing unit through the address buses and the data bus and adapted to be accessed by I/O instructions from the central processing unit; and a CRT display for displaying a video picture in response to video data stored in the video RAM.
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Microcomputer apparatus includes a Z80A-CPU central processing unit operable with 8-bit data and 15-bit address information; an upper 8-bit address bus; a lower 8-bit address bus; an 8-bit data bus; a ROM for storing a monitor program and/or a BASIC interpreter and connected to the central processing unit through the address buses and the data bus; a first RAM for a work area connected to the central processing unit through the address buses and the data bus; a second separate video buffer RAM for video display connected to the central processing unit through the address buses and the data bus and adapted to be accessed by I/O instructions from the central processing unit; and a CRT display for displaying a video picture in response to video data stored in the video RAM.
Description
s~
BACKGRt:)UND OE' THE INVENTION
Field of th~ Invention This invention relates generally to microcomputer apparatus and, more particularly, is directed to a microcomputer apparatus that operates with a CRT display.
Descri~tion of _he Prior Art Recently, desk top microcomputer apparatus have become very populc~r. Such microcomputer apparatus conventionally employ an 8-bit central processing unit (CPU) which uses 16~bit addresses, such that the CPU can directly access a memory area of 64K locations, that is, from OOOOH to FFFFH, with each address location including 8-bits (one byte) of data. Accordingly, with a personal computer of the above type which uses an 8-bit CPU, 32K of the locations of memory area, for example, may be used for a read only memory (ROM) area for storing a monitor program and/or BASIC interpreter, whereby the remaining address or memory area of 32K locations can be used for a random access memory (RAM) area.
However, when using the microcomputer apparatus with a CRT monitor or display, it is necessary to provide a video R~M
area. For èxample, if a graphic or video display of 640 X 400 dots is provided, with one bit being assigned to one dot, a video RA~1 of 32K bytes or less is required. As a result, there may be ~little or no RAM area for user programming. In order to expand the memory area to avoid such problems, it has been proposed to provide a plurality of memory banks selectively connected to the CPU under the control of the system software. However, since change-over of the different memory banks must be carried out in accordance with the software program, such change-over is
BACKGRt:)UND OE' THE INVENTION
Field of th~ Invention This invention relates generally to microcomputer apparatus and, more particularly, is directed to a microcomputer apparatus that operates with a CRT display.
Descri~tion of _he Prior Art Recently, desk top microcomputer apparatus have become very populc~r. Such microcomputer apparatus conventionally employ an 8-bit central processing unit (CPU) which uses 16~bit addresses, such that the CPU can directly access a memory area of 64K locations, that is, from OOOOH to FFFFH, with each address location including 8-bits (one byte) of data. Accordingly, with a personal computer of the above type which uses an 8-bit CPU, 32K of the locations of memory area, for example, may be used for a read only memory (ROM) area for storing a monitor program and/or BASIC interpreter, whereby the remaining address or memory area of 32K locations can be used for a random access memory (RAM) area.
However, when using the microcomputer apparatus with a CRT monitor or display, it is necessary to provide a video R~M
area. For èxample, if a graphic or video display of 640 X 400 dots is provided, with one bit being assigned to one dot, a video RA~1 of 32K bytes or less is required. As a result, there may be ~little or no RAM area for user programming. In order to expand the memory area to avoid such problems, it has been proposed to provide a plurality of memory banks selectively connected to the CPU under the control of the system software. However, since change-over of the different memory banks must be carried out in accordance with the software program, such change-over is
-2-troublesome and the processing speed of the program is lowered.
In addition, the construction of such program is relatively complicated since extremely careful attention must be taken to prevent errors.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide microcomputer apparatus that avoids the above-described difficulties encountered with the prior art~
More particularly, it is an object of this invention to provide microcomputer apparatus of the desk top type which is adapted to be used with a CRT display.
It is another object of -this invention to provide microcomputer apparatus having a video buffer memory area for a CRT display which is mapped on an I~O address area of the microcomputer apparatus.
It is still another object of this invention to provide microcomputer apparatus in which the directly accessible address axea of the apparatus that can be used for user programming is not reduced, by allocating a video buffer memory area to an I/O
address area of the microcomputer apparatus.
It is yet another object of this invention to provide microcomputer apparatus having a video buffer memory area for a CRT display controlled by I/O instructions of the CPU.
- In accordance with an aspect of this invention, microcomputer apparatus includes central processing means operable with n-bit data and m-bit address information; bus means; read only memory means for stor1ng a monitor program and connected to the central processing means through the bus means;
first random access memory means for a work area connected to the central processing means through the bus means; and second separate random access memory means for video display connected to the central processing means through the bus means and adapted to be accessed by I/O instructions from the central processing means.
The above, and other, objects, features and advantages of the invention will become apparent from the following detailed description of an illustrative embodiment of the invention which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figs. lA and lB are schematic diagrams used to explain the operation of a central processing unit for microcomputer apparatus according to this invention;
Fig. 2 is a block diagram of microcomputer apparatus according to one embodiment of this invention;
Figs. 3A and 3B are schematic diagrams used to explain the memory address allocation in the microcomputer apparatus of Fig. 2; and Figs. 4A-4D are schematic diagrams used ~o explain the connection between the central processing unit and the video buffer memory`according to the present invention.
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DETAILED DESCRIPTION OF A PREFERRED EMBODI~ENT
Referriny to the drawings in detail, and initially to F-ig. 2 thereof, microcomputer apparatus according to one embodiment of this invention includes a central processing unit (CPU) 1 which may, for example, be a Z80A-CPU designed by Zilog, Inc. or an NSC-800 CPU designéd by National Semiconductor.
Hereinafter, any reference to CPU 1 will be directed to the Z80A-CPU which will be used for explanative purposes only. The microcomputer apparatus according to this invention also includ~s a read only memory (ROM) 2 which stores a monitor program and a BASIC interpreter program, and which, for example, includes 32K
8-bit address locations from 0000H to 7FFFH, as shown in Fig. 3A.
The microcomputer apparatus also includes a random access memory (RAM) 3 in which a user program can be written and which also serves as a work area for CPU 1. As shown in Fig. 3B, RA~1 3 also includes 32K 8-bit address locations from 8000H to FFFFH. It is to be appreciated that the above numbers of 8-bit address locations are only given for illustrative purposes, and the invention is not limited by the specific figures used. An 8-bit data bus 4, a lower 8-bit address bus 5L and an upper 8-bit address bus 5H are connected to corresponding data terminals Do to D7, address terminals Ao to A7 and address terminals A8 to A15, respectively~ of CPU 1, ROM 2 and RAM 3 for transferring information therebetween.
To control the reading of informaion from ROM 2 and RAM
In addition, the construction of such program is relatively complicated since extremely careful attention must be taken to prevent errors.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide microcomputer apparatus that avoids the above-described difficulties encountered with the prior art~
More particularly, it is an object of this invention to provide microcomputer apparatus of the desk top type which is adapted to be used with a CRT display.
It is another object of -this invention to provide microcomputer apparatus having a video buffer memory area for a CRT display which is mapped on an I~O address area of the microcomputer apparatus.
It is still another object of this invention to provide microcomputer apparatus in which the directly accessible address axea of the apparatus that can be used for user programming is not reduced, by allocating a video buffer memory area to an I/O
address area of the microcomputer apparatus.
It is yet another object of this invention to provide microcomputer apparatus having a video buffer memory area for a CRT display controlled by I/O instructions of the CPU.
- In accordance with an aspect of this invention, microcomputer apparatus includes central processing means operable with n-bit data and m-bit address information; bus means; read only memory means for stor1ng a monitor program and connected to the central processing means through the bus means;
first random access memory means for a work area connected to the central processing means through the bus means; and second separate random access memory means for video display connected to the central processing means through the bus means and adapted to be accessed by I/O instructions from the central processing means.
The above, and other, objects, features and advantages of the invention will become apparent from the following detailed description of an illustrative embodiment of the invention which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figs. lA and lB are schematic diagrams used to explain the operation of a central processing unit for microcomputer apparatus according to this invention;
Fig. 2 is a block diagram of microcomputer apparatus according to one embodiment of this invention;
Figs. 3A and 3B are schematic diagrams used to explain the memory address allocation in the microcomputer apparatus of Fig. 2; and Figs. 4A-4D are schematic diagrams used ~o explain the connection between the central processing unit and the video buffer memory`according to the present invention.
-,.~ ,. - . .
DETAILED DESCRIPTION OF A PREFERRED EMBODI~ENT
Referriny to the drawings in detail, and initially to F-ig. 2 thereof, microcomputer apparatus according to one embodiment of this invention includes a central processing unit (CPU) 1 which may, for example, be a Z80A-CPU designed by Zilog, Inc. or an NSC-800 CPU designéd by National Semiconductor.
Hereinafter, any reference to CPU 1 will be directed to the Z80A-CPU which will be used for explanative purposes only. The microcomputer apparatus according to this invention also includ~s a read only memory (ROM) 2 which stores a monitor program and a BASIC interpreter program, and which, for example, includes 32K
8-bit address locations from 0000H to 7FFFH, as shown in Fig. 3A.
The microcomputer apparatus also includes a random access memory (RAM) 3 in which a user program can be written and which also serves as a work area for CPU 1. As shown in Fig. 3B, RA~1 3 also includes 32K 8-bit address locations from 8000H to FFFFH. It is to be appreciated that the above numbers of 8-bit address locations are only given for illustrative purposes, and the invention is not limited by the specific figures used. An 8-bit data bus 4, a lower 8-bit address bus 5L and an upper 8-bit address bus 5H are connected to corresponding data terminals Do to D7, address terminals Ao to A7 and address terminals A8 to A15, respectively~ of CPU 1, ROM 2 and RAM 3 for transferring information therebetween.
To control the reading of informaion from ROM 2 and RAM
3, CPU 1 supplies a memory request signal MREQ and/or a read signal RD to respective inputs of an OR circuit 6 to derive a memory read signal MEMR which is supplied to respective read terminals R of each of ROM 2 and RAM 3. In like manner, to , ' ' `'. . ! . -, perform a writing operation with respect to RAM 3, a write signal WR is generated by CPU 1, and write signal WR and/or the afQrementioned memory request signal MREQ are supplied to respective inputs of an OR circuit 7. The latter circuit, in turn, produces a memory wrlte signal MEMW which is supplied to a write terminal W of ~M 3.
With the microcomputer apparatus according to this invention~ as shown in Fig. 2, a maximum of 256 external I/O
ports 11 can be connected to CPU 1, each being designated by a port nllmber n from 00H to FFH. However, fewer than 756 I/O
oports 11 can be provided. For example, ports numbered 80H to FFH can be provided. A plurality of external I/O devices J such as a keyboard 21 and a magnetic tape cassette 22 can be connected to each I/O port 11, with a maximum of 256 external I/O devices being connected to each port. For ease in understanding the present invention, only the one I/O port 11 shown in FIg. 2 will be described hereinafter. I/O port 11 includes data terminals Do to D7 connected to data bus 4, and address terminals Ao to A7 connected to lower address bus 5L. In the same manner as previously discussed in regard to RAM 2 and RAM 3, CPU 1 controls the reading and writing of information from and to IjO port 11.
Thus, CPU 1 generates an I/O request signal IORQ, and the I/O
request signal and/or the read signal RD are supplied to respective inputs of an OR circuit 8 which, in turn, supplies an I/O read signal IOR to a read terminal R of I/O port 11. In like manner, the I/O request signal IORQ and/or the write signal WR
are supplied by CPU 1 to respective inputs of an OR circuit 9 which, in turn~ supplies an I/O write signal IOW to a write terminal W of I/O port 11. In this manner, reading and writing of information between I/O port 11 and CPU 1 can be effected.
By way of example only, operating instructions for a Z80A-CPU will now be discussed for transferring data between an external I/O port 11 and CPU 1 ~and consequently, RAM 3). It is to be first noted that the Z80A-CPU includes at least A, B, C, D, E, H and L general purpose registers and the transfer of 8-bit data between an external I/O port 11 and one or more of these registers occurs through data bus line 4. Corresponding address information is transferred through the 16-bit address bus line comprised of upper 8-bit address bus line 5H and lower 8-bit address bus line 5L. In particular, the following I/O
instructions can be used:
I-1 IN A, n This instruction transfers 8-bit data at an input port designated by port nu~er n In = O ~~ 255) to the A register or the CPU.
I-2 OUT n, A
This instruction transfers 8-bit data from the A register of the CPU to an output port designated by port number n. It is to be appreciated that, with these instructions, the 8-bit data from the A register appears both on data terminals Do to D7 and on address terminals A~ to A15. In such case, the lower 8-bit address terminals Ao to A7 are supplied with address information and indicate the port number n, as shown in Fig. lA.
II-l IN r, (C) This instrution transfers data at a port (identified by port number n~ designated by the BC register pair to an r register, where the r register is one of the A, B, C, D, E, H and L
registers.
II-2 OUT (C), r This instruction transfers data from the r register to the port (identified by port number n) designated by the BC register pair.
~n Fig. lB, data for the r register appears at data terminals D~
to D7, the C register contains information from address terminals Ao to A7 corresponding to the port number n, and the B register contains information from address terminals A8 to A15 corresponding to the I/O device connecced to the designated port.
Sin~e eight bi-cs of information are provided in the C register, a 5~2~
maximum of 256 (0 v~ 255) IiO devices can be connected to each port, as previously discussed.
As will be apparent from the discussion hereinafter, the following block transfer instructions are also used with CPU
1 :
III-l INIR, INDR
With these instructions, a plurality of bytes of data, that is, a block of data, can be transferred from a port n to the main memory. In such case, the BC register pair is used to determine the port number ~C register) and the number of bytes to be transferred (B register). The data block is transferred to a memory location, the address of which is determined by the HL
register pair. For example, the last address location to which the data is to be transferred is stored in the HL register pair.
The B register is then used as a counter and counts down to zero.
In particular, the value in the B register is continuously decremented by one, and during each decrement of one, one byte of the block is transferred. When the value stored in register B is equal to zero, all of the bytes of the block of data have been transferred from the respective I/O port designated by the C register.
III-2 OTIR, OTDR
With these instructions, a data block can be transferred from the main memory to an I/O port designated by the C register. The HL
register pair and the B register are used in a similar manner to that described above.
As an example of the above instructions, the following program can be used to effec-t such transfer-LD HL, 08FFH
LD BC, FF0 3 H
OTDRWith this program, the last address in the main memory at which the data is stored is loaded into the HL registPr pair by the load instruction LD, that is, the last address 0$FFH. The port number n is loaded into the C register, that is, 03H, and the number of bytes to be transferred is loaded into the B register, that is, FFH. The value loaded into the B register i5 then continuously decremented by one until it equals zero, and during each decrement of one, one byte of the block of data located at addresses 0800H to 08FFH of the main memory is tranferred to the port designated by port number 03H. When the value stored in the B register eauals zero, all of the bytes of the block of data have been transferred.
In accordance with an aspect of this invention, a separate video RAM 12 is provided as a buffer memory for use in displaying the processed results and, as shown in Fig. 3B, is allocated with a 32K address memory having addresses 0000H to 7~FFH, for example. For ease of transfer of data between video RAM 12 and the Z80A-CPU, as shown in Fig. 2, the lower 8-bit address terminals Ao to A7 of video RP*l 12 are connected to upper address bus 5H corresponding to the upper $-bit address terminals A8 to A15 of CPU 1, ROM 2 and RAM 3. In like manner, the upper ~-~it address terminals A8 to A15 of video RAM 12 are connected to lower address bus 5L corresponding to the lower 8-bit address terminals Ao to A7 of CPU 1, ROM 2 and RP~I 3. In addition, I/O
read signal IOR and I~O write signal IOW from OR circuits 8 and 9, respectively, are supplied to a read terminal R and a write terminal W, respectively of video R~ 12 for controlling the reading and writing operations with respect thereto. Data -terminals Do to D7 of video RAM 12 are also connected to data bus
With the microcomputer apparatus according to this invention~ as shown in Fig. 2, a maximum of 256 external I/O
ports 11 can be connected to CPU 1, each being designated by a port nllmber n from 00H to FFH. However, fewer than 756 I/O
oports 11 can be provided. For example, ports numbered 80H to FFH can be provided. A plurality of external I/O devices J such as a keyboard 21 and a magnetic tape cassette 22 can be connected to each I/O port 11, with a maximum of 256 external I/O devices being connected to each port. For ease in understanding the present invention, only the one I/O port 11 shown in FIg. 2 will be described hereinafter. I/O port 11 includes data terminals Do to D7 connected to data bus 4, and address terminals Ao to A7 connected to lower address bus 5L. In the same manner as previously discussed in regard to RAM 2 and RAM 3, CPU 1 controls the reading and writing of information from and to IjO port 11.
Thus, CPU 1 generates an I/O request signal IORQ, and the I/O
request signal and/or the read signal RD are supplied to respective inputs of an OR circuit 8 which, in turn, supplies an I/O read signal IOR to a read terminal R of I/O port 11. In like manner, the I/O request signal IORQ and/or the write signal WR
are supplied by CPU 1 to respective inputs of an OR circuit 9 which, in turn~ supplies an I/O write signal IOW to a write terminal W of I/O port 11. In this manner, reading and writing of information between I/O port 11 and CPU 1 can be effected.
By way of example only, operating instructions for a Z80A-CPU will now be discussed for transferring data between an external I/O port 11 and CPU 1 ~and consequently, RAM 3). It is to be first noted that the Z80A-CPU includes at least A, B, C, D, E, H and L general purpose registers and the transfer of 8-bit data between an external I/O port 11 and one or more of these registers occurs through data bus line 4. Corresponding address information is transferred through the 16-bit address bus line comprised of upper 8-bit address bus line 5H and lower 8-bit address bus line 5L. In particular, the following I/O
instructions can be used:
I-1 IN A, n This instruction transfers 8-bit data at an input port designated by port nu~er n In = O ~~ 255) to the A register or the CPU.
I-2 OUT n, A
This instruction transfers 8-bit data from the A register of the CPU to an output port designated by port number n. It is to be appreciated that, with these instructions, the 8-bit data from the A register appears both on data terminals Do to D7 and on address terminals A~ to A15. In such case, the lower 8-bit address terminals Ao to A7 are supplied with address information and indicate the port number n, as shown in Fig. lA.
II-l IN r, (C) This instrution transfers data at a port (identified by port number n~ designated by the BC register pair to an r register, where the r register is one of the A, B, C, D, E, H and L
registers.
II-2 OUT (C), r This instruction transfers data from the r register to the port (identified by port number n) designated by the BC register pair.
~n Fig. lB, data for the r register appears at data terminals D~
to D7, the C register contains information from address terminals Ao to A7 corresponding to the port number n, and the B register contains information from address terminals A8 to A15 corresponding to the I/O device connecced to the designated port.
Sin~e eight bi-cs of information are provided in the C register, a 5~2~
maximum of 256 (0 v~ 255) IiO devices can be connected to each port, as previously discussed.
As will be apparent from the discussion hereinafter, the following block transfer instructions are also used with CPU
1 :
III-l INIR, INDR
With these instructions, a plurality of bytes of data, that is, a block of data, can be transferred from a port n to the main memory. In such case, the BC register pair is used to determine the port number ~C register) and the number of bytes to be transferred (B register). The data block is transferred to a memory location, the address of which is determined by the HL
register pair. For example, the last address location to which the data is to be transferred is stored in the HL register pair.
The B register is then used as a counter and counts down to zero.
In particular, the value in the B register is continuously decremented by one, and during each decrement of one, one byte of the block is transferred. When the value stored in register B is equal to zero, all of the bytes of the block of data have been transferred from the respective I/O port designated by the C register.
III-2 OTIR, OTDR
With these instructions, a data block can be transferred from the main memory to an I/O port designated by the C register. The HL
register pair and the B register are used in a similar manner to that described above.
As an example of the above instructions, the following program can be used to effec-t such transfer-LD HL, 08FFH
LD BC, FF0 3 H
OTDRWith this program, the last address in the main memory at which the data is stored is loaded into the HL registPr pair by the load instruction LD, that is, the last address 0$FFH. The port number n is loaded into the C register, that is, 03H, and the number of bytes to be transferred is loaded into the B register, that is, FFH. The value loaded into the B register i5 then continuously decremented by one until it equals zero, and during each decrement of one, one byte of the block of data located at addresses 0800H to 08FFH of the main memory is tranferred to the port designated by port number 03H. When the value stored in the B register eauals zero, all of the bytes of the block of data have been transferred.
In accordance with an aspect of this invention, a separate video RAM 12 is provided as a buffer memory for use in displaying the processed results and, as shown in Fig. 3B, is allocated with a 32K address memory having addresses 0000H to 7~FFH, for example. For ease of transfer of data between video RAM 12 and the Z80A-CPU, as shown in Fig. 2, the lower 8-bit address terminals Ao to A7 of video RP*l 12 are connected to upper address bus 5H corresponding to the upper $-bit address terminals A8 to A15 of CPU 1, ROM 2 and RAM 3. In like manner, the upper ~-~it address terminals A8 to A15 of video RAM 12 are connected to lower address bus 5L corresponding to the lower 8-bit address terminals Ao to A7 of CPU 1, ROM 2 and RP~I 3. In addition, I/O
read signal IOR and I~O write signal IOW from OR circuits 8 and 9, respectively, are supplied to a read terminal R and a write terminal W, respectively of video R~ 12 for controlling the reading and writing operations with respect thereto. Data -terminals Do to D7 of video RAM 12 are also connected to data bus
4. To display the contents of video RAM 12, a CRT controller 13 is connected to video RAM 12 for sequentially reading the data from video RAM 12 and supplying the same to a CRT display 23.
With the microcomputer apparatus according to this invention, as shown in Fig. 2, ROM 2 and RAM 3 are assigned to respective memory control areas of CPU 1, while video RAM 12 is assigned to an I/O area thereof. In this manner, video RAM 12 can be addressed by the ~C register pair of CPU 1 in response to I/O instructions, as discussed previously in regard, for example, to instructions II-l and II-2. Accordingly, as a result of such allocation with respect to ROM 2, RAM 3 and RAM 12; the programmable or work area that can be used in RP~I 3 is not reduced by a video RAM area so that a larger program area is provided for the user. Further, since the area of video RAM 12 can be made as large as 32K bytes, a graphic function having high resolution, for example, 640 x 400 dots, can be achieved. It is to be appreciated that the instructions or commands given by CPU
1 for ROM 2 and RAM 3 can be similar tc those used in conventional microcomputer apparatus, while the I/O instructions or commands I~ 2, II-l, II-2, III-1 and III-2 can be easily used for video Rl~M 12. In other words, it is important that a separate video RA~1 12 is provided which is accessed by I/O
instructions from CPU 1. Accordingly, video ~ 12 can be considered as another I/O port or I/O device.
It is to be appreciated, as previously discussed, that the connections between the lower 8-bit address terminals Ao to A7 and the upper 8-bit address terminals A8 to A15 of video R~M
--lG-12 are reversed or interchanged from those of CPU 1, ROM 2 and RAM 3, as shown in Fiys. 4A-4C, at least ror the case where CPU 1 is a ~80A-CPU. Accordingly, block transfer of a 256-byte unit can be achieved between P~M 3 and video R~M 12 in response to I/O
instructions III-l and III-2. For example, the aforemen,ioned OTDR program can be used to achieve such transfer. In such case, the valve stored in the C register designates video KAM 12. With such program, data from ~AM 3 can be readily transferred directly to video R~ 12 without any buffer memory or the like. As shown in Fig. 4D, the lower 8-bit addresses Ao to A7 of CPU 1 stored in the C register thereof correspond to respective address locations of I/O port 11, or video RAM 12, whereby I/O instructions I-l, I-2, II-l, II-2, III-l and III-2 can be used with video RAM 12 in a manner similar to that of a conventional microcomputer.
It is to be appreciated that, with the present invention, it is unnecessary to first select a memory bank and then access such memory bank. Accordingly, the speed for carrying out the program is not lowered and the programmer need not prepare a complex program for the same.
Having described a specific preferred embodiment of the invention with reference to the accompanying drawings, it is to be understood that the present invention is not limited to that precise embodiment and that various changes~and modifications may be effected therein by one skilled in ~he art without departing from the scope or spirit of the invention as described in the appended claims herein.
--11~
With the microcomputer apparatus according to this invention, as shown in Fig. 2, ROM 2 and RAM 3 are assigned to respective memory control areas of CPU 1, while video RAM 12 is assigned to an I/O area thereof. In this manner, video RAM 12 can be addressed by the ~C register pair of CPU 1 in response to I/O instructions, as discussed previously in regard, for example, to instructions II-l and II-2. Accordingly, as a result of such allocation with respect to ROM 2, RAM 3 and RAM 12; the programmable or work area that can be used in RP~I 3 is not reduced by a video RAM area so that a larger program area is provided for the user. Further, since the area of video RAM 12 can be made as large as 32K bytes, a graphic function having high resolution, for example, 640 x 400 dots, can be achieved. It is to be appreciated that the instructions or commands given by CPU
1 for ROM 2 and RAM 3 can be similar tc those used in conventional microcomputer apparatus, while the I/O instructions or commands I~ 2, II-l, II-2, III-1 and III-2 can be easily used for video Rl~M 12. In other words, it is important that a separate video RA~1 12 is provided which is accessed by I/O
instructions from CPU 1. Accordingly, video ~ 12 can be considered as another I/O port or I/O device.
It is to be appreciated, as previously discussed, that the connections between the lower 8-bit address terminals Ao to A7 and the upper 8-bit address terminals A8 to A15 of video R~M
--lG-12 are reversed or interchanged from those of CPU 1, ROM 2 and RAM 3, as shown in Fiys. 4A-4C, at least ror the case where CPU 1 is a ~80A-CPU. Accordingly, block transfer of a 256-byte unit can be achieved between P~M 3 and video R~M 12 in response to I/O
instructions III-l and III-2. For example, the aforemen,ioned OTDR program can be used to achieve such transfer. In such case, the valve stored in the C register designates video KAM 12. With such program, data from ~AM 3 can be readily transferred directly to video R~ 12 without any buffer memory or the like. As shown in Fig. 4D, the lower 8-bit addresses Ao to A7 of CPU 1 stored in the C register thereof correspond to respective address locations of I/O port 11, or video RAM 12, whereby I/O instructions I-l, I-2, II-l, II-2, III-l and III-2 can be used with video RAM 12 in a manner similar to that of a conventional microcomputer.
It is to be appreciated that, with the present invention, it is unnecessary to first select a memory bank and then access such memory bank. Accordingly, the speed for carrying out the program is not lowered and the programmer need not prepare a complex program for the same.
Having described a specific preferred embodiment of the invention with reference to the accompanying drawings, it is to be understood that the present invention is not limited to that precise embodiment and that various changes~and modifications may be effected therein by one skilled in ~he art without departing from the scope or spirit of the invention as described in the appended claims herein.
--11~
Claims (7)
1. Microcomputer apparatus comprising:
central processing means operable with n-bit data and m-bit address information;
bus means;
read only memory means for storing a monitor program and connected to said central processing means through said bus means;
first random access memory means for a work area connected to said central processing means through said bus means; and second separate random access memory means for video display connected to said central processing means through said bus means and adapted to be accessed by I/O instructions from said central processing means.
central processing means operable with n-bit data and m-bit address information;
bus means;
read only memory means for storing a monitor program and connected to said central processing means through said bus means;
first random access memory means for a work area connected to said central processing means through said bus means; and second separate random access memory means for video display connected to said central processing means through said bus means and adapted to be accessed by I/O instructions from said central processing means.
2. Microcomputer apparatus according to Claim l; in which n equals eight and m equals sixteen.
3. Microcomputer apparatus according to Claim 2; in which said central processing means is a Z80A-CPU.
4. Microcompuer apparatus according to Claim 3; in which said bus means includes address bus means, said central processing means includes upper 8-bit address terminals and lower 8-bit address terminals, and said second random access memory means inclues upper 8-bit address terminals connected to said lower 8-bit address terminals of said central processing means through said address bus means and lower 8-bit address terminals connected to said upper 8-bit address terminals or said central processing means through said address bus means.
5. Microcomputer apparatus according to Claim 4; in which said address bus means includes an upper 8-bit address bus for connecting the upper 8-bit address terminals of said central processing means with the lower 8-bit address terminals of said second random access memory means, and a lower 8-bit address bus for connecting the lower 8-bit address terminals of said central processing means with the upper 8-bit address terminals of said second random access memory means.
6. Microcomputer apparatus according to Claim l; in which said bus means includes data bus means, said central processing means includes data terminals, and said second random access memory means includes data terminals connected to the data terminals of said central processing means through said data bus means.
7. Microcomputer apparatus according to Claim l;
further including display means for displaying a video picture in response to video data stored in said second random access memory means.
further including display means for displaying a video picture in response to video data stored in said second random access memory means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56092826A JPS57207970A (en) | 1981-06-16 | 1981-06-16 | Microcomputer |
| JP92826/81 | 1981-06-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1181528A true CA1181528A (en) | 1985-01-22 |
Family
ID=14065231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000405102A Expired CA1181528A (en) | 1981-06-16 | 1982-06-14 | Micro computer adapted for use with crt display |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS57207970A (en) |
| AT (1) | AT388620B (en) |
| AU (1) | AU561809B2 (en) |
| CA (1) | CA1181528A (en) |
| DE (1) | DE3222704A1 (en) |
| FR (1) | FR2507799A1 (en) |
| GB (1) | GB2103398B (en) |
| NL (1) | NL8202448A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3308612A1 (en) * | 1983-03-11 | 1984-09-13 | hob Horst Brandstätter, 8502 Zirndorf | Screen arrangement for computer or memory systems |
| GB2137382B (en) * | 1983-08-20 | 1985-12-04 | Christopher John Favero Jordan | Computer memories |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3973244A (en) * | 1975-02-27 | 1976-08-03 | Zentec Corporation | Microcomputer terminal system |
| US4026555A (en) * | 1975-03-12 | 1977-05-31 | Alpex Computer Corporation | Television display control apparatus |
| DE2922540C2 (en) * | 1978-06-02 | 1985-10-24 | Hitachi, Ltd., Tokio/Tokyo | Data processing system |
| JPS6036592B2 (en) * | 1979-06-13 | 1985-08-21 | 株式会社日立製作所 | Character graphic display device |
| JPS57101888A (en) * | 1980-12-16 | 1982-06-24 | Sony Corp | Character display |
| JPS57101887A (en) * | 1980-12-16 | 1982-06-24 | Sony Corp | Character display |
-
1981
- 1981-06-16 JP JP56092826A patent/JPS57207970A/en active Pending
-
1982
- 1982-06-10 AU AU84772/82A patent/AU561809B2/en not_active Ceased
- 1982-06-14 CA CA000405102A patent/CA1181528A/en not_active Expired
- 1982-06-15 GB GB08217266A patent/GB2103398B/en not_active Expired
- 1982-06-16 NL NL8202448A patent/NL8202448A/en not_active Application Discontinuation
- 1982-06-16 FR FR8210537A patent/FR2507799A1/en active Granted
- 1982-06-16 AT AT233082A patent/AT388620B/en not_active IP Right Cessation
- 1982-06-16 DE DE19823222704 patent/DE3222704A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57207970A (en) | 1982-12-20 |
| GB2103398B (en) | 1985-07-17 |
| AU561809B2 (en) | 1987-05-21 |
| ATA233082A (en) | 1988-12-15 |
| FR2507799B1 (en) | 1985-01-04 |
| FR2507799A1 (en) | 1982-12-17 |
| AU8477282A (en) | 1982-12-23 |
| DE3222704A1 (en) | 1982-12-30 |
| GB2103398A (en) | 1983-02-16 |
| NL8202448A (en) | 1983-01-17 |
| AT388620B (en) | 1989-08-10 |
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