CA1116307A - Semi-conductor structures - Google Patents
Semi-conductor structuresInfo
- Publication number
- CA1116307A CA1116307A CA000323760A CA323760A CA1116307A CA 1116307 A CA1116307 A CA 1116307A CA 000323760 A CA000323760 A CA 000323760A CA 323760 A CA323760 A CA 323760A CA 1116307 A CA1116307 A CA 1116307A
- Authority
- CA
- Canada
- Prior art keywords
- cell
- transistors
- square
- transistor
- contact areas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
The invention relates to uncommitted logic arrays comprising semi-conductor structures in integrated circuit form and is concerned with the problems of access to elements of each cell, and packing density, Such a structure is described having an array of cells each of which comprises transistors which are not, or are only partially, interconnected. Some of the transistors have their electrode regions connected to externally accessible contact areas, The transistors are symmetrically arranged in each cell, and the cell may include an outer ring of contact regions which may be connected together in pairs by connecting links buried below an insulating substrate. The arrangement of each cell enables connections to be made to any pair of transistors even from the opposite corner of the cell, and gives good packing density,
The invention relates to uncommitted logic arrays comprising semi-conductor structures in integrated circuit form and is concerned with the problems of access to elements of each cell, and packing density, Such a structure is described having an array of cells each of which comprises transistors which are not, or are only partially, interconnected. Some of the transistors have their electrode regions connected to externally accessible contact areas, The transistors are symmetrically arranged in each cell, and the cell may include an outer ring of contact regions which may be connected together in pairs by connecting links buried below an insulating substrate. The arrangement of each cell enables connections to be made to any pair of transistors even from the opposite corner of the cell, and gives good packing density,
Description
3~ ~
BACKGROUND OF THE INVENTION
The invention relates to microelectronics, and more specifically to semi-conductor structures made by integrated circuit techniques.
It is known to make semi-conductor structures in integrated circuit form which are designed to implement a particular electrical circuit and can therefore only be used for that function. When the initial design and development has been carried'out, therefore, such structures can be produced inexpensively in large quantities.
However, the design and development of such structures is expensive and time-consuming and makes special-purpose integrated circuits less suitable where only relatively few are required. Furthermore, this fact makes special-purpose integrated circuits less suitable for use for experimental purposes.
It is therefore also known to make semi-conductor structures in integrated circuit form as "uncommitted logic arrays". Such structures comprise standard arrangements of circuit components in integrated circuit form which are not, or are only partially connected together by the integrated circuit. They can thus be connected up in a large variety of different ways by external connections to perform particular desired clrcuit functions.
An object of the' invention is to provide an improved semi-conductor structure in integrated cir'cuit fo~m.
A more specific object of the invention is to provide a semi-conductor structure in integrated circuit form with improved external access to the circuit elements.
Another more specific object of the invention is to provide a semi-conductor structure in integrated circuit form with improved packing density.
~RIEE SUM~RY OF T~lE INVENTION
.. . _ . . .. _ According to the invention, there is provided a semi-conductor structure :in integrated circuit form, comprising an array of cells arranged in perpendicular rows and columns, each cell of which comprises a plurality of transistors which are not, or are only partially, in~erconnected, the transistors in each cell being positioned with some lying spaced ~rom each other on the sides of a firs~ square extending around the center of the cell and with the remai~lder lying spaced ~rom each other on the sides o~ a second square extending around the center o~ the cell and parallel to and outside the first square and such that the transistors are symmetrically arranged in the cell with respec~ to perpendicular axes which cross at the center o:E the cell and are respectively aligned with the directions of the said rows and columns and with the diagonals o the said square~, the transistors in each cell having their electrode regions connected to externally access-ible contact areas.
DESCRIPTION OF THE DRAWINGS
. . ~
A microelectronic semi-conductor structure embodylng the invention will now be described, by way of example, with reference to the accompanying dia~rammatic drawings in which:
Figure 1 is a diagrammatic and very much enlarged plan view of part of the structure embodying the invention;
Figures.2 to 5 show symbolic and circuit diagrams of particular circuits and corresponding ways in which a cell 3'~ ~
forming part of the structure of Fig.l may be connected up to dedicate it to perform the functions of the particular circuits; and Figures 6~ to 6G show stages in a method of manufacturing part of one of the cells in the structure of Fig.l.
DESCRIPTION OF_PRE~ERRE~ EMBO_DIMENTS
The microelectronic semi-conductor structure now to be described, part of which is shown diagrammaticaly in Figure 1, comprises an array of "cells", each cell comprising, in this example, four pairs of transistors. In each cell the two transistors of each pair are partially connected together, but otherwise the transistors in the cell are not interconnPcted, and instead contact areas are provided by which connections can be made tothe transistors; n~ither are the cells of the array interconnected. The array is thus uncommitted to any particular circuit or function. Therefore, by the super-imposition on to the array of a pattern of electrical conductors, the transistors of the cells can be connected together within each cell and, if desired, with transistors in one or more ~ 7 /
other cells, and in this way one or mor0 cells in the array may be arrangecl to form one or more circuits dedicated to a particular func-tion.
It is emphasized that the array is made by-integrated 5 circuit techni~ues in miniaturisecl form. For example, an array comprising ~40 cells, each containing four transistor pairs, may occupy an area appro~imately 0.5 cms square.
The array will now be described in more detail with reference to ~igure 1 which shows four cells I, II, III and IV
on a substrate 5 having a layer of electrical insulation over it.
As shown, cell I comprises ~our transistor pairs, a first pair comprising transistors 6A and 8A, a second pair comprising transistors 6B and 8BJ a third pair comprising transis-tors 6C and 8C, and a fourth pair comprising transistors 6D and 8DO
~s shown, the transistors are physically arranged to lie on outer and inner rings, the outer ring comprising transistors 6A, 6B, 6C and 6D, and the inner ring comprising transistors r 8A, 8B,8C and 8D. In this example, the transistors of the outer ring are N type field effect transistors, while the transistors of the inner ring are P type.
Within each transistor pair, the gate of the transistor in the inner ring is directly connected (via a connection indicated at 10A in the case of the transistor pair 6A, 8A and by correspondlng connections in the case of the other transistor pairs) to the gate of the transistor in the outer ring.
i3~7 ., However, -the connections 101~, lOB, lOC and lOD are the only connections be-tween the transistors. ~s is shown in the case OI transis-tors 6A and 8~,tlle gate o transistor 6~
is brought out to a contact pad area 24A, its source and drain regions are brought oul; to contact areas 26A and 28A
respectively, and the source and drain regions of the transistor 8A are respectively brought out to contac-t areas 30 and 32A, The same arrangement is provided for the transistors 6B and 8B and their contact areas are referenced similarly to those of the transistors 6A and 8A (but with a suffix B)- e~cept for contact pad 30; it will be seen that the latter is shared with transistor 8B and therefore connects the two transistors together.
Transistors 6C and 8C, and 6D and 8D, are similarly arranged and connected but a:re not connected to the transistors 6A and 8A, and 6B and 8B.
Power supply connections are brought up from the underside of and through the substrate 5 and are connected to a contact area 34 (positive) and to contact areas 36 and 38 (negative).
Each cell includes an outer ring of contact areas arranged in pairs, as shown at 40 and 42, 44 and 46, 48 and 50, 52 and 54, 56 and 58, and 60 and 62.As shown, the contact areas of each such pair are connected together by a link 64 but the contact areas are not otherwise connected. The ].ink 64is through the substrate and under the insulating layer on it.
3~J 7 ; ~11 the contact areas are accessible through the insulating layer on the substra-te.
The arrangement of each of the other cells of the array is the same as shown ~or cell I, and in practice there would be a larKe number o~ cells in tl~e array.
The array therefore provides a large number of cells in each of which the elements (the transistors) are (save for the links lOA, lOB, lOC and lOD and the contact areas 30) unconnected but have their electrode regions brought out to respective contact areas, Each cell therefore provides an array of contact areas by means of which the transistors can be connected together in various ways and can be connected to external circuitry and, if desired, to the transistors in another cell or cells, so as to produce a desired circuit and in this way to dedicate the cell or cells to a particular function.
The contact areas 40 to 62 in the outer ring of contact of each cell may be used in the interconnection process. They may also, or instead, be used to facilitate connections from one part of the array to another. The links 64, being below the insulating layer on the substrate and thus insulated from the surface, enable incoming connecting links to enter towards the inner part of the cell by passing across the insulating layer on the substrate and over the links 64.
In order to carry out the interconnection process, a .
suitable pattern of conductors is made up, such as in aluminium by a known process, and the pa-ttern of conduc-tors is then placed over the array so that the condl.lctors connect up the contact areas in the desired manner.
Figure~s 2 to 5.show, by way of example, ways in which the contact areas of a cell may be i.n-terconnec-ted (in -the manner described, by means of a pat-tern of conductors) so as to interconnect the transistors of the cell to perform a particular function or functions.
Figure 2 shows the cell connected to perform two functions, that of an inverter and of a 3-input NAND gate. Figure 2A
shows symbolically and schematically the circuit of` the inverter, while Figure 2B shows symbolically and schematically the circuit o~ the 3-input NAND gate. Figure 2C shows the cell with the connections superimposed on it to dedicate the ceil to perform the functions of -the circuits in Figures 2A
and 2B In Figure 2C, the connections corresponding to Figure 2A are shown by dotted line, while those corresponding to Figure 2B are shown by full line.
Figure 3 again shows the cell connected to perform two ~unctions, this time that of a 2-in~ut NOR gate and of a
BACKGROUND OF THE INVENTION
The invention relates to microelectronics, and more specifically to semi-conductor structures made by integrated circuit techniques.
It is known to make semi-conductor structures in integrated circuit form which are designed to implement a particular electrical circuit and can therefore only be used for that function. When the initial design and development has been carried'out, therefore, such structures can be produced inexpensively in large quantities.
However, the design and development of such structures is expensive and time-consuming and makes special-purpose integrated circuits less suitable where only relatively few are required. Furthermore, this fact makes special-purpose integrated circuits less suitable for use for experimental purposes.
It is therefore also known to make semi-conductor structures in integrated circuit form as "uncommitted logic arrays". Such structures comprise standard arrangements of circuit components in integrated circuit form which are not, or are only partially connected together by the integrated circuit. They can thus be connected up in a large variety of different ways by external connections to perform particular desired clrcuit functions.
An object of the' invention is to provide an improved semi-conductor structure in integrated cir'cuit fo~m.
A more specific object of the invention is to provide a semi-conductor structure in integrated circuit form with improved external access to the circuit elements.
Another more specific object of the invention is to provide a semi-conductor structure in integrated circuit form with improved packing density.
~RIEE SUM~RY OF T~lE INVENTION
.. . _ . . .. _ According to the invention, there is provided a semi-conductor structure :in integrated circuit form, comprising an array of cells arranged in perpendicular rows and columns, each cell of which comprises a plurality of transistors which are not, or are only partially, in~erconnected, the transistors in each cell being positioned with some lying spaced ~rom each other on the sides of a firs~ square extending around the center of the cell and with the remai~lder lying spaced ~rom each other on the sides o~ a second square extending around the center o~ the cell and parallel to and outside the first square and such that the transistors are symmetrically arranged in the cell with respec~ to perpendicular axes which cross at the center o:E the cell and are respectively aligned with the directions of the said rows and columns and with the diagonals o the said square~, the transistors in each cell having their electrode regions connected to externally access-ible contact areas.
DESCRIPTION OF THE DRAWINGS
. . ~
A microelectronic semi-conductor structure embodylng the invention will now be described, by way of example, with reference to the accompanying dia~rammatic drawings in which:
Figure 1 is a diagrammatic and very much enlarged plan view of part of the structure embodying the invention;
Figures.2 to 5 show symbolic and circuit diagrams of particular circuits and corresponding ways in which a cell 3'~ ~
forming part of the structure of Fig.l may be connected up to dedicate it to perform the functions of the particular circuits; and Figures 6~ to 6G show stages in a method of manufacturing part of one of the cells in the structure of Fig.l.
DESCRIPTION OF_PRE~ERRE~ EMBO_DIMENTS
The microelectronic semi-conductor structure now to be described, part of which is shown diagrammaticaly in Figure 1, comprises an array of "cells", each cell comprising, in this example, four pairs of transistors. In each cell the two transistors of each pair are partially connected together, but otherwise the transistors in the cell are not interconnPcted, and instead contact areas are provided by which connections can be made tothe transistors; n~ither are the cells of the array interconnected. The array is thus uncommitted to any particular circuit or function. Therefore, by the super-imposition on to the array of a pattern of electrical conductors, the transistors of the cells can be connected together within each cell and, if desired, with transistors in one or more ~ 7 /
other cells, and in this way one or mor0 cells in the array may be arrangecl to form one or more circuits dedicated to a particular func-tion.
It is emphasized that the array is made by-integrated 5 circuit techni~ues in miniaturisecl form. For example, an array comprising ~40 cells, each containing four transistor pairs, may occupy an area appro~imately 0.5 cms square.
The array will now be described in more detail with reference to ~igure 1 which shows four cells I, II, III and IV
on a substrate 5 having a layer of electrical insulation over it.
As shown, cell I comprises ~our transistor pairs, a first pair comprising transistors 6A and 8A, a second pair comprising transistors 6B and 8BJ a third pair comprising transis-tors 6C and 8C, and a fourth pair comprising transistors 6D and 8DO
~s shown, the transistors are physically arranged to lie on outer and inner rings, the outer ring comprising transistors 6A, 6B, 6C and 6D, and the inner ring comprising transistors r 8A, 8B,8C and 8D. In this example, the transistors of the outer ring are N type field effect transistors, while the transistors of the inner ring are P type.
Within each transistor pair, the gate of the transistor in the inner ring is directly connected (via a connection indicated at 10A in the case of the transistor pair 6A, 8A and by correspondlng connections in the case of the other transistor pairs) to the gate of the transistor in the outer ring.
i3~7 ., However, -the connections 101~, lOB, lOC and lOD are the only connections be-tween the transistors. ~s is shown in the case OI transis-tors 6A and 8~,tlle gate o transistor 6~
is brought out to a contact pad area 24A, its source and drain regions are brought oul; to contact areas 26A and 28A
respectively, and the source and drain regions of the transistor 8A are respectively brought out to contac-t areas 30 and 32A, The same arrangement is provided for the transistors 6B and 8B and their contact areas are referenced similarly to those of the transistors 6A and 8A (but with a suffix B)- e~cept for contact pad 30; it will be seen that the latter is shared with transistor 8B and therefore connects the two transistors together.
Transistors 6C and 8C, and 6D and 8D, are similarly arranged and connected but a:re not connected to the transistors 6A and 8A, and 6B and 8B.
Power supply connections are brought up from the underside of and through the substrate 5 and are connected to a contact area 34 (positive) and to contact areas 36 and 38 (negative).
Each cell includes an outer ring of contact areas arranged in pairs, as shown at 40 and 42, 44 and 46, 48 and 50, 52 and 54, 56 and 58, and 60 and 62.As shown, the contact areas of each such pair are connected together by a link 64 but the contact areas are not otherwise connected. The ].ink 64is through the substrate and under the insulating layer on it.
3~J 7 ; ~11 the contact areas are accessible through the insulating layer on the substra-te.
The arrangement of each of the other cells of the array is the same as shown ~or cell I, and in practice there would be a larKe number o~ cells in tl~e array.
The array therefore provides a large number of cells in each of which the elements (the transistors) are (save for the links lOA, lOB, lOC and lOD and the contact areas 30) unconnected but have their electrode regions brought out to respective contact areas, Each cell therefore provides an array of contact areas by means of which the transistors can be connected together in various ways and can be connected to external circuitry and, if desired, to the transistors in another cell or cells, so as to produce a desired circuit and in this way to dedicate the cell or cells to a particular function.
The contact areas 40 to 62 in the outer ring of contact of each cell may be used in the interconnection process. They may also, or instead, be used to facilitate connections from one part of the array to another. The links 64, being below the insulating layer on the substrate and thus insulated from the surface, enable incoming connecting links to enter towards the inner part of the cell by passing across the insulating layer on the substrate and over the links 64.
In order to carry out the interconnection process, a .
suitable pattern of conductors is made up, such as in aluminium by a known process, and the pa-ttern of conduc-tors is then placed over the array so that the condl.lctors connect up the contact areas in the desired manner.
Figure~s 2 to 5.show, by way of example, ways in which the contact areas of a cell may be i.n-terconnec-ted (in -the manner described, by means of a pat-tern of conductors) so as to interconnect the transistors of the cell to perform a particular function or functions.
Figure 2 shows the cell connected to perform two functions, that of an inverter and of a 3-input NAND gate. Figure 2A
shows symbolically and schematically the circuit of` the inverter, while Figure 2B shows symbolically and schematically the circuit o~ the 3-input NAND gate. Figure 2C shows the cell with the connections superimposed on it to dedicate the ceil to perform the functions of -the circuits in Figures 2A
and 2B In Figure 2C, the connections corresponding to Figure 2A are shown by dotted line, while those corresponding to Figure 2B are shown by full line.
Figure 3 again shows the cell connected to perform two ~unctions, this time that of a 2-in~ut NOR gate and of a
2-input NAND gate. Figure 3A shows symbolically and schemat-ically the circuit of the NOR gate, while Figure 3B shows symbolically and schematically the circuit of the NAND gate Figure 3C shows the cell Witil the connections superimposed on it to dèdicate the cell to perform the functions of the $3~
circuits in Figures 3A and 3B. In Figure 3C, the connections corresponding to Figure 3A are shown by do-tted line, while those corresponding to Figure 3B are shown by ~ull line.
Figure ~ StlOWS the cell connectecl to perform a single ~unction, that of` two 2-input AND gates ~eeding into a 2-input NOR gate. Figure ~ shows symbolically and schematically the correspotlding circuit. Figure 4B shows the cell with the connections superimpo~ed on it to dedicate the cell to perform the ~unction oi the circuit of Figure 4A.
Figure 5 again showsthe cell connected to perform a single ~unction, this time that o~ a change-over circuit using a pair of transmission gates and an inverter. Figure 5~ shows symbolically and schematically the circuit, while Figure 5B
shows the cell with the connections superimposed on it to dedicate the cell to per~orm the ~unction of the circuit.
Figures 2 to 5 show examples of the very wide variety of circuits that can be achieved (the circuits shown represent only a very small proportion of the number possible) and also show the ease with which connections can be made to any contact area of a cell, yet leaving space for other connections to be made past the cell to cells in other parts o~ the array or connections for connecting the cells together. These advan-tages result from a number o~ ~actors in the design.
It is found that iour transistor pairs for each cell is the optimum. For most circuit iunctions, this enables a single cell to be sufficient for performing the function, but at the same time cloes no-t result in any substantial underuse of the transistors.
The ar rangemen-t O;r the transistors Oe each cell in inner and outer rings also facilitatetheir connection.
The general symmetry of each cell is also advantageous.
It is found that many circuit Iunc-tions require at least two transistors each wi-th one of its electrode regions connected to one of the electrode regions of the other, and the cell arrangement used is therefore advantageous in that this inter-connection is "built in" in the form of the common contact areas 30. Reference to Figures 3A and 3C illustrates this.
The contact area 30 is indicated in Figure 3~, and the points at which connections between transistors are required to be added (by externally connecting appropriate ones of the contact areas of the cell) are indicated by "X". Therefore, -the circuit function can be achieved with only five inter-connections (besides the input and output connections).
The outer ring of contacts 40 to 62 facilitates the formation of through connections from one cell to another and the buried links 64 allow cross-over connections.
The arrangement of each cell enables connections to be made to any pair of transistors even from the opposits corner of the cell.
The arrangement of the cell therefore gives extremely good utilisation of the totalarea of silicon, This is important for reasons of cost, There will inevitably be a certain number of crystal structure fau]ts resulting from the production process, and there will tllerefore be a certain amount oI
wastage. 'l`he excellent packinG density achieved by the cell arrangemellt minimises this wastage.
Figures 6~ to 6F illustrate ~riefly and diagran~natically the method of manuac-turing the array, in this case a part of the array comprising a pair of the transistors, one N type, one P type.
Initially, a substrate 5 of N doped silicon is produced and then formed into "lands" 68, 69 some of which are P-doped as shown a-t 70 and 71 in Fig.6A.
~ thin oxide layer 72 is thenformed on the top of each land (Fig.6B).
Layers 74, 76 of polysilicon are then placed on top of each land, over tbe oxide layer thereon (Fig.6C). The remainder of oxide layer on each land is then removed, Fig.6D.
Then, in two separate steps, N and P impurities are diffused in to the material of the lands, N ma-terial being doped in where an N type transistor is to be formed (as shown on the~lefthand side of Figure 6E) and P material being doped in where a P type transistor is to be formed (as shown at the righthand side of Figure 6E). During this doping process, each polysilicon layer defines an undiffused region 80,82 underneatb .
, - ' ' ' .
i-t which forms the channel of the transistor. The polysilicon layers form -the gates of the transistors, As shown in Figure 6D, a tllick layer 8~ of oxide is then grown over the wllole structure and (Fig.6G) holes 86 are then etched -throu~ll by means oE which contact may be made to the contact areas of the structure.
The Ioregoing s-teps are carried out by a series of separate maslcing processes followed hy etching processesO
The array now has the form shown in Figo 1~
lQ As already explained, in order to dedicate the array to form particular circui~.-t functions, the contact areas are connected up together and to external connections in -the desired manner by means of a pattern o:E conductors. When this pattern of conductors has b0en placed over -the array and connected to the contact areas, the whole is covered by depositing glass on it and the circuits are then completed.
' ,
circuits in Figures 3A and 3B. In Figure 3C, the connections corresponding to Figure 3A are shown by do-tted line, while those corresponding to Figure 3B are shown by ~ull line.
Figure ~ StlOWS the cell connectecl to perform a single ~unction, that of` two 2-input AND gates ~eeding into a 2-input NOR gate. Figure ~ shows symbolically and schematically the correspotlding circuit. Figure 4B shows the cell with the connections superimpo~ed on it to dedicate the cell to perform the ~unction oi the circuit of Figure 4A.
Figure 5 again showsthe cell connected to perform a single ~unction, this time that o~ a change-over circuit using a pair of transmission gates and an inverter. Figure 5~ shows symbolically and schematically the circuit, while Figure 5B
shows the cell with the connections superimposed on it to dedicate the cell to per~orm the ~unction of the circuit.
Figures 2 to 5 show examples of the very wide variety of circuits that can be achieved (the circuits shown represent only a very small proportion of the number possible) and also show the ease with which connections can be made to any contact area of a cell, yet leaving space for other connections to be made past the cell to cells in other parts o~ the array or connections for connecting the cells together. These advan-tages result from a number o~ ~actors in the design.
It is found that iour transistor pairs for each cell is the optimum. For most circuit iunctions, this enables a single cell to be sufficient for performing the function, but at the same time cloes no-t result in any substantial underuse of the transistors.
The ar rangemen-t O;r the transistors Oe each cell in inner and outer rings also facilitatetheir connection.
The general symmetry of each cell is also advantageous.
It is found that many circuit Iunc-tions require at least two transistors each wi-th one of its electrode regions connected to one of the electrode regions of the other, and the cell arrangement used is therefore advantageous in that this inter-connection is "built in" in the form of the common contact areas 30. Reference to Figures 3A and 3C illustrates this.
The contact area 30 is indicated in Figure 3~, and the points at which connections between transistors are required to be added (by externally connecting appropriate ones of the contact areas of the cell) are indicated by "X". Therefore, -the circuit function can be achieved with only five inter-connections (besides the input and output connections).
The outer ring of contacts 40 to 62 facilitates the formation of through connections from one cell to another and the buried links 64 allow cross-over connections.
The arrangement of each cell enables connections to be made to any pair of transistors even from the opposits corner of the cell.
The arrangement of the cell therefore gives extremely good utilisation of the totalarea of silicon, This is important for reasons of cost, There will inevitably be a certain number of crystal structure fau]ts resulting from the production process, and there will tllerefore be a certain amount oI
wastage. 'l`he excellent packinG density achieved by the cell arrangemellt minimises this wastage.
Figures 6~ to 6F illustrate ~riefly and diagran~natically the method of manuac-turing the array, in this case a part of the array comprising a pair of the transistors, one N type, one P type.
Initially, a substrate 5 of N doped silicon is produced and then formed into "lands" 68, 69 some of which are P-doped as shown a-t 70 and 71 in Fig.6A.
~ thin oxide layer 72 is thenformed on the top of each land (Fig.6B).
Layers 74, 76 of polysilicon are then placed on top of each land, over tbe oxide layer thereon (Fig.6C). The remainder of oxide layer on each land is then removed, Fig.6D.
Then, in two separate steps, N and P impurities are diffused in to the material of the lands, N ma-terial being doped in where an N type transistor is to be formed (as shown on the~lefthand side of Figure 6E) and P material being doped in where a P type transistor is to be formed (as shown at the righthand side of Figure 6E). During this doping process, each polysilicon layer defines an undiffused region 80,82 underneatb .
, - ' ' ' .
i-t which forms the channel of the transistor. The polysilicon layers form -the gates of the transistors, As shown in Figure 6D, a tllick layer 8~ of oxide is then grown over the wllole structure and (Fig.6G) holes 86 are then etched -throu~ll by means oE which contact may be made to the contact areas of the structure.
The Ioregoing s-teps are carried out by a series of separate maslcing processes followed hy etching processesO
The array now has the form shown in Figo 1~
lQ As already explained, in order to dedicate the array to form particular circui~.-t functions, the contact areas are connected up together and to external connections in -the desired manner by means of a pattern o:E conductors. When this pattern of conductors has b0en placed over -the array and connected to the contact areas, the whole is covered by depositing glass on it and the circuits are then completed.
' ,
Claims (8)
1. A semi-conductor structure in integrated circuit form, comprising an array of cells arranged in perpendicular rows and columns, each cell of which comprises a plurality of transistors which are not, or are only partially, interconnected, the transistors in each cell being positioned with some lying spaced from each other on the sides of a first square extending around the center of the cell and with the remainder lying spaced from each other on the sides of a second square extending around the center of the cell and parallel to and outside the first square and such that the transistors are symmetrically arranged in the cell with respect to perpendicular axes which cross at the center of the cell and are respectively aligned with the directions of the said rows and columns and with the diagonals of the said squares, the transistors in each cell having their electrode regions connected to externally access-ible contact areas.
2. A structure according to claim 1, in which each cell comprises a plurality of pairs of partially interconnected transistors, one transistor of each pair being a field effect N type transistor and the other transistor of each pair being a field effect P-type transistor, one transistor of each pair lying on the first square and the other transistor of each pair lying on the second square.
3. A structure according to claim 2, in which in each pair the gate region of one of the transistors is connected to the gate region of the other.
4. A structure according to claim 1, in which there are four pairs of transistors in each cell.
5. A structure according to claim 4, in which one, only, of the electrode regions of each of the transistors of the first square is connected to one of the electrode regions of one, only, of the other transistors of the first square.
6. A structure according to claim 1, in which each cell includes contact regions which are not connected to the trans-istors and lie on a third square extending around the center of the cell parallel to and outside the first and second squares.
7. A system according to claim 6, in which at least some of the contact regions are connected together in pairs by connecting links which are buried below insulating material and which lie on the sides of the said third square,
8. A generally planar semi-conductor structure, made up of an array of cells and in which each cell comprises a substrate, eight field effect transistors integrated into the substrate, the first four of which respectively lie on the sides of a first square symmetrically disposed with reference to the center of the cell, each transistor of the other four being associated with a respective one of the transistors of the first four and lying adjacent to it and on a respective side of a second square outside of and with its sides parallel to the said first square and each transistor of the said other four having its gate region directly connected to the gate region of the associated transistor, contact areas respectively connected to all the electrode regions of all the transistors except for the gate regions of all the transistors of the first four, the contact areas being symmetrically disposed within the cell, each transistor of the first four having one, only, of its two electrode regions connected to the same contact area as the corresponding electrode of one, only, of the adjacent transistors of the first four, and a symmetrically arranged plurality of further contact areas unconnected to the transistors and arranged outside the first and second squares, and lying on the sides of a third square which are parallel to the sides of the first and second squares, the said further contact areas being in pairs with the contact areas of each such pair being connected together by conducting paths below the electrically insulating layer, all the contact areas being accessible externally of the cell through a layer of electrically insulating material on the substrate so as to enable the transistors of each cell to be connected together in any desired manner to provide a required circuit function, the cells being arranged in the said array in rows and columns with the sides of the said squares being inclined to the directions of the rows and columns to facilitate connections to the said contact areas by means of conductors running between the rows and columns,
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1282978 | 1978-04-01 | ||
| GB12829/78 | 1978-04-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1116307A true CA1116307A (en) | 1982-01-12 |
Family
ID=10011906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000323760A Expired CA1116307A (en) | 1978-04-01 | 1979-03-19 | Semi-conductor structures |
Country Status (3)
| Country | Link |
|---|---|
| CA (1) | CA1116307A (en) |
| DE (1) | DE2912817A1 (en) |
| FR (1) | FR2421467A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3365707A (en) * | 1967-06-23 | 1968-01-23 | Rca Corp | Lsi array and standard cells |
| US3772536A (en) * | 1967-09-20 | 1973-11-13 | Trw Inc | Digital cell for large scale integration |
| GB1440512A (en) * | 1973-04-30 | 1976-06-23 | Rca Corp | Universal array using complementary transistors |
| US3999214A (en) * | 1974-06-26 | 1976-12-21 | Ibm Corporation | Wireable planar integrated circuit chip structure |
-
1979
- 1979-03-19 CA CA000323760A patent/CA1116307A/en not_active Expired
- 1979-03-30 DE DE19792912817 patent/DE2912817A1/en not_active Withdrawn
- 1979-03-30 FR FR7908131A patent/FR2421467A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| FR2421467A1 (en) | 1979-10-26 |
| DE2912817A1 (en) | 1979-10-11 |
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