DE2912817A1 - SEMI-CONDUCTOR ARRANGEMENT - Google Patents

Description

March 28, 1979 9366 - S / kn

Racal Microelectronic Systems Limited

Semiconductor arrangement

The invention relates to a semiconductor arrangement in the form of an integrated circuit, with a row or group of cells, each of which has a multiplicity of transistors which are not or only partially connected to one another, the transistors in each cell are connected with their electrode sections with externally accessible contact surfaces.

It is known to produce semiconductor arrangements in the form of integrated circuits which are designed in such a way that a special electrical circuit is fulfilled and can therefore only be used for this function. Once the design and development are done, such assemblies can be inexpensively manufactured in large quantities.
However, such arrangements are expensive to design and develop

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and time consuming and makes special purpose integrated circuits less suitable, if only relatively few of them integrated circuits are required. This fact also leaves fewer special purpose integrated circuits can be used for experimental purposes. It is also known to have integrated semiconductor devices Circuit form as "unbound logical series (groupings)" to manufacture. Such arrangements have standard arrangements of circuit components in integrated circuit form, the are not or only partially interconnected by the integrated circuit. You can therefore use a wide variety of Way to be connected by external connections to the specially perform the desired circuit functions.

The invention is based on the object of providing an improved semiconductor arrangement in the form of an integrated circuit create.

This object is achieved according to the invention by the subject matter of Claim 1 solved.

Further refinements of the invention emerge from the subclaims.

The invention provides a semiconductor device in integrated circuit form with improved external access to the Circuit elements. The semiconductor arrangement according to the invention in Integrated circuit form also has improved packing density.

The invention relates generally to microelectronics and specifically to semiconductor arrangements that are produced by integrated switching

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ORIGINAL INSPECTED

processing techniques are formed.

The semiconductor arrangement according to the invention has a row or grouping of cells, each of which has a plurality of Contains transistors that are not or only partially connected to one another; of the transistors in each cell are theirs Electrode sections connected to externally accessible contact surfaces, the transistors being arranged symmetrically in each cell are.

An embodiment of a microelectronic semiconductor device according to the invention is described below with reference to FIG Description of the drawing to explain further features. Show it:

Fig. 1 is a schematic and greatly enlarged plan view part of the arrangement according to the invention,

FIGS. 2 to 5 symbolic diagrams and circuit diagrams special circuits and corresponding ways with which a cell * forming part of the arrangement according to FIG. can be made to perform the functions of special circuits ,, and

FIGS. 6A to 6G manufacturing stages for part of one of the cells the arrangement according to FIG. 1.

The microelectronic semiconductor arrangement described below, a portion of which is shown schematically in FIG. 1 comprises a row or grouping of "cells", each cell at the illustrated embodiment contains four transistor pairs. In each Cell, the two transistors of each pair are partially connected to each other, on the other hand, the transistors are in the cell

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* tied together

are not connected to each other and instead are contact surfaces provided through which the connections to the transistors are made; neither are the cells of the grouping with each other tied together. The grouping is therefore opposite pjer special circuit or function unbound. Therefore, by superimposing a pattern of electrical conductors on top of the Grouping or row (of cells) the transistors of the cells within each cell are interconnected and - if desirable - with the transistors in one or more of the others Cells; in this way one or more cells of the array can be arranged to form one or more circuits that are available for a special function.

It is emphasized that the series or grouping by integrated Circuit techniques are formed in miniaturized form. For example, a group can have 440 cells, each of which has four

Contains transistor pairs, occupy an area of about 0.5 cm.

This group will now be described in detail with reference to FIG explains which four cells I, II, III and IV are on a substrate 5 with an electrical insulating layer above it.

From Fig. 1 it is seen that cell I contains four transistor pairs, namely a first pair consisting of transistors 6A and 8A, a second pair consisting of transistors 6B and 8B, a third pair consisting of transistors 6C and 6C SC, a fourth pair consisting of transistors 6Ό and 8D. Referring to Fig. 1, the transistors are physically arranged to lie on outer and inner rings, the outer ring having transistors 6A, 6B, 6C and 6D, while the inner ring has transistors 8A,

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8B, 8C and 8D. In this example, the transistors of the outer ring are N field effect transistors, while the transistors of the inner ring are P-type field effect transistors.

Inside each transistor pair is the control electrode (gate) of the Transistor in the inner ring directly (via a connection, which in the case of the transistor pair 6A, 8A is designated 1OA, and through corresponding connections with respect to the remaining transistor pairs) connected to the control electrode of the transistor in the outer ring. Connections 10A, 10B, IOC and IOD are the only connections between the transistors. From the drawing it can be seen that with respect to the transistors 6A and 8A, the control electrode of the Transistor 6A are led out to a contact track surface 24A, the source and drain regions of which to contact surfaces 26A and 28A are led; the source and drain regions of the transistor 8A are each led to contact areas 30 and 32A. The same arrangement is provided with respect to the transistors OB and 8B, and their contact areas are in a similar manner as compared to those of the transistors 6A and 8A, but provided with an addition B, with the exception of the contact pad 30; it can be seen that the contact area 30 is shared with the transistor 8B and therefore connects the two transistors to one another.

The transistors 6C and 8C, and 6D and 8D are arranged and connected in a similar manner, but not connected to the transistors 6A and 8A and 63 and 8B.

The feed connections are brought up from the bottom and through the substrate 5 and are connected to a contact area 34 (positive) and to contact areas 36 and 38 (negative).

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Each cell contains an outer ring of contact surfaces that are arranged in pairs, as indicated by reference numerals 40 and 42, 44 and 46, 48 and 50, 52 and 54, 56 and 58, 60 and 62 are shown is. The contact surfaces of each such pair are interconnected by a link 64, but the contact surfaces are not connected in any other way. The connector 64 passes through the substrate and under the insulating layer thereon.

All contact areas are through the insulating layer on the substrate accessible,

The arrangement of each of the remaining cells in the grouping is the same as shown for cell I; in the Practice consists of large numbers of cells in grouping.

The grouping therefore provides a large number of cells in which in each case the elements (transistors) - apart from the connecting pieces 10A, 103, IOC, IOD and the contact surfaces 30 - not connected are, however, their electrode portions are through the associated Contact surfaces led to the outside. Each cell therefore provides a series or group of contact surfaces by means of which the transistors can be connected together in various ways and can be connected to external circuitry and, if desired, with the transistors in another cell or cells, so that the desired switching is possible will; in this way the cell is designed or grounded for a specific function.

The contact surfaces 40 to 62 in the outer ring of the contact each Cells can be used in the interconnection process. They can also or instead be used to make connections

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from one part of the group to another to facilitate. The connectors 64 that are below the insulating layer on the substrate and are thus isolated from the surface, allow incoming connectors towards the interior Part of the cell can be guided or reached by passing it over the insulating layer on the substrate and over the connecting pieces 64 happen.

To carry out the interconnection process, a suitable pattern of conductors is formed, such as in aluminum through a known method and the conductor pattern is then placed over the groupinj so that the conductors make contact surfaces in the connect in the way you want.

2 to 5 show, for example, ways in which the contact surfaces of the cell - in the manner described by means of

A conductor pattern - can be connected together so that the transistors of the cell are connected to a specific one To perform function or functions.

Figure 2 shows the cell connected to perform two functions, namely that of an inverter and a NAND gate with three inputs. FIG. 2A shows symbolically and schematically the circuit of the inverter, while FIG. 2B symbolically and schematically illustrates the circuit of the NAND gate with three inputs. Fig. 2C shows the cell, where the Connections are placed on it so that the cell is tuned to the functions of FIGS. 2A and 2B. In Fig. 2C are Connections corresponding to those in Fig. 2A are shown by a dashed line, while those connections, which correspond to Fig. 2B are fully marked.

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Fig. 3 shows the cell which is connected or switched in such a way that that it performs two functions, namely one function NOR gate with two inputs and a NAND gate with two inputs. Fig. 3A shows symbolically and schematically the circuit of the NOR gate, while Fig. 3B symbiotic and scheraatically the Represents the circuit of the NAND gate. Figure 3C shows the cell, where the connections are superimposed on it to enable this cell to perform the functions of the circuits of Figures 3A and 3B is turned off. In Fig. 3C are connections similar to those in Fig. 3A correspond, shown in dashed lines, while the connections corresponding to Fig. 3B are fully marked.

Fig. 4 shows the cell in a circuit so that a single function is carried out, namely that of two AND gates with two inputs that lead to a NOR gate with two inputs. 4A shows symbolically and schematically the corresponding circuit. Fig. 4B shows the cell with prebindings superimposed on it, so that it performs the function of the circuit of FIG. 4A.

FIG. 5 again shows the cell which is switched in such a way that a single function is carried out, namely the function of a toggle Circuit using a pair of transmission links and an inverter. Fig. 5A shows symbolically and schematically the circuit, while Fig. 5B shows the cell with connections superimposed on it to enable the function of the circuit executes.

Figs. 2 to 5 show examples of a very large variety of circuits, which are achievable (the circuits shown represent only a very small ratio of the possible number) and also show the ease with which the connections

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can be made to any contact area of the cell, but leaving room for other connections to be made later to the cell or to cells in other parts of the grouping or for connections to be made to the cells with one another 21 connect. These advantages result from a large number of Factors in the conception or * in the design.

It has been found that four transistor pairs for each cell is an optimum. For most switching functions it is possible in that a single cell is sufficient to carry out the function, while at the same time not in one Underutilization of the transistor results.

The arrangement of the transistors in each cell in the inner and outer rings also simplifies their interconnection.

The general symmetry of each cell is also beneficial. It has been found that many circuit functions require at least two transistors, each of which has an electrode region connected to an electrode region of the other transistor; the cell arrangement used is therefore advantageous in that this interconnection is "built in" in the form of the common contact surfaces 30. This can be seen from FIGS. 3A and 3C. The contact surface 30 is shown in Figure 3A; the points at which connections between the transistors are required to be added (by external connection of corresponding contact surfaces of the cell) ₁ are indicated by the reference ^{numeral 11} X ". The circuit function can therefore with only five interconnections (besides the input and output connections ) can be achieved.

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The outer ring of contacts 40-62 facilitates the formation of cell-to-cell vias and cell-to-cell through-connections Countersunk or embedded connectors 64 enable crossover connections.

The arrangement of each cell allows connections to each pair of transistors to be made from the opposite corner of the Cell can be manufactured.

The arrangement of the cell therefore provides extremely good use of the total area of silicon. This is important for reasons of cost. Inevitably, there will be a certain number of crystal arrangement errors resulting from the manufacturing process and there will therefore be a certain amount of scrap. The excellent packing density achieved by the cell arrangement minimizes this waste.

Figures 6A to 6F show briefly and schematically the process of making the group, in which case part of the group comprises a pair of transistors, namely an IN-type transistor and a P-type transistor.

First, a substrate 5 with N-doped silicon is produced and then formed into "islands" 68,69, some of which are P-doped, as shown at 70 and 71 in Figure 6A. A thin one Oxide layer 72 is then formed on top of each island (Figure 6B).

The layers 74, 76 of polysilicon (polysilicon) are then placed on top of each island, over the oxide layer foefindiishs thereon (Fig _o 6C) _O the remainder of the oxide layer on jsdsr Στι? · 3ΐ v; £. " C5 er / c $ ®xwt _e like c? ys Fif »<SB emerges <,

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Then N and P purifications are made in two separate steps diffuses into the material of the islands, with the N material there is doped where an N-type transistor is to be formed (as on the left side of Fig. 6E), while the P material is doped where a P-type transistor is to be formed (as shown on the right-hand side of Figure 6E). While of the doping process, each polysilicon layer defines an undiffused area 80, 82 below it, which is the Channel of the transistor forms. The polysilicon layers form the control electrodes of the transistors.

As can be seen from FIG. 6D, a thick layer of oxide is then grown over the entire arrangement and becomes as shown in FIG. 6G then holes 86 are etched through, by means of which contact is made with the contact surfaces of the structure.

The foregoing steps are carried out by a series of separate masking processes followed by etching processes. The output then has the form shown in FIG.

As already described, - so that the ^r ; Grouping certain circuit functions are granted - the contact surfaces are interconnected and connected to external connections in the desired manner by means of a conductor diagram. When this pattern or pattern of conductors has been placed over the array and connected to the pads, the whole is covered by deposits of glass on it and the circuits are completed.

Claims (12)

March 28, 1979 9366 - S / kn Racal Microelectronic Systems Limited Bracknell, Berkshire, England Claims 1.1 Semiconductor arrangement in the form of an integrated circuit, rait a row or group of cells, each of which has a large number of transistors that are not or only partially connected to one another, the traisistors in each cell with their electrode sections from the outside accessible contact surfaces are connected,
characterized in that the transistors (6A, 6B, ... 8A, 8E>) are arranged symmetrically in each cell. 2. Arrangement according to claim 1, characterized in that each Cell (i, II, III) a multitude of transistor pairs (6A and 8A; etc.) having. 3. Arrangement according to claim 2, characterized in that in each transistor pair (eg 6A and 8A) the gate section of one of the transistors is connected to the gate section of the other transistor via a direct connection (IOA). 9098A1 / 0773 4. Arrangement according to at least one of the preceding claims, characterized in that some of the transistors (8A, 8B, 8C, 8D) essentially! are arranged symmetrically at a first point around the center point of the cell (i, II, III, ...) and that the remaining transistors (6A, 6B, 6C, 6D) are arranged essentially symmetrically at a second point around the center point of the cell and are arranged outside the first position. 5. Arrangement according to claim 4, characterized in that a transistor (e.g. 8A) of each pair is on the first side and that the other. Transistor (e.g. 6A) of each pair is in the second position. 6. Arrangement according to claim 4 or 5, characterized in that the first and second locations are each at right angles stand. 7. Arrangement according to at least one of Claims 2 to 6, characterized in that one transistor of each transistor pair (e.g. 6A and 8A) an N-type transistor and the other transistor of each pair is a P-type transistor. 8. Arrangement according to at least one of claims 2 to 7, characterized characterized in that there are four pairs of transistors in each cell. 9. Arrangement according to claim 8, characterized in that the four pairs of transistors are arranged in two groups (6A, 8A, 6B, 8B; 6C, 8C, 6D _r 8D) and each group consists of two transistor pairs. 909841/0773 10. Arrangement according to claim 9, characterized in that within of each group (e.g. 6A, 8A, 6B, 8B) one of the electrode portions of only one transistor (8A) of the transistor pair with the corresponding one Electrode portion of only one transistor (8B) of the other pair of transistors is connected. 11. The arrangement according to at least one of the preceding claims, characterized in that in each cell (i, II, III, IV) a
outer ring of contact areas (40 to 62) is included, which are not connected to the transistors. 12. The arrangement according to claim 11, characterized in that the Contact areas (40 to 62) in pairs by connecting pieces (64) are interconnected, which are embedded below the insulating material are. / 0773 ORIGINAL INSPECTED