CA1111146A

CA1111146A - Method of manufacturing semiconductor device

Info

Publication number: CA1111146A
Application number: CA282,953A
Authority: CA
Inventors: Jun-Ichi Nishizawa
Original assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
Current assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
Priority date: 1976-07-19
Filing date: 1977-07-18
Publication date: 1981-10-20
Also published as: DE2732582C2; FR2359506A1; DE2732582A1; FR2359506B1; JPS5311572A

Abstract

Abstract of the disclosure A method of manufacturing a semiconductor device including a first and a second region of a low and a high impurity concen-tration located adjacent to each other, comprises the steps of forming the second heavily doped region of a second conductivity type in a semiconductor region of a low impurity concentration, doping a third impurity of a third conductivity type opposite to the second conductivity type in a region into which redis-tribution of that impurity located in the heavily doped region is expected. The concentration of the third impurity is selected so as to substantially compensate for the effect of the redis-tribution of the impurity of the second conductivity type and to leave the conductivity type and the effective impurity concen-tration of the adjacent region of the low impurity concentration in such conditions as desired.

Description

a) Field of the invention:
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it pertains to a method of manufacturing a semiconductor device including a first region of a high impurity concentration of a first conductivity type and being contiguous to a second region of a low impurity concentration of a second conductivity type which may be the same as or opposite to said first conductivity type.
b) Description of the prior art:
In high frequency, high power, or large-scale-inteyrated semiconductor devices, there is a need for forming regions of different impurity concentrations and different conductivity types in two-dimensional or three-dimensional structures with high accuracy. Particularly, in forming a region of a first conductivity type (e.g. n-type) of a very high impurity concentra-tion contiguous to a region of a second conductivity type (e.g.
p-type) of a low impurity concentration by selective diffusion, selective epitaxial growth, etc., redistribution (out-diffusion) of the first conductivity type impurity occurs through abnormal diffusion, surface diffusion, re-evaporat;on, back-etch, etc. due to the required high temperature treatment. Therefore, accurate formation of the repective regions becomes difficult. Further-more, redistribution of the impurity from the heavily doped region to the adjacent lightly doped region also occurs after the formation of the respective regions in any high temperature process such as oxidation, diffusion, epitaxial growth, or chemical vapor X, 2 deposition (CVD~ due to similar reasons. Then, not only the predetermined shapes are deformed but also adjacent but separate heavily doped regions may be short-circuited through a redis-tributed region of originally low impurity concentration, which leads to the destruction of -the designed device structure or characteristics.
An object of the present invention is to provide a method of manufacturing a semiconductor device including adjacent and clearly defined regions of high and low impurity concentra-tions, the method being capable of solving the conventional drawbacks.
Accordingly, the present invention provides a method of manufacturing a semiconductor device including at least a first region of a low impurity concentration of a first conductivity type primarily deterrnined by a first impurity and a second region of a high second impurity concentration of a second conductivity type primarily determined by a second impurity, located adjacent to each other in a semiconductor crystal, comprising steps of: doping, into said second reglon in addition to sa:id second impurit:~, an auxiliary impurity having a different atomic radius from that of the semiconductor èlement, the difference being opposite in sign to that of said second impurity, by such an amount that distortion of the semiconductor crystal due to the difference of the atomic radius of said second impurity and said semiconductor element is substantially compensated for; and in-troducing a third impurity of a conductivity type opposite to said second conductivity type in such region and with such a concentration that the redistribution of said second impurity into at least part of said first region is substantially compensated for.
More particularly, according to an aspect of the present invention, there is provided a semiconductor device ..
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including at least a first region of a low impurity concentration of a first conduetivity type primarily determined by a first impurity, and a second region of a high impurity concentration of a second conductivity type primarily determined by a seeond impurity, the first and second regions heing located adjacent to eaeh other in a semiconduetor erystal, wherein said second region ineludes, in addition to said seeond impurity, an auxiliary impurity having such a different atomie radius from that of the semieonduetor element that the differenee is opposite in sign to that of said second impurity, by sueh an amount that distortion of the semiconductor crystal due to the diff-erenee of the atomie radius of said second impurity and said semiconductor element is substantially eompensated for, and said first region ineludes at least a portion located adjaeent to said seeond region and ineluding said seeond impurity redistributed from said seeond region and a thi.rd impurity of a eonduetivity type opposite to said seeond conduetivity type with such a concentration that the redistributed second impurity is substantially compcnsated for.
The method is partieularly effeetive in the manufaeture of sueh semieonduetor deviees as ~he statie induetion semieonduetor deviees ineluding transistors, thyristors, integrated -3a-~ a logic, etc. proposed by the present inventor (Japanese Patent No.
968,336, issued August 1, 1979 and entitled "Field Ef~ect Tran-sistor", Japanese Patent No. 968,337, issued August 31, 1979 and entitled "Field Effect Transistor", and U.S. Patent No. 4,160,250 issued July 3, 1979, all in the name of the above applicants; and Japanese Patent Application No. 50-126111 "Static Induction Type Thyristor", Japanese Patent Application No. 50-126112 "Static In-duction Type Thyristor", Japanese Patent Application No. 50-126113 "Method of Manufacturiny Static Induction Type Thyristor",all pub-lished on April 21, 1977 in the names of the present applicants and Mitsubishi ~enki Kabushiki Kaisha).
The invention will now be described in more detail,by way of example only, with reference to the accompanying drawings, in which:-Figs. la and lb are cross-sections of a semiconductor chip showing how a heavily doped reoion is formed in a semi-conductor region of a low impurity concentration of the same of the opposite conductivity tvpe.
Figs. 2a and 2h are cross-sections of a semiconductor chip showing how abnormal diffusion occurs from aheavily doped region into a lightly doped region.

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Figs 3a to 3c are c~QsS-SectiQns of a semiconductor device showing how abnormal diffusion of an impurity from a heavily doped region can be compensated for according to an em-bodiment of the present invention.
Figs. 4a and ~b are cross-sections of a semiconductor chip showing how surface diffusion or redistribution occurs from a heavily doped region into a lightly doped region upon formation of an insulator film.
Figs. 5a to 5c are cross-~ections of a semiconductor chip showing how impurity redistribution occurs from a heavily doped re~ion into a lightly doped region upon formation of an overlie layer.
Figs. 6a to 6c are cross-sections of a semiconductor chip showing how impurity redistribution can be compensated for according to another embodiment of the present invention.
Figs. la and lb show the conventional method of forming a heavily doped region of a first conductivity type in a low impurity concentration crystal. In forming a heavily doped region, for example of p-type, in a low impurity concentration region of n- or p-type, a thin oxide or nitride film 11 for use as a diffusion mask is f~rmed on;the surface of the semiconductor chip 1 and an appropriate window or windows are formed therein by the usual photoetching or selective etching technique. In this case, windows have been formed on both sides of the diffusion mask 11. Then, a p-type inpurity is heavily doped into the ~ . -- 5 --semiconductor chip 1 by the diffusion from the impurity vapor or from the glass or doped oxide layer including the impurity to form heavily doped regions 2. An undiffused region 1', i.e.
a region of a low impurity concentration, remains under the diffusion mask 11 (see Fig. lb). Here, there is a possibility that the doped impurity atoms may diffuse along the surface, i.e. along the interface of the diffusion mask 11 and the semi-conductor chip 1, at an abnormally high speed (abnormal diffu-sion which may be caused by the interfacial strains). This is referred to also as a kind of redistribution in this specifi-cation. When a pair of heavily doped regions 2 are located near to each other as in this case, they may be connected through an abnormal diffusion layer 2' as shown in Fig. 2a. Such abnormal diffusion becomes more apparent as the impurity concentration in the heavily doped region 2 is higher, as the impurity concen-tration in the lightly doped or intrinsic region 1 is lower, and as the separation between adjacent pair of heavily doped regions

2 is shorter. Further, this undesirable diffusion also depends on the thickness cmd material of the diffusion mask 11, the diffusion temperature, the diffusion period, and so forth. For example, the hole concentration in the abnormal diffusion layer 2' reaches the order of 1012 to 1014 cm 3 when the impurity concentration in the low impurity concentration region 1 is about 5 x 101 to 2 x 1013 atoms/cm3, the impurity (e.g. boron B) surface concentration in the heavily doped p-type region 2 is about 10 atoms/cm3, the separation between the adjacent heavily doped regions 2 is 5 to 10 ~m, the diffusion temperature is 1200C, :

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the diffusion period is 30 minutes, and the diffusion mask 11 is formed of SiO2 and has a thickness of about 4000 A. Further-more, even if the adjacent heavily doped regions are not connected to each other yet as shown in Fig. 2b, the abnormal extension of the p-type layer 2' along the crystal surface lowers the dimensional accuracy and may increase the junction capacitance.
Thus, a desired carrier density distribution cannot be obtained, and hence a semiconductor element of desired electrical charac-teristics cannot be provided. The above probiem becomes serious in the selective diffusion for forming the junction type gate region of static induction type field effect transistors and thyristors, the emitter diffusion in bipolar transistors and the selective diffusion for forming source and drain of field effect transistors.
According to an embodiment of the present invention, the effects of the abnormally redistributed impurity atoms of a first conductivity type along the interface between a diffusion mask and a semiconductor body thereunder are removed by doping the diffusion mask with an impurity of a second conductivity type opposite to the first conductivity type of the heavily doped region so as to electronically compensate for the redistributed impurity atoms of the first conductivity type with those of the second conductivity type under the diffusion mask.
Figs. 3a to 3c illustrates the above embodiment of this invention. A diffusion mask 11 containing an n-type impurity is formed on an n -type semiconductor chip 1 (Fig. 3a). The diffusion mask 11 may be formed by oxidizing the surface of the semiconductor chip 1 at 1200C in an atmosphere formed of a mixture of about 1 cc/min of dry oxygen passed through PCQ3 refrigerated by dry ice in a main wet oxygen gas of 5 Q/min.
Alternatively, the diffusion mask 11 mav be a chemical-vapor-deposited silicon oxide (SiO2) or silicon nitride (Si3N4) film containing such an impurity formed by adding a small amount of a hydride or a chloride of an impurity element in a main mixture gas of SiH4 + 2 or SiH4 + NH3-Then, the diffusion mask 11 is selectively etched by the usual technique, and then a p-type impurity is diffused into the semiconductor chip 1 to form heavily doped p-type regions 2. ~pon this diffusion process, the n-type impurity atoms contained in the diffusion mask 11 out-diffuse into the semi-conductor chip 1 (1' in Fig. 3b) and compensate for the p-type impurity atoms diffused abnormally from the heavily doped regions 2. Appropriate selection of the doping level in the diffusion mask 11 enables the effective conductivity type and carrier concentration in the surface region 1' to be kept as before which would otherwise be altered. Further, the extension of the boundary of the doped regions along the surface as shown by the regions 2' in Fig. 2b can be effectively prevented by the above-stated method. Namely, the effective boundary of the doped regions 2 near the surface becomes as shown by the solid line A
in Fig. 3c. Thus, the dimensional accuracy can also be improved.
In the event when the regions of the high and low impurity concentrations are of the opposite conductivity type as in the above-stated instance, the preferred amount of the impurity to --.
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be doped in the diffusion mask is of such level that the result-ant impurity concentration in the semiconductor chip 1 will be the same or slightly higher than the impurity concentration redistributed from the heavily doped region. When the two regions are of the same conductivity type, the preferred doping level is such that the resultant impurity concentration in the semi-conductor chip is slightly lower or at most the same as the impurity concentration redistributed from the heavily doped region. Namely, the uncompensated-for residue impurity in the semiconductor chip l should be of the same conductivity type with that of the low concentration region.
It will be apparent that uniform distribution of the impurity in the diffusion mask is not necessary. A diffusion mask containing no impurity may be overcoated on a diffusion mask containing a desired level of impurity, or the impurity concentration may be graded. Various alternations or modifica-tions may be adopted according to the kind of impurity, concentra-tion of the redistributed impurity, and so forth. Although the above embodiment has been described on the instance of forming heavily doped regions by the selective diffusion, it will be apparent that the present invention can be adapted for the~case of selective epitaxial growth, and so forth. In the selective epitaxial growth, an impurity of a conductivity type opposite to that of the selective growth layer may be added in the mask (SiO2, Si3N4, etc.) for selective growth.
According to another embodiment of the present invention, a layer of such conductivity type which is opposite to that of _g_ the heavily doped region to be formed thereafter is preliminarily formed by diffusion or epitaxial growth in or on the semiconduc-tor surface before the formation of a diffusion mask. E~ere again, the impurity concentration in the preliminarily doped region is selected to be the same as or slightly higher than the expected impurity concentration to be redistributed from the heavily doped region when the regions of the high and the low impurity concen-trations are of the opposite conductivity type, and to be the same or slightly lower than the expected impurity concentration to be redistributed from the heavily doped region when the regions of the high and the low impurity concentrations are of the same conductivity type. This method attains similar effects for removing the problem of undesirable diffusion described in con-nection with Figs. 2a and 2b. A combined use of the foregoing methods is also very effective.
Next, another problem and a solution thereof will be described. Here, it is assumed that regions of a high and a low impurity concentration 2 and 1 are exposed on a semiconductor surface without any passivating film such as an oxide ~ilm (as shown in Fig. 4a). When an oxide or nitride film 11 is formed on the entire-surface of the semiconductor chip by CVD or thermal oxidation, the impurity atoms in the heavily doped regions 2 will diffuse outwardly and/or evaporate into the gas phase and will re-deposit on the surface due to the high temperature which is required in such process. As a result, the heavily doped regions 2 expand outwardly, and a thin layer 2' of a relatively low impurity concentration may be formed which has the same conduc-tivity type as that of the heavily doped region 2 as shown in :
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Fig. 4b. This naturally will cause short-circuiting of the heavily doped regions 2 located close to each other, and will prevent the achievement of the desired performance of the element.
This problem becomes serious in such instances when a third region or a diffusion mask is to be formed theron.
A solution to this problem is to lightly diffuse or deposit an impurity of the opposite conductivity type to that of the heavily doped regions 2 in the whole surface area of the semi-conductor chip 1 prior to the formation of a third layer or an oxide or nitride insulating film so as to compensate for the impurity atoms redistributed from the heavily doped regions 2.
An alternative method is to dope an impurity of the opposite conductivity type in the insulating film to be formed.
When a heavily doped region is to be formed in a lightly doped or a nearly intrinsic semiconductor chip of the same or opposite conductivity type, as in the case of forming an embedded gate of a static induction type semiconductor device, for example a heavily doped region 2 may be formed in a semiconductor crystal layer 1 of a low impurity concentration of the opposite conduc-tivity type as shown in Fig. lb, then the diffusion mask isremoved to expose both regions and an epitaxial layer 3 of a low impurity concentration of the opposite conductivity type is grown thereon (as shown in Fig. 5a). Here, the epitaxial growth is accomplished at a high temperature around 1100C to 1200C.
Therefore, first in the heating process before the epitaxial ; growth, the impurity atoms in the heavily doped region 2 may evaporate and re-deposit or diffuse along the surface to redis-tribute in the surface portion of the semiconductor layer 1.

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' Then, in the initial stage of the epitaxial growth, the impurity atoms ln the heavily doped region may also ~vaporate and re-deposit on the surface and diffuse along the surface, or may be released into the gas phase together with the semiconductor atoms by the backetch of HC~ and so forth which is produced by the growth reaction and then re-introduced into the growth layer 3, and so on. As a result, a designed structure as shown in Fig.
5a cannot be achieved, and such structures as shown in Figs. 5b and 5c will be brought about. Even in Fig. 5a, the heavily doped region 2 is subjected to some degree of extension into the region

3 of a low impurity concentration due to the thermal diffusion of impurity atoms during the heat treatment. In Fig. 5b, impurity atoms in the heavily doped region 2 redistribute in the neighbor-hood of the interface of the semiconductor chip 1 and the growth layer 3, and will form a region 2' of the same conductivity type as that of the heavily doped region 2. Thus, adjacent pair of heavily doped regions 2 may be short-circuited or the low impurity concentration layers 1 and 3 are cut off by the unintentionally formed region 2'. Furthermore, the heavily doped regions 2 unnecessarily wil:L extend into the low impurity concentration region 3 by the so-called auto-doping due to the back-etch and the like. Fig. 5c shows an intermediate state, in which the newly formed regions 2' produced by the redistribution of the impurity atoms from the heavily doped regions 2 have extended along the surface, but they do not yet touch each other. This phenomenon to fonm structures as shown in Fig. 5c, and more remarkably in Fig. 5b, becomes even more remarkable as the ': ' , . .

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impurity concentration in the semiconductor chip l and in the growth layer 3 is lower, as the growth temperature is higher, r3~ as the impurity concentration in the heavily doped tegion 2 is higher and as the width or the area of the low impurity concen-tration region l' defined by the heavily doped regions 2 is smaller. For example, a structure as shown in Fig. 5b which was brought about when the semiconductor crystal was silicon, the heavily doped region 2 had an impurity (boron B) concen-tration of about lO atoms/cm3 and a separation distance of 20 to 30 ~m, the n-type matrix region l had a low impurity concen-tration of about 1013 atoms/cm3, and an n-type growth layer 3 having an impurity concentration of about 1014 atoms/cm3 was formed thereon to a thickness of 20 ~m at 1200C by the epitaxial growth with the gas of SiCQ4 + H2. Here, the p-type redistributed region 2' had an impurity concentration of about 5 x 1014 to atoms/cm and a thickness of 2 to 3 llm, and the p-type heavily doped region 2 had extended into the growth layer by about 5 to 8 ~m. Even when the degree of this phenomenon is weak and a structure as shown in Fig. Sc is brought about, the junction area inevitably increases and the dimensions of the respective regions connot be accurately controlled. Then, the yield of products decreases especially for the devices for high frequency and high power uses and of high density integration.
For example, this phenomenon becomes a serious problem in the formation of an embedded region of a high impurity concentration in a static induction field effect semiconductor device and also in the formation of other embedded regions of a high impurity concentration in semiconductor devices.

A solution to this problem is illustrated in Figs. 6a and 6b. Namely, prior to the epitaxial growth, an impurity of a conductivity type opposite to that of the heavily doped region 2 is preliminarily deposited (adsorbed) on or diffused (driven)in the whole portions or in the selected portions of the semiconductor surface to compensate for the redistributed impurity atoms. In Fig. 6a, a layer 3' of such impurity material is deposited on the surface. When the impurity is of n-type, the deposition may be càrried out by means of a phosphor glass deposited in the atmosphere of PCQ3 + N2 + 2 at 500C to 800C
for about 20 minutes. This deposited glass layer is removed before the growth, with the impurity adsorbed on the semi-conductor surface. In Fig. 6b, a layer 3' is a diffused layer formed by the known technique, to have, for example, a surface impurity concentration of 1015 to 1017 atoms/cm3 and a depth below several microns. When the region 2 of the high impurity concentration and the epitaxial layer 3 of the low impurity concentration are of the same conductivity type, the surface concentration of the opposite conductivity type impurity may be lower and also the depth of the layer may be shallower. Impurity atoms redistributed from the heavily doped region in the epitaxial growth process are compensated for by the impurity atoms of the opposite conductivity type introduced from the deposit or the diffused layer to prevent the formation of a laterally spreading redistribution layer 2' and the excessive extension of the heavily doped region Z into the growth layer 3. The formation of the diffused layer 3' of the opposite conductivity type may be either before or after the formation of the heavily doped region 2.

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An alternative method is to divide the epitaxial layer in at least two layers 3' and 3 having different impurity concentrations, as shown in Fig. 6c. When the regions 2 of the high impurity concentration in the substrate and the epitaxially grown layer 3 of the low impurity concentration are of the opposite conductivity type, the impurity concentration in the first grown layer 3' closer to the heavily doped region 2 is arranged to be relatively high to effect the compensation of the redistributed impurity atoms. The second grown layer 3 is arranged to have a desired impurity concentration and thickness.
The impurity concentration and the thickness of the first grown layer 3' should be varied in accordance with the expected concentration of the redistributed impurity atoms which very with various parameters. Under the above-mentioned conditions, the concentration may be of the order of 5 x 1014 to 10 7 atoms/cm and the thickness may be 1 to 3 ~m. What is important C here is to dope an impurity in the first ~ 3~ in such a quantity which just or slightly will excessively compensate for the redistributed impurity. On the contrary, when the regions 2 of the high impurity concentration and the epitaxially grown layer 3 of the low impurity concentration are of the same conduc-tivity type, the first grown layer 3' is doped with an~impurity of the opposite conductivity type (relative to said same conduc-tivity type) up to a concentration slightly lower or at most equal to the concentration of the redistributed impurity. Indeed, im-purities of said same conductivity type may also be doped simultane-ously. This method has the advantage that the growth of the firstlayer - ~
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3' and the second layer 3 may be accomplished continuously in the same epitaxial growth process. A modified method is to gradually lower the impurity concentration of the opposite conductivity type from the interface to establish a graded distribution. Further, if necessary, the gas etch process in the heating step prior to the epitaxial growth may be performed in an atmosphere of the opposite conductivity type. This can improve the crystallization of the growth layer. Yet further, the first epitaxial layer 3' having a relatively high impurity concentration of the opposite conductivity type may be formed in the region 1' of the low impurity concentration prior to the formation of the heavily doped region 2. In accordance with the above-stated methods, the redistributed impurity atoms can be compensated for, and the formation of a redistributed layer can be effectively prevented. After the epitaxial growth, the heavily doped region 2 will have a smaller area of junction or boundary and a smaller extension into the epitaxial ]ayer as shown by the dotted line in Fig. 6c.
Another method is to dope an impurity o the opposite conductivity type to some extent in the heavily doped region.
The doped impurity of the opposite conductivity type is prefer-ably selected from those having a high vapor pressure, and hence a large degree of auto-doping (especially in case the regions of the high and the low impurity concentrations are of the opposite conductivity type). Furthermore, if the main impurity atom has a larger radius than the semiconductor atom, the added impurity atom of the opposite conductivity type preferably has . ,. , ,. ,. .: , : ~ :
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. -' 1~11146 a smaller radius, and vice versa. The manner of doping a secon-dary impurity may be selected from the simultaneous selective diffusion, double selective diffusion, and the simultaneous doped epitaxial growth in the formation of the heavily doped region, depending on the diffusion constants of the employed impurities. Here, the concentration of the secondary impurity of the opposite conductivity type should be lower than that of the main impurity. When such pair of impurities which have a larger and a lower atomic radius with respect to that of the semiconductor atom are employed, the distortion in the semi-conductor crystal due to the difference in the atomic radius can be cancelled to some extent even at high impurity concentra-tions. Thus, the generation of the lattice defects such as dislocations can be suppressed and the crystallization of the epitaxial layer formed thereon can be improved. Indeed, the main purpose of the secondary impurity is to compensate for the redistribution of the main impurity atoms by that of the secon-dary impurity atoms in the epitaxial growth process. For per-fectly compensating for the distortion o~ the semiconductor crystal in the heavily doped region, a third impurity may be additionally doped which is selected from a group of impurities of the same conductivity type into that of the main impuri.ty element and a group of atoms belonging to the same group of the as C periodic table i~3 that of the semiconductor element. For example, in case the se~iconductor is silicon and in case the heavil~ doped region is of the p-type, such combinations of impurities can be selected as B + Sb (+Ge or Sn), B ~ As (+Ge or Sn), . .
,. ', . ~ . ' B + P (+Ge or Sn), B + Ga + Sb, B + As (+Ga, AQ, TQ or In), and Ga + P (+B or C). When the heavily doped region is of the n-type, such combinations can be adopted as Sb + TQ (+C, P or B), As + B (+P or C), P + AQ (+Ga, Ge or Sn). Impurities mentioned in the parenthesis may be added for the lattice constant adjust-ment, whenever necessary. It will be apparent that the combina-tions of impurities are not limited to those mentioned above.
As described above, the compensation of the lattice distortion may be accomplished simultaneously with the com~ensation of the impurity redistribution, while reducing the effective impurity concentration in the epitaxial layer.
The above-mentoned embodiments have been described to help the understanding of the present invention but should not be read in any limitative way. m e conductivity types of the respective regions may be reversed, and the heavily doped region may also be formed by selective epitaxial growth, selective etching after a uniform epitaxial growth, ion implantation and so forth, as well as selective diffusion. The semiconductor element may also begermanium(Ge)~ V compounds, II - VI
compounds and the like, as well as silicon (Si).
As has been described above, according to the present invention, it should be noted that, when a heavily doped region is formed or to be formed in a semiconductor region of a low impurity concentration, redistrubution of the impurity from the heavily doped region is compensated for by the addition of a secondary impurity of the opposite conductivity type to enable high dimensional accuracy and a high yield of the product - - ~
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Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method of manufacturing a semiconductor device including at least a first region of a low impurity concentration of a first conductivity type primarily determined by a first impurity and a second region of a high second impurity concen-tration of a second conductivity type primarily determined by a second impurity, located adjacent to each other in a semi-conductor crystal, comprising steps of:
doping, into said second region in addition to said second impurity, an auxiliary impurity having a different atomic radius from that of the semiconductor element, the difference being opposite in sign to that of said second impurity, by such an amount that distortion of the semiconductor crystal due to the difference of the atomic radius of said second impurity and said semiconductor element is substantially compensated for; and introducing a third impurity of a conductivity type opposite to said second conductivity type in such region and with such a concentration that the redistribution of said second impurity into at least part of said first region is substantially compensated for.

2. A method of manufacturing a semiconductor device according to claim 1, wherein: said auxiliary impurity belongs to the same group of the periodic table as that of the semiconductor element.

3. A method of manufacturing a semiconductor device according to claim 2, wherein: said semiconductor element is silicon and said auxiliary impurity is one selected from the group consisting of germanium, tin and carbon.

4. A method of manufacturing a semiconductor device according to claim 1, wherein: said second region is formed in said first region.

5. A method of manufacturing a semiconductor device according to claim 4, wherein: said second region includes a pair of regions sandwiching said part of said first region.

6. A method of manufacturing a semiconductor device according to claim 4, wherein: said first region includes a first layer and a second layer formed thereon, said second region is formed in said first layer and said part of the first region includes part of said second layer in contact with said second region.

7. A semiconductor device including at least a first region of a low impurity concentration of a first conductivity type primarily determined by a first impurity, and a second region of a high impurity concentration of a second conductivity type primarily determined by a second impurity, the first and second regions being located adjacent to each other in a semiconductor crystal, wherein said second region includes, in addition to said second impurity, an auxiliary impurity having such a different atomic radius from that of the semiconductor element that the difference is opposite in sign to that of said second impurity, by such an amount that distortion of the semiconductor crystal due to the difference of the atomic radius of said second impurity and said semiconductor element is substantially compensated for, and said first region includes at least a portion located adjacent to said second region and including said second impurity redistributed from said second region and a third impurity of a conductivity type opposite to said second conductivity type with such a concentration that the redistributed second impurity is substantially compensated for.

8. A semiconductor device according to claim 7, wherein: said auxiliary impurity belongs to the same group of the periodic table as that of the semiconductor element.

9. A semiconductor device according to claim 8, wherein: said semiconductor element is silicon and said auxiliary impurity is one selected from the group consisting of germanium, tin and carbon.

10. A semiconductor device according to claim 7, wherein: said second region is formed in said first region.

11. A semiconductor device according to claim 10, wherein: said second region includes a pair of regions sandwiching said part of said first region.

12. A semiconductor device according to claim 10, wherein: said first region includes a first layer and a second layer formed thereon, said second region is formed in said first layer and said part of the first region includes part of said second layer in contact with said second region.