JPS58121684A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To readily form a P-N junction vertical channel semiconductor device having excellent stopping efficiency in simple steps. CONSTITUTION:Dish-shaped P type layers 23 of reverse conductive type are formed by diffusing impurity in the surface part of an N type silicon wafer 21 of semiconductor substrate, an oxidized film 31 of the prescribed thickness is formed on the overall surface of the wafer, phosphorus glass 32 containing the prescribed density phosphorus is covered on the oxidized film, is then heat treated as prescribed, thereby diffusing the phosphorus contained in phosphorus glass through the film 31 in the wafer and manufacturing a vertical N-channel semiconductor device. The conductive type of a peripheral end having low impurity density of P type layer is inverted into N type by controlling the density of the phosphorus contained in the phsophorus glass, the thickness of the oxidized film and the heat treating conditions, and since the density of the phosphorus diffused in the silicon wafer is as high as toward the surface of the wafer, the inverted region in the vicinity of the surface is large, and becomes smaller toward the deeper part, thereby forming the layer 23 of the shape which provides excellent stopping efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for improving the blocking efficiency of a semiconductor device having a Kpm channel.

Generally, in a channel-controlled semiconductor device, the voltage and current characteristics of the device are controlled by controlling the electric field formed at the PN junction of the semiconductor device. In such a semiconductor device, in the case of a power element with a large current capacity, the main current path is formed in a direction perpendicular to the surface, and so-called vertical channel devices have been devised. There is.

As an example of such a semiconductor device, the electrostatic conductive transistor shown in FIG. 1 is known.6 As shown in FIG. A dish-shaped P conductivity type gate layer 2 is formed on the surface. On the surface of the base layer 10 where the gate layer 2 is not formed,
A source electrode 4 is provided via an N0 layer 3 for resistive contact. A drain electrode 6 is provided on the other surface of the base layer 2 via a drain layer 5 of N0 conductivity type.

A gate electrode 7 is provided on the surface of the gate layer 2.

In the electrostatic induction disk transistor constructed as described above, by applying a reverse bias voltage to the gate electrode 7 and the source electrode 4, it is possible to prevent current from flowing between the source electrode 4 and the drain electrode 6. This is base layer 1
This is because the flow of carriers is prevented by a potential peak or depletion layer formed near the region 8 (i.e., Tejannel region) indicated by the dotted line in the figure due to the electric field effect caused by the voltage applied to the gate layer 2. be. It is known that the current blocking efficiency in this case is better as the width of the channel region in the horizontal direction is narrower.

However, in the case where the silicate layer 2 is formed by the conventional diffusion method, the impurities are also diffused in the horizontal direction, so the cross section of the PN junction surface 9 between the base layer 1 and the gate layer 2 is dish-shaped. Become. Therefore, the width of the channel region becomes wider than the width of the source electrode 4 region, resulting in a disadvantage that the blocking efficiency deteriorates.

In order to overcome the above-mentioned drawbacks, a method has conventionally been devised in which the side surfaces of the PN junction surface are formed vertically by epitaxial growth to narrow the width of the channel region. A conventional example thereof is shown in FIGS. 2 and 3.

In FIG. 2, first, a P-conductivity type gate layer 12A is formed on the surface of an N-conductivity type base layer 11A by diffusion, and then an N-conductivity type base layer 11B is epitaxially grown on that surface. , furthermore, a gate layer 12 of P conductivity type.
B is formed by diffusion. According to this method, the shape of the gate layer 12 formed in the space layer 11 is improved, so that the width of the channel region can be narrowed. In addition, in FIG. 3, a groove with a desired rectangular cross section is formed on the surface of the base layer 13 made of N-conductivity type silicon by anisotropic etching, and the groove is filled by epitaxial growth. A gate layer 14 of P conductivity type silicon is formed therein. therefore,
According to this method, the width of the channel region can be controlled to an arbitrary width.

However, by the epitaxial growth method described above,
All of the methods of forming the width of the channel region narrowly require additional steps such as epitaxial growth and etching, which have the drawbacks of increasing manufacturing costs and decreasing yield.

An object of the present invention is to provide a method for manufacturing a PN junction semiconductor device having a vertical channel, which can easily form a PN junction shaped semiconductor device with excellent blocking efficiency through simple steps. .

The present invention provides a method for manufacturing a vertical channel PN junction type semiconductor device including a step of forming an opposite conductivity type layer having a dish-shaped cross section on the surface of a conductivity type semiconductor substrate by impurity diffusion. The present invention attempts to manufacture a PNiNi pillow-shaped semiconductor device with excellent blocking efficiency by adding a step of selectively doping impurities to the edge region and inverting the conductivity type of the region.

That is, the present invention is based on the fact that the peripheral edge region of the dish-shaped opposite conductivity type layer formed by normal diffusion is a region with a low impurity concentration because it is produced by lateral diffusion. This was done in consideration of the situation. tJ+, the conductivity type of the peripheral edge region with low impurity concentration can be selectively reversed by appropriate doping conditions, since it does not affect the region with high impurity concentration in the dish-shaped layer of the opposite conductivity type. This is what we are trying to do.

Hereinafter, the present invention will be explained based on examples.

A method for manufacturing a vertical N-channel semiconductor device as an embodiment of the present invention will be described.

A dish-shaped P-type layer of the opposite conductivity type is formed on the surface of an N-type silicon wafer, which is a semiconductor substrate, by impurity diffusion.
An oxide film of a predetermined thickness is provided on the entire surface of this wafer, and after a phosphorus glass containing a predetermined low concentration of phosphorus is deposited on the oxide film, a predetermined heat treatment is performed to allow phosphorus to pass through the oxide film. A vertical N-channel semiconductor device is manufactured by diffusing phosphorus contained in the glass into the wafer.

Therefore, according to the manufacturing method of this example, by controlling the concentration of phosphorus contained in the phosphorus glass, the thickness of the oxide film, and the heat treatment conditions to appropriate values, it is possible to form a dish-shaped product for 7'h.
The region with high impurity concentration of the P-type layer is not affected, and the conductivity type of the peripheral edge region with low impurity concentration of the P-type layer is inverted, and the N
Moreover, since the concentration of phosphorus diffused into the silicon wafer is higher the closer it is to the surface, the inversion region is large near the surface and becomes smaller as it goes deeper, as shown in Figure 4. As shown, a P-type layer 23 can be formed with a shape that provides very good blocking efficiency.

Furthermore, according to this example, since the phosphorus in the phosphorus glass is diffused into the wafer through the oxide film, the controllability of the low concentration doping amount is excellent, and manufacturing methods such as epitaxial growth and anisotropic etching can be used. PN junctions having a desired shape can be manufactured extremely easily, and the manufacturing cost can be greatly reduced, since only thermal diffusion is required.

Although the oxide film is used to control the doping amount as described above, it goes without saying that the oxide film is not required if the phosphorus concentration of the phosphorus glass and the heat treatment conditions are appropriate.

Further, the present invention will be explained in detail based on illustrated embodiments.

Figures 5-5 show the steps of an embodiment in which the present invention is applied to a static induction diode.

As shown in FIG. 5, an N-type layer 22 having a resistivity of about 40 Ω and a thickness of about 13 μm is epitaxially grown on a N0 conductivity type substrate 21 using an oxide film as a mask. , Boron was selectively deposited using BN as a diffusion source by heat treatment for 90 minutes at a temperature of 950C, and then drive-in diffusion was performed at a temperature of 1150G for about 300 minutes, as shown in (■) in the same figure. , a P-type layer 23 with a junction depth of about 8 μm is formed. At this time,
There is no problem even if the P-type layers 23 are connected to each other, as shown in FIG.
A phosphorus glass film 32 having a thickness of about 0.2 μm and a phosphorus glass film 32 having a phosphorus concentration of about 6% is deposited to a thickness of about 0.35 μm using the CVD method.
Heat treatment is performed for 00 minutes. As a result, the P-type layer 23 on the surface of the sea urchin, except for the area approximately corresponding to the diffusion window of the mask during the horn diffusion, is inverted to the N-type layer 23, as shown in FIG. A P-type layer 23 is formed as shown in FIG. next,
As shown in FIG. .

The blocking characteristics of this stiff PN junction element vary depending on the width of the channel, as described above.

Therefore, the channel width in FIG.
Change the channel width in Figure (C) to W as shown.

, and both W and W are formed to have a thickness of about 2 μm,
A comparative experiment of blocking properties was conducted. As a result, the forward voltage drop in all cases was 0.75 V, whereas in terms of reverse characteristics, the conventional example with the shape (■) in the same figure had a reverse voltage drop of several mA to several mA at a reverse voltage of several V. A leakage current of several tens of mA flowed and there was almost no stylus force, but in this example, the shape shown in the figure 0 has a leakage current of 1μ for a reverse voltage of 100V.
It had a rating of A or lower and had excellent pressure resistance and was round.

Therefore, according to this example, in addition to the effects of the previous example, an electrostatic induction board diode with excellent voltage resistance and improved blocking characteristics can be realized by a simple manufacturing method. effective.

6 and 7 respectively show other embodiments to which the present invention is applied. In addition, in the drawings, parts with the same reference numerals as those in the embodiment illustrated in FIG. 5 are made of the same materials and have the same functions.

FIG. 6 shows an example applied to a bipolar electrostatic induction board diode having a P-type layer 24 with a shallow junction depth, and FIG. 7 shows the conventional example shown in FIG. An example of application to a static induction transistor similar to that shown is shown.

In the embodiments shown in FIGS. 6 and 7, the same effects as in the above embodiments could be obtained.

In each of the above-mentioned embodiments, a PN junction N-channel semiconductor device in which a P-type layer is formed on an N-type semiconductor substrate has been described, but in order to form a similar P-channel semiconductor device, It is only necessary to change the conductivity type of the impurity source to be doped. For example, by using boron glass instead of phosphorus glass, and appropriately selecting doping amount control conditions such as boron concentration, oxide film thickness, and heat treatment conditions, it is possible to produce the same product. can do.

In addition, round impurity doping to invert the conductivity type of a desired region is not limited to methods such as thermal diffusion, but can also be performed by ion implantation using an appropriate mask or controlling the implantation amount as described above. A PN junction semiconductor device having a shape similar to that of the embodiment can be realized.

Furthermore, the present invention is not limited to the type of semiconductor device shown in the above embodiments, but can be applied to any type of semiconductor device that obtains control characteristics through a so-called channel.

As described above, according to the present invention, a vertical channel semiconductor device in the form of a PN junction with excellent blocking efficiency can be easily formed through simple steps, thereby significantly reducing the manufacturing cost. In addition, it has the effect of improving yield.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional electrostatic induction transistor, and Figures 2 and 3 are nine pages each improved by the conventional method.
A cross-sectional view of the N-junction shape, FIG. 4 is a PN of an embodiment of the present invention.
Cross-sectional views of the junction shape, Figures 5-5F are cross-sectional views of each manufacturing process of nine embodiments of the electrostatic conduction type diode to which the present invention is applied, and Figure 6 is a cross-sectional view of the nine embodiments to which the present invention is applied. FIG. 7 is a cross-sectional view of a bipolar electrostatic induction diode according to an embodiment of the present invention, and FIG. 7 is a cross-sectional view of a static induction type transistor according to another embodiment of the present invention. 21...N0 conductivity type substrate, 22...N type layer, 23.
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Claims (1)

[Claims] 1. - A method for manufacturing a vertical channel PN junction type semiconductor device including a step of forming an opposite conductivity type layer having a dish-shaped cross section on a surface portion of a conductivity type semiconductor substrate by impurity diffusion. 1. A method for manufacturing a semiconductor device, comprising the step of selectively doping an impurity into a peripheral edge region of a layer of an opposite conductivity type to invert the conductivity type of the region.