CA1108786A - Integrated display device - Google Patents
Integrated display deviceInfo
- Publication number
- CA1108786A CA1108786A CA312,755A CA312755A CA1108786A CA 1108786 A CA1108786 A CA 1108786A CA 312755 A CA312755 A CA 312755A CA 1108786 A CA1108786 A CA 1108786A
- Authority
- CA
- Canada
- Prior art keywords
- substrate
- integrated circuit
- cover
- anodes
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 39
- 239000011521 glass Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 239000007787 solid Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 241000518994 Conta Species 0.000 description 1
- 241000282339 Mustela Species 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 101150115956 slc25a26 gene Proteins 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J31/00—Cathode ray tubes; Electron beam tubes
- H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
- H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
- H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
- H01J31/15—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen with ray or beam selectively directed to luminescent anode segments
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G9/00—Visual time or date indication means
- G04G9/08—Visual time or date indication means by building-up characters using a combination of indicating elements, e.g. by using multiplexing techniques
- G04G9/10—Visual time or date indication means by building-up characters using a combination of indicating elements, e.g. by using multiplexing techniques by controlling light sources, e.g. electroluminescent diodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
- G09G3/06—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
Abstract
Abstract of the Disclosure A high vacuum fluorescent display device contains solid state drive circuitry within a unitary evacuated container.
Description
7~
~ gro~ing cl~ss of disp]ay devices employs pllosphor coatecl segmented anodes excited by low energy thermoelectrons emitted by a dull red filament controlled by a control grid either interposed therebetween or on the outside of the filament. These devices are enclosed in enclosures in which a hard vacuum is drawn. A
transparent window in the enclosure enables viewing of the excited anode segments usually through the control grid. The segmented anodes may be in any configuration such as 7-segment numeric or multiple-segment alphabetic as illustrated in U.S. Patent 3,986,760, issued October 19~ 1976 to Kishino, or they may be in a sequentially illuminated linear indicator such as disclosed in applicant's U.S. Patent 4,100,455, issued July 11, 197~.
The prior art and the present invention will be described in conjunction with the accompanying drawings, in which:
Fig. 1 shows one example of the prior art employing a 7-segment alphanumeric display controlled by an integrated circuit ~ ig. 2 shows another example of the prior art employing a linear scale indicator.
Fig. 3 shows one embodiment of the present ~`
invention.
Fig. 4 shows another embodiment of the present invention.
Vacuum fluorescent display devices are being widely chosen for display purposes because of their brightness, reliability, color and compatibility for drive by solid state descrete or integrated circuits. In the typical application, the value to be displayed is an analog or B ~
mb/, J - 1 -I`
t7~
digital signal which must then be processed to yield one binary signal per anode segment to command each anode segment to be either illuminated or extinguished. More sophisticated sytems can~ in addition, incrementally control the brightness o the anode segments between full oEf and ull on.
Fig. 1 shows the method used in the prior art to perform the simple ~unction of driving a 7-segment numeric display lO ~rom a 4-Iine binary-coded-decimal input 12.
An evacuated enclosure 14 of the display 10 is mounted on a suitable support such as a circuit board 16. An integrated circuit 18 in its evacuated enclosure 20 is also mounted on the circuit board 16. One signal line 22 per segment,~a total o 7 lines in the illustrated example, is connected between the evacuated enclosure 20 and the evacuated enclosure 14 to connect the 7 binary signals ~; ~ between them. Thus, exclusive of DC power inpues7 the integrated circuit evacuated enclosure 20 has 11 hermetically sealed leads 24 piercing it and the dispIay evacuated enclosare 14 has 7 hermetically sealed leads 24 piercing ~ -it. Furthermore, the leads 24 are connected to the signal lines 22 by interconnections 26 at each of the two ends of each signal line 22. Thus there are 14 interconnections ::
26 for the 7 signal lines 22. In the electronics industry, faulty interconnections 22 account for a large part o~
both assembly labor and device failures. An even more ::: : : :
: :
~2-:
- : . .
~ ;
~ Jf~ ~
exaggerated example of interconnect requirements is to be :~ound in the linear scale indicator of the referenced U.S. patent application. A 40-segmenk linear scale indicator as illustrated at 28 in Fig. 2 requires 40 signal lines 22, 80 hermetic seals and 80 interconnections to con~rol the 40 segments from a driver inte~rated circuit 30. In a typical application, only a single analog input signal line 32 is required into the integrated circuit 30. The integrated circuit 30 generates a contiguous set of binary.ones on the signal lines 2~ to the linear scale indicator 28 in proportion to the amplitude of the analog signal on the signal line 32.
. Summary of the Invention The applicant has discovered that many of the mechanical, chemical and sealing operations incident to manufacturing a vacuum fluorescent di9play and an integrated circuit are t~e same. For.example, both : devices require cleaning, metallizing, application of :photoresist, etching and removal of photoresist. In ~: .
addition, the working environment of both devices is preferably a hard vacuum. The bonding of the~integrated circuit. t~ the substrat is per~ormecl using a low : temperature glass preform which fuses at a~low:temperature of~approximately 525C. This temperature is low enough to have negligible effect on the:integrated circuit~
:
; Furthermore, the cover of the enclosure~is bonded to :
~,.,~ ::
: ~ -3-.
~ L~ J ~ ~
the ~u~stra~ at tl-e samc temp~rature. ConsequeQtly7 the app]icnnt con~emp]ates perforrning the e]ectrLcal interconnections between electrical leads formed on the substrate and integrated cLrcuit, then placing the cover in place and bonding the lntegrated circuit to the substrate in the same heating operation used to seal the perimeter of the cover to the substrate.
The present invention is used in a method of producing an integrated display device having a substrate and a cover bonded thereto to form a hermetically sealed enclosure having an integrated circuit mounted therein.
This method includes the steps of forming a plurality of anodes on the substrate~ forming electric leads on the substrate, with the electric leads interconnecting with the anodes. The anodes have at least a part thereof coated with a phosphor. Further steps are affixing at least one control grid and one filament to the substrate, mounting the integrated circuit on the substrate and interconnecting the integrated circuit with the electric leads. The invention relates to the improvement comprising the steps of., (a) positioning a low-temperature glass preform on the substrate between the integrated circuit and the substrate prior to inter-connection of the integrated circuit with the electrical leads; (b) placing the cover on the substrate for covering the anodes, control grid, filament and integrated circuit; and (c3 heating the cover and substrate for heat bonding the cover to the substrate, the cover and substrate forming thereby a single sealed enclosure, the low-temperature glass preform fusing during the operation of heating the cover and substrate whereby the integrated circuit is bonded to the substrate as the cover is heat bonded to the substrate.
mb/~ 4 , ., "
: ~ , 7~i ThC! app l :Lc~l~t dlscLoses a (levLce in whlch the integra~ecl c;rc~sit and vacllum fluorescent dlsplay are botll fabricate(l on a single subs~rate wlth dlrect interconnections between devices. Both devices are sealed within a single evacuated envelope. Thus, 14 of the hermetic seals for leads 24 shown in Fig. 1 and the 14 interconnects 26 are eliminated. In Fig. 2, 80 leads and interconnects are eliminated leaving only the analog signal line 32 piercing the vacuum enclosure.
In all cases, certain dc connections, such as ~ilament voltages must still be supplied through the vacuu envelope.
In one application contemplated by the applicant, a complete digital clock, including a plurality of numeric display devices and the timing and control electronics are all fabricated on a single substrate, interconnected and enclosed in a single evacuated enclosure. Gettering may be employed to improve the vacuum.
The very great reduction in assembly labor as well as the improvement in reliability, stemming from the sharply reduced number of hermetic seals and interconnects, gives the present invention significantly improved practicability.
Detailed DescriPtion of the Preferred Embodiment ... . ...... . ..... _ ~ . , Referring to Fig. 3, there is shown generally at 34 an integrated display according to the present invention. A substrate 36, suitably of glass or ceramic has a display device 37 applied thereto consisting of a conductive pattern of segmented anodes 38 and integral interconnect lines 40 formed by conventional methods well known in the art. At least part of the anodes 38 are covered by electron-excitable phosphor material.
mb/~ _ 5 _ An :Lnte~rrlt(LI c:Lrcu:Lt :].~3 i.s nff:Lxed ~:o ~-he same substrnte 36 conta:Ln:lllg ~:hc di.sp:Lny device 37 and :Lnterconnect lines ~0 w:i.th:Ln the same evacuated enclosure 42. The evacuated enclosure i9 formed by a concave cover plate being placed over the substrate 36 and sealed thereto about their abutting perimeters.
In this way, only internal connections between the display device 37 and the lntegrated mb/l" - 5a -, ~ J~t~ ~
circui~ 18 are required. ~3 iS readily e-vident, the device in Fig. 3 eliminated 14 interconnects and 14 hermetic æeals as compared to the prior art device shown in Fig, 1.
Even more dramatic reductions in interconnects and hermetic seals occur when a prior art deyice o~ the type shown in Fig. 2 is integrated into a single evacuated en-closure. Eighty of 81 hermetic seals and 80 interconnects are eliminated in the 40-segment device and replaced by high-reliability machine-made interconnect lines which are sealed and protected within the slngle evacuated enclosure.
Certain types of devices made according to the present invention require no signal inputs or outputs except for power and alignment signals. A complete digital clock is shown at 44 in Fig. 4. A digital clock integrated circui~ 46 is affixed to the same substrate 48 as the four-digit display elements 50 and the hours/minutes delimiter 52. According to the operation of vacuum fIuorescent dîsplay devices disclosed in the references, a control grid 54 over each display element 50 de~ermines whether it is illuminated or extinguished.
Each control grid 54 i6 connected to the digital clock integrated circuit 46 by a control line 58 at least partly integrally formed on the substrate 48 during the p-reparatlon o~ the d~s-` play elements 50. The corresponding anodes 56 from each dis-play element 50 are connected in parallel to outputs of the .
;~ ~ digital clock integrated circuit 46 by signal lines 60 at ~ ~ ' ' , .
leas-t partly in~egrally forrned on the substrate 48 during the preparation of tlle di.splav elements 50. It will be evident to one skilled in the ar-t, that the control lines 58 and signal lines 60 may be on the ront or rear face of the substrate or they may be sandwiched between one or more layers of insulating material. Furthermore, some parts o the control lines 58 and signal lines 60 may be on one sur-ace and other parts on other surfaces. Interconnections between display elements 50, integrated circuit 46 and parts o the control and signal lines 58, 60 may be direct or through holes in the insula.ting layers or by other means known or to become known in the' a.rt. The displa,y elements 50, the integrated circuit 46 and at least part of the con-trol and signal lines 58, 60 are enclosed within a single evacuated enclosure 62.
The digital clock 44 illuminates each o the display elements 50 i~ turn at a high rate to create the visual impression that all display elements 50 are continuously illuminated with their selected numerals~ For example, the control lines 58 may ena.ble the illumination of one display element 50 at a time at the rate o 400 per second. Thus each o the ~ display elements 50 is illuminated 100 times per second. At the time a particular,display element 50 is enabled by its control line 58, all signaL lines 60 assume the digital code required to display the.decimal digit required or that position. A8 the next display element 50 is enabled by its control line 58, the digital code on ali signal lines 60 changes to display the decimal digit required for that position.
In all devices discussed, dc power input leads are required through hermetic seals. These have been omitted for simplicity.
It will be understood that the claims are intended to cover all changes and modiications of the preferred embodi-ments o~ the invention, herein chosen for the purpose o illustration which do not constitute departures from the spirit and scope of the invention.
:
,
~ gro~ing cl~ss of disp]ay devices employs pllosphor coatecl segmented anodes excited by low energy thermoelectrons emitted by a dull red filament controlled by a control grid either interposed therebetween or on the outside of the filament. These devices are enclosed in enclosures in which a hard vacuum is drawn. A
transparent window in the enclosure enables viewing of the excited anode segments usually through the control grid. The segmented anodes may be in any configuration such as 7-segment numeric or multiple-segment alphabetic as illustrated in U.S. Patent 3,986,760, issued October 19~ 1976 to Kishino, or they may be in a sequentially illuminated linear indicator such as disclosed in applicant's U.S. Patent 4,100,455, issued July 11, 197~.
The prior art and the present invention will be described in conjunction with the accompanying drawings, in which:
Fig. 1 shows one example of the prior art employing a 7-segment alphanumeric display controlled by an integrated circuit ~ ig. 2 shows another example of the prior art employing a linear scale indicator.
Fig. 3 shows one embodiment of the present ~`
invention.
Fig. 4 shows another embodiment of the present invention.
Vacuum fluorescent display devices are being widely chosen for display purposes because of their brightness, reliability, color and compatibility for drive by solid state descrete or integrated circuits. In the typical application, the value to be displayed is an analog or B ~
mb/, J - 1 -I`
t7~
digital signal which must then be processed to yield one binary signal per anode segment to command each anode segment to be either illuminated or extinguished. More sophisticated sytems can~ in addition, incrementally control the brightness o the anode segments between full oEf and ull on.
Fig. 1 shows the method used in the prior art to perform the simple ~unction of driving a 7-segment numeric display lO ~rom a 4-Iine binary-coded-decimal input 12.
An evacuated enclosure 14 of the display 10 is mounted on a suitable support such as a circuit board 16. An integrated circuit 18 in its evacuated enclosure 20 is also mounted on the circuit board 16. One signal line 22 per segment,~a total o 7 lines in the illustrated example, is connected between the evacuated enclosure 20 and the evacuated enclosure 14 to connect the 7 binary signals ~; ~ between them. Thus, exclusive of DC power inpues7 the integrated circuit evacuated enclosure 20 has 11 hermetically sealed leads 24 piercing it and the dispIay evacuated enclosare 14 has 7 hermetically sealed leads 24 piercing ~ -it. Furthermore, the leads 24 are connected to the signal lines 22 by interconnections 26 at each of the two ends of each signal line 22. Thus there are 14 interconnections ::
26 for the 7 signal lines 22. In the electronics industry, faulty interconnections 22 account for a large part o~
both assembly labor and device failures. An even more ::: : : :
: :
~2-:
- : . .
~ ;
~ Jf~ ~
exaggerated example of interconnect requirements is to be :~ound in the linear scale indicator of the referenced U.S. patent application. A 40-segmenk linear scale indicator as illustrated at 28 in Fig. 2 requires 40 signal lines 22, 80 hermetic seals and 80 interconnections to con~rol the 40 segments from a driver inte~rated circuit 30. In a typical application, only a single analog input signal line 32 is required into the integrated circuit 30. The integrated circuit 30 generates a contiguous set of binary.ones on the signal lines 2~ to the linear scale indicator 28 in proportion to the amplitude of the analog signal on the signal line 32.
. Summary of the Invention The applicant has discovered that many of the mechanical, chemical and sealing operations incident to manufacturing a vacuum fluorescent di9play and an integrated circuit are t~e same. For.example, both : devices require cleaning, metallizing, application of :photoresist, etching and removal of photoresist. In ~: .
addition, the working environment of both devices is preferably a hard vacuum. The bonding of the~integrated circuit. t~ the substrat is per~ormecl using a low : temperature glass preform which fuses at a~low:temperature of~approximately 525C. This temperature is low enough to have negligible effect on the:integrated circuit~
:
; Furthermore, the cover of the enclosure~is bonded to :
~,.,~ ::
: ~ -3-.
~ L~ J ~ ~
the ~u~stra~ at tl-e samc temp~rature. ConsequeQtly7 the app]icnnt con~emp]ates perforrning the e]ectrLcal interconnections between electrical leads formed on the substrate and integrated cLrcuit, then placing the cover in place and bonding the lntegrated circuit to the substrate in the same heating operation used to seal the perimeter of the cover to the substrate.
The present invention is used in a method of producing an integrated display device having a substrate and a cover bonded thereto to form a hermetically sealed enclosure having an integrated circuit mounted therein.
This method includes the steps of forming a plurality of anodes on the substrate~ forming electric leads on the substrate, with the electric leads interconnecting with the anodes. The anodes have at least a part thereof coated with a phosphor. Further steps are affixing at least one control grid and one filament to the substrate, mounting the integrated circuit on the substrate and interconnecting the integrated circuit with the electric leads. The invention relates to the improvement comprising the steps of., (a) positioning a low-temperature glass preform on the substrate between the integrated circuit and the substrate prior to inter-connection of the integrated circuit with the electrical leads; (b) placing the cover on the substrate for covering the anodes, control grid, filament and integrated circuit; and (c3 heating the cover and substrate for heat bonding the cover to the substrate, the cover and substrate forming thereby a single sealed enclosure, the low-temperature glass preform fusing during the operation of heating the cover and substrate whereby the integrated circuit is bonded to the substrate as the cover is heat bonded to the substrate.
mb/~ 4 , ., "
: ~ , 7~i ThC! app l :Lc~l~t dlscLoses a (levLce in whlch the integra~ecl c;rc~sit and vacllum fluorescent dlsplay are botll fabricate(l on a single subs~rate wlth dlrect interconnections between devices. Both devices are sealed within a single evacuated envelope. Thus, 14 of the hermetic seals for leads 24 shown in Fig. 1 and the 14 interconnects 26 are eliminated. In Fig. 2, 80 leads and interconnects are eliminated leaving only the analog signal line 32 piercing the vacuum enclosure.
In all cases, certain dc connections, such as ~ilament voltages must still be supplied through the vacuu envelope.
In one application contemplated by the applicant, a complete digital clock, including a plurality of numeric display devices and the timing and control electronics are all fabricated on a single substrate, interconnected and enclosed in a single evacuated enclosure. Gettering may be employed to improve the vacuum.
The very great reduction in assembly labor as well as the improvement in reliability, stemming from the sharply reduced number of hermetic seals and interconnects, gives the present invention significantly improved practicability.
Detailed DescriPtion of the Preferred Embodiment ... . ...... . ..... _ ~ . , Referring to Fig. 3, there is shown generally at 34 an integrated display according to the present invention. A substrate 36, suitably of glass or ceramic has a display device 37 applied thereto consisting of a conductive pattern of segmented anodes 38 and integral interconnect lines 40 formed by conventional methods well known in the art. At least part of the anodes 38 are covered by electron-excitable phosphor material.
mb/~ _ 5 _ An :Lnte~rrlt(LI c:Lrcu:Lt :].~3 i.s nff:Lxed ~:o ~-he same substrnte 36 conta:Ln:lllg ~:hc di.sp:Lny device 37 and :Lnterconnect lines ~0 w:i.th:Ln the same evacuated enclosure 42. The evacuated enclosure i9 formed by a concave cover plate being placed over the substrate 36 and sealed thereto about their abutting perimeters.
In this way, only internal connections between the display device 37 and the lntegrated mb/l" - 5a -, ~ J~t~ ~
circui~ 18 are required. ~3 iS readily e-vident, the device in Fig. 3 eliminated 14 interconnects and 14 hermetic æeals as compared to the prior art device shown in Fig, 1.
Even more dramatic reductions in interconnects and hermetic seals occur when a prior art deyice o~ the type shown in Fig. 2 is integrated into a single evacuated en-closure. Eighty of 81 hermetic seals and 80 interconnects are eliminated in the 40-segment device and replaced by high-reliability machine-made interconnect lines which are sealed and protected within the slngle evacuated enclosure.
Certain types of devices made according to the present invention require no signal inputs or outputs except for power and alignment signals. A complete digital clock is shown at 44 in Fig. 4. A digital clock integrated circui~ 46 is affixed to the same substrate 48 as the four-digit display elements 50 and the hours/minutes delimiter 52. According to the operation of vacuum fIuorescent dîsplay devices disclosed in the references, a control grid 54 over each display element 50 de~ermines whether it is illuminated or extinguished.
Each control grid 54 i6 connected to the digital clock integrated circuit 46 by a control line 58 at least partly integrally formed on the substrate 48 during the p-reparatlon o~ the d~s-` play elements 50. The corresponding anodes 56 from each dis-play element 50 are connected in parallel to outputs of the .
;~ ~ digital clock integrated circuit 46 by signal lines 60 at ~ ~ ' ' , .
leas-t partly in~egrally forrned on the substrate 48 during the preparation of tlle di.splav elements 50. It will be evident to one skilled in the ar-t, that the control lines 58 and signal lines 60 may be on the ront or rear face of the substrate or they may be sandwiched between one or more layers of insulating material. Furthermore, some parts o the control lines 58 and signal lines 60 may be on one sur-ace and other parts on other surfaces. Interconnections between display elements 50, integrated circuit 46 and parts o the control and signal lines 58, 60 may be direct or through holes in the insula.ting layers or by other means known or to become known in the' a.rt. The displa,y elements 50, the integrated circuit 46 and at least part of the con-trol and signal lines 58, 60 are enclosed within a single evacuated enclosure 62.
The digital clock 44 illuminates each o the display elements 50 i~ turn at a high rate to create the visual impression that all display elements 50 are continuously illuminated with their selected numerals~ For example, the control lines 58 may ena.ble the illumination of one display element 50 at a time at the rate o 400 per second. Thus each o the ~ display elements 50 is illuminated 100 times per second. At the time a particular,display element 50 is enabled by its control line 58, all signaL lines 60 assume the digital code required to display the.decimal digit required or that position. A8 the next display element 50 is enabled by its control line 58, the digital code on ali signal lines 60 changes to display the decimal digit required for that position.
In all devices discussed, dc power input leads are required through hermetic seals. These have been omitted for simplicity.
It will be understood that the claims are intended to cover all changes and modiications of the preferred embodi-ments o~ the invention, herein chosen for the purpose o illustration which do not constitute departures from the spirit and scope of the invention.
:
,
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a method of producing an integrated display device having a substrate and a cover bonded thereto to form a hermetically sealed enclosure having an integrated circuit mounted therein, which method includes the steps of forming a plurality of anodes on said substrate, forming electric leads on said substrate, said electric leads interconnecting with said anodes, said anodes having at least a part thereof coated with a phosphor, affixing at least one control grid and one filament to said substrate, mounting said integrated circuit on said substrate and interconnecting said integrated circuit with said electric leads, the improvement comprising the steps of:
(a) positioning a low-temperature glass preform on said substrate between said integrated circuit and said substrate prior to inter-connection of said integrated circuit with said electrical leads;
(b) placing said cover on said substrate for covering said anodes, control grid, filament and integrated circuit; and (c) heating said cover and substrate for heat bonding said cover to said substrate, said cover and substrate forming thereby a single sealed enclosure, said low-temperature glass preform fusing during the operation of heating said cover and substrate whereby said integrated circuit is bonded to said substrate as said cover is heat bonded to said substrate.
(a) positioning a low-temperature glass preform on said substrate between said integrated circuit and said substrate prior to inter-connection of said integrated circuit with said electrical leads;
(b) placing said cover on said substrate for covering said anodes, control grid, filament and integrated circuit; and (c) heating said cover and substrate for heat bonding said cover to said substrate, said cover and substrate forming thereby a single sealed enclosure, said low-temperature glass preform fusing during the operation of heating said cover and substrate whereby said integrated circuit is bonded to said substrate as said cover is heat bonded to said substrate.
2. The method of claim 1 and wherein the temperature for heating of said cover and said substrate is about 525°.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US85091977A | 1977-11-14 | 1977-11-14 | |
| US850,919 | 1977-11-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1108786A true CA1108786A (en) | 1981-09-08 |
Family
ID=25309447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA312,755A Expired CA1108786A (en) | 1977-11-14 | 1978-10-05 | Integrated display device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5496357A (en) |
| CA (1) | CA1108786A (en) |
| DE (1) | DE2844059C2 (en) |
| FR (1) | FR2408887A1 (en) |
| GB (1) | GB2009492B (en) |
| IT (1) | IT1109219B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57150889U (en) * | 1981-03-17 | 1982-09-21 | ||
| JPS6010262U (en) * | 1983-07-01 | 1985-01-24 | 日本電気株式会社 | fluorescent display tube |
| JPS6127052A (en) * | 1984-07-16 | 1986-02-06 | Ise Electronics Corp | Fluorescent character displayer tube |
| JPS6124946U (en) * | 1984-07-18 | 1986-02-14 | 日本電気株式会社 | fluorescent display tube |
| JPS61101793U (en) * | 1984-12-07 | 1986-06-28 | ||
| JPS62291847A (en) * | 1986-06-11 | 1987-12-18 | Nec Corp | Fluorescent display pannel |
| JPS63195940A (en) * | 1987-02-06 | 1988-08-15 | Nec Corp | Fluorescent display panel |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4812668B1 (en) * | 1969-12-13 | 1973-04-21 | ||
| JPS5234904B1 (en) * | 1971-03-20 | 1977-09-06 | ||
| GB1430468A (en) * | 1972-08-10 | 1976-03-31 | Ise Electronics Corp | Display modules |
| JPS5527418B2 (en) * | 1974-01-25 | 1980-07-21 | ||
| JPS5255433A (en) * | 1975-10-31 | 1977-05-06 | Sharp Corp | Display device |
-
1978
- 1978-10-05 CA CA312,755A patent/CA1108786A/en not_active Expired
- 1978-10-10 DE DE2844059A patent/DE2844059C2/en not_active Expired
- 1978-10-23 IT IT51609/78A patent/IT1109219B/en active
- 1978-11-10 GB GB7844006A patent/GB2009492B/en not_active Expired
- 1978-11-14 JP JP14040278A patent/JPS5496357A/en active Pending
- 1978-11-14 FR FR7832111A patent/FR2408887A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5496357A (en) | 1979-07-30 |
| GB2009492B (en) | 1982-05-19 |
| FR2408887A1 (en) | 1979-06-08 |
| FR2408887B1 (en) | 1983-07-18 |
| GB2009492A (en) | 1979-06-13 |
| DE2844059C2 (en) | 1982-08-19 |
| DE2844059A1 (en) | 1979-05-17 |
| IT1109219B (en) | 1985-12-16 |
| IT7851609A0 (en) | 1978-10-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |