CA1105143A - Parallel analog-to-digital converter - Google Patents
Parallel analog-to-digital converterInfo
- Publication number
- CA1105143A CA1105143A CA267,300A CA267300A CA1105143A CA 1105143 A CA1105143 A CA 1105143A CA 267300 A CA267300 A CA 267300A CA 1105143 A CA1105143 A CA 1105143A
- Authority
- CA
- Canada
- Prior art keywords
- emitter
- transistors
- analog
- coupled
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
Abstract
PARALLEL ANALOG-TO-DIGITAL CONVERTER
ABSTRACT OF THE DISCLOSURE
A high-speed analog-to-digital converter includes a plurality of parallel-connected comparators, AND gates, and emitter followers which produce a coded output, for example, binary or Gray code, in accordance with preselected different discrete analog signal levels.
Each comparator exhibits a non-linear transfer characteristic so that the voltage gain is boosted for differential inputs near zero volts. A
predetermined hysteresis may be introduced in the transfer character-istic to reduce comparator response to low level oscillation and noise.
ABSTRACT OF THE DISCLOSURE
A high-speed analog-to-digital converter includes a plurality of parallel-connected comparators, AND gates, and emitter followers which produce a coded output, for example, binary or Gray code, in accordance with preselected different discrete analog signal levels.
Each comparator exhibits a non-linear transfer characteristic so that the voltage gain is boosted for differential inputs near zero volts. A
predetermined hysteresis may be introduced in the transfer character-istic to reduce comparator response to low level oscillation and noise.
Description
BACKGROUND 0~ THE INVENTION
N
Parallel analog~to-dlgital convertPrs utili~lng 2 -7 compara-eors to produce N logic blts are well-known ln ~he-art, a~ exempliflPd by V.S. Patent No. 3,539,831. Typically ~he analog lnput signal 15 com-p~red to a linearly dlvlded reference voltage, and the comparator o~t-puts are encoded in a useabl~ digltal form. Prlor encodlng clrcults have utilized complex logic networks, resulting in additlon~l delay tlmes which reduce conversion speed. Al~o, with the many parts re-quired, such converters were costly and consumed power excessively.
8 0 Two problems addressed by investlgators in the art are to increase conversion speed and to increa~e input resolution by ~lim-lnatlng the presence of circult hysteresls about the balanced differ-I enClal input voltage. Con~ersion tlmes of less than 8 nanoseconds ; l have been achieved by the use of strobed comparators. One example of strobed comparators is described by D.R. Breuer, 1972 Internatlonal ', ' . ' , ' ' .
. ~ ' ,~ ' ' ' , . . . -. ~; . . ~ :- .
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- , . . .
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:' ' ' ' ' ' . : ' .. ' , .. ' ., . ' . ., , . .:, . : ,'. . . ' .. .
,' " ' ' . ' :'' .~ ... ,.'.. '.. ,'' "' ' ' ' ' '' " : ' ~' .' ' ' . ' : . ' ' ' ', ' : . ' . ,., ', ' . ' - : . :': ,:: ,:. .. .
': ' , ' . ` ' . ' ' ' . - ' ' '' ' ', , ' . '.:, . . , " ' ' ' . ' ' ' ' ",: . ' ' . ' .
.` ',., : ' ' ' :' '',, '. , .-, . '' . .. '. . ' :
. ~ ~ ' . ' ~". ' . ' ' '' ' ' ' ' ' .' ., .' '' .. ,: . . ', " ,: ' . ' .' . " . ' ' . " : ' .
:'' ~' '.:'. ' ' . ' : ' . ' .'.' . . , ' .. ' , . . , :
: . . ' : ' . ' ' ,: ' ' : - - ' ' . ' , '' : , .
~ :: : : : ~ :
Solid-State Circuits Conference Digest of Technical Papers, pages 146-1~7.
The presence of circuit hysteresis, which is an intrinsic characteristic of some comparators, results in a deadband about the balanced differentiaL input and limits resolution. While the trend has been to completely eliminate such hysteresis, a predetermined small amount of hysteresis may be desirable to m:inimize error introduced by low-level oscillation and noise, while still providing good resolution.
SUMMARY OF THE INVENTION_ _ _ In accordance with an aspect of the invention there is provided an analog-to-digital converter, comprising: a reference voltage source providing 2N different discrete voltage levels; switch means operatively coupled to said reference voltage source for providing 2 1 complementary digital signals responsive to an analog signal in comparison with said voltage levels, said switch means including 2N-l comparators connected in parallel, each of said comparators including a first pair of emitter-; coupled transistors which operate as a switch responsive to the comparison of an analog signals with one of said discrete voltage levels applied to the respective bases thereof and a second pair of emitter-coupled transistors to operate as a regenerative latching means for reinforcing the complementary digital output therefrom, said second pair of emitter-coupled transistors having a selectable, pre-biasing current source connected to the emitters thereof to pre-bias said second pair of emitter-coupled 30 tran~sistors to a predetermined threshold level; gate means operatively coupled to said comparators for receiving said
N
Parallel analog~to-dlgital convertPrs utili~lng 2 -7 compara-eors to produce N logic blts are well-known ln ~he-art, a~ exempliflPd by V.S. Patent No. 3,539,831. Typically ~he analog lnput signal 15 com-p~red to a linearly dlvlded reference voltage, and the comparator o~t-puts are encoded in a useabl~ digltal form. Prlor encodlng clrcults have utilized complex logic networks, resulting in additlon~l delay tlmes which reduce conversion speed. Al~o, with the many parts re-quired, such converters were costly and consumed power excessively.
8 0 Two problems addressed by investlgators in the art are to increase conversion speed and to increa~e input resolution by ~lim-lnatlng the presence of circult hysteresls about the balanced differ-I enClal input voltage. Con~ersion tlmes of less than 8 nanoseconds ; l have been achieved by the use of strobed comparators. One example of strobed comparators is described by D.R. Breuer, 1972 Internatlonal ', ' . ' , ' ' .
. ~ ' ,~ ' ' ' , . . . -. ~; . . ~ :- .
, ~,.
- , . . .
', ' , ' : '' " . , . , ~ ' ' ' " ' ' ' ,'. ' :~, .:' ' ,', .:' ', ~ . ' ' '.. :.,'. .'' ,.'-' ~,'" "' ' ` ` . , ., " ' , ' ', ',, ', ' '' ' ,' , , ' ,,.',, , : ' ,' ':' ." " "" ,i . ' ' ". ' ::' . " ' ' ' .
:' ' ' ' ' ' . : ' .. ' , .. ' ., . ' . ., , . .:, . : ,'. . . ' .. .
,' " ' ' . ' :'' .~ ... ,.'.. '.. ,'' "' ' ' ' ' '' " : ' ~' .' ' ' . ' : . ' ' ' ', ' : . ' . ,., ', ' . ' - : . :': ,:: ,:. .. .
': ' , ' . ` ' . ' ' ' . - ' ' '' ' ', , ' . '.:, . . , " ' ' ' . ' ' ' ' ",: . ' ' . ' .
.` ',., : ' ' ' :' '',, '. , .-, . '' . .. '. . ' :
. ~ ~ ' . ' ~". ' . ' ' '' ' ' ' ' ' .' ., .' '' .. ,: . . ', " ,: ' . ' .' . " . ' ' . " : ' .
:'' ~' '.:'. ' ' . ' : ' . ' .'.' . . , ' .. ' , . . , :
: . . ' : ' . ' ' ,: ' ' : - - ' ' . ' , '' : , .
~ :: : : : ~ :
Solid-State Circuits Conference Digest of Technical Papers, pages 146-1~7.
The presence of circuit hysteresis, which is an intrinsic characteristic of some comparators, results in a deadband about the balanced differentiaL input and limits resolution. While the trend has been to completely eliminate such hysteresis, a predetermined small amount of hysteresis may be desirable to m:inimize error introduced by low-level oscillation and noise, while still providing good resolution.
SUMMARY OF THE INVENTION_ _ _ In accordance with an aspect of the invention there is provided an analog-to-digital converter, comprising: a reference voltage source providing 2N different discrete voltage levels; switch means operatively coupled to said reference voltage source for providing 2 1 complementary digital signals responsive to an analog signal in comparison with said voltage levels, said switch means including 2N-l comparators connected in parallel, each of said comparators including a first pair of emitter-; coupled transistors which operate as a switch responsive to the comparison of an analog signals with one of said discrete voltage levels applied to the respective bases thereof and a second pair of emitter-coupled transistors to operate as a regenerative latching means for reinforcing the complementary digital output therefrom, said second pair of emitter-coupled transistors having a selectable, pre-biasing current source connected to the emitters thereof to pre-bias said second pair of emitter-coupled 30 tran~sistors to a predetermined threshold level; gate means operatively coupled to said comparators for receiving said
- 2 -.
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complementary ~i(3ital signals and providing 2N voLtage levels, wherein only one oE said digital outputs is enabled at a time; and encoding means operatively coupled to said gate means for receivlng said digital outputs and producing N-bit data words therefrom wherein a different N-bit data word is provided for each of said 2N discrete voltage levels~
In accordance with the present invention, a high-speed analog-to-digltal converter includes a plurality of parallel-connected comparators which are associated with preselected different discrete analog levels. Each comparator exhibits a non-linear transfer characteristic such that gain is relatively high when the difEerential input voltage thereof is near zero and becomes relatively low as the differential input voltage thereoE increases.
A predetermined amount of hysteresis may be introduced in the transfer characteristic to thereby produce a predeter-; mined "deadband" about the zero volts differential input point. Thus, the comparator response to low-level oscillation and noise is reduced while maintaining good gain and resolution characteristics.
The comparator outputs are connected to an encoding circuit, for example, binary or Gray codes, comprising an AND gate and an emitter follower associated with each of the aforementioned analog levels, and the AND gate-emitter follower stages are connected so that only one of the plurality thereof is enabled at any time. The emitter followers have as many emitters as the number of coded bits represented thereby, and such emitters are connected to appropriate parallel output lines :
- 2a -~: , ,. . - .- : ., ' so that when a particular eml~ter follower i9 enabled it prod~ce3 the coded information representative of the assoclated diRcrete analog level.
It i6 therefore, one obJect of the present invention to pro-vide an improved high-speed digit~l-to-analog converter.
It is another obJect to provide a comparator clrcult having a transfer characteristic havlng a predetermlned hystere~is therein about the zero differential input voltage.
It is a further obJect to provlde a comparator circuit havlng I ~ a non-linear gain characteristlc whereln gain ls boosted near the zero differential lnput voltage.
It i6 yet another obJect to provide a novel dlgital encoder for an analog-to-digltal converter.
It ls yet a further obJect to provide a digital encoder for an ; analog-to-digital converter utilizlng simplified circuits.
I~ is still another obJect to provide a p~r~llel analog-to-digital converter which consumes a minlmum amount of power.
Other ob~ects and attainments of the present invention will become apparent to those skilled in the art upon a reading of the following de~ailed description when taken in conJunction with the drawings.
BRIEF DESCRIPTION _F_THE DRAWINGS
Flg. lA shows a comparator circuit~in accordance wlth the present invention;
Fig. lB illustrates a non linear transfer curvP with pre-determined hystere~is of the comparator of Fig. lA;
Fig. lC illustrates a non linear transfer curv without hys~eresis of the comparstor of Flg. lA;
.
'.
- . . ' . ' , ' .:
Fig. 2 shows an encoding circult for an analog-to-digital converter in accordance wi.th the pre~ent invention;
Flg. 3 shows an overall block dla~ram of a 4-blt parallel analog-to-dlgital converter; and Fig. 4 show~ a single comparator cell and its assoclated encodlng circuit representatlve of the preferred embodlment of the present lnventlon.
D~TAILED DESCRIPTION OF THE INVENTION
A comparator clrcult whlch exhlbits non-linear galn i8 shown 0 in Fig. lA. A first pair of emitter coupled transistors 1 and 2 receive an input signal from a slgnal source 4 whlch is applled to the base of transistor 1 and compared with the ground reference on the base of transistor 2. A current sin~ 5 connected to the common emiteers permlts a current IT to be switched through elther transistor 1 or 2 in accord-ance with the polarity of the input signal. Transifitors 7 and 8 com-prise a second emitter-coupled pair, wlth the common emltters connected to a current sink 10 which provldes an operating current Ix. Tran-sistors 7 and 8 are coupled t~ the collector circuits of transistors l and 2 ln such a manner as to provide regeneratlve feedback. The co~-~0 lectors of transistors 7 and 8 are cross coupled and separated from therespective bases of the transistors by level shifting batteries 12 and 13, which may suitably be conventional d~odPs or Zener diodes. Resis-tors 15 and 16 having equal values RC provide the collectDr load for the circuit whlle the output is taken between termlnals 18 and 19. It may ~` be appreciated, as an example, that a positive signal at the base of .
transistor l results in a posltive signal at the base of transistor 8 so that these two trans:lstors are turnPd on while trans~stors 2 and 7 are .
. ~ .
~ ~ ' , , .
turned off. Hence, the current IT through transistor l i~ reinforced by the current IX through transistor 8 at node 21. On'the other hand, a negatlve pol~rity at the base of translstor l causes trnnslstors 2 and 7 to be conducting while translstors l and 8 are turned off.
When the hereinabove describec1 circuit ls operated as a strobed comparator, the current IT i8 switched between the flrst and second pairs of transistors, and transll3tors 7 and R operate as a latch.
The current IX in this case serves to prebias translstorfi 7 and 8 to the turn on threshold level to speed up turn on of either translstor 7 or 8 when strobed. The prebia~ing current IX causes the apparent impedance at the bases of transistors 7 and 8 to be negative, which ln turn has' the effect of increasing the gain of transistors l and 2 whenever the differentlal input voltage at the bases thereof l~ near zero. Thls negative impedance effect can be made large enough to cause hysteresls in the transfer'curve, as seen in Figs. lB and lC. The voltage gain of the strobed comparator ~ay be deflned by the following equation:
IT
AV = ~ c _ l+cosh(Vin/VT) ~ _ RC l+cosh(VOut/VT) Where VT is the well-known volt equivalent of temperature and i8 defined as Boltzmann's constan~ multlplied by the Kelvin temperature and divided 2 O by the charge of an electron and is equal to about 26 milllvolts at room temperature.
The condiiton for hysteresis in the transfer curve to exist is IXRc~2VT. The transfer curve of Pig. lB shows a hysteres~s loop at the zero crossing of the absciaaa nd the ordinate, and the amount of - hysteresis afectlng ehe co~parator is equal to the limits of the dead-bahd window, or ' VIN'. Assoclated wlth each VIN' polnt in Fig. lB ls a value of V0', which is representatlve of the comparator output voltage.
' ~ - .
k~
complementary ~i(3ital signals and providing 2N voLtage levels, wherein only one oE said digital outputs is enabled at a time; and encoding means operatively coupled to said gate means for receivlng said digital outputs and producing N-bit data words therefrom wherein a different N-bit data word is provided for each of said 2N discrete voltage levels~
In accordance with the present invention, a high-speed analog-to-digltal converter includes a plurality of parallel-connected comparators which are associated with preselected different discrete analog levels. Each comparator exhibits a non-linear transfer characteristic such that gain is relatively high when the difEerential input voltage thereof is near zero and becomes relatively low as the differential input voltage thereoE increases.
A predetermined amount of hysteresis may be introduced in the transfer characteristic to thereby produce a predeter-; mined "deadband" about the zero volts differential input point. Thus, the comparator response to low-level oscillation and noise is reduced while maintaining good gain and resolution characteristics.
The comparator outputs are connected to an encoding circuit, for example, binary or Gray codes, comprising an AND gate and an emitter follower associated with each of the aforementioned analog levels, and the AND gate-emitter follower stages are connected so that only one of the plurality thereof is enabled at any time. The emitter followers have as many emitters as the number of coded bits represented thereby, and such emitters are connected to appropriate parallel output lines :
- 2a -~: , ,. . - .- : ., ' so that when a particular eml~ter follower i9 enabled it prod~ce3 the coded information representative of the assoclated diRcrete analog level.
It i6 therefore, one obJect of the present invention to pro-vide an improved high-speed digit~l-to-analog converter.
It is another obJect to provide a comparator clrcult having a transfer characteristic havlng a predetermlned hystere~is therein about the zero differential input voltage.
It is a further obJect to provlde a comparator circuit havlng I ~ a non-linear gain characteristlc whereln gain ls boosted near the zero differential lnput voltage.
It i6 yet another obJect to provide a novel dlgital encoder for an analog-to-digltal converter.
It ls yet a further obJect to provide a digital encoder for an ; analog-to-digital converter utilizlng simplified circuits.
I~ is still another obJect to provide a p~r~llel analog-to-digital converter which consumes a minlmum amount of power.
Other ob~ects and attainments of the present invention will become apparent to those skilled in the art upon a reading of the following de~ailed description when taken in conJunction with the drawings.
BRIEF DESCRIPTION _F_THE DRAWINGS
Flg. lA shows a comparator circuit~in accordance wlth the present invention;
Fig. lB illustrates a non linear transfer curvP with pre-determined hystere~is of the comparator of Fig. lA;
Fig. lC illustrates a non linear transfer curv without hys~eresis of the comparstor of Flg. lA;
.
'.
- . . ' . ' , ' .:
Fig. 2 shows an encoding circult for an analog-to-digital converter in accordance wi.th the pre~ent invention;
Flg. 3 shows an overall block dla~ram of a 4-blt parallel analog-to-dlgital converter; and Fig. 4 show~ a single comparator cell and its assoclated encodlng circuit representatlve of the preferred embodlment of the present lnventlon.
D~TAILED DESCRIPTION OF THE INVENTION
A comparator clrcult whlch exhlbits non-linear galn i8 shown 0 in Fig. lA. A first pair of emitter coupled transistors 1 and 2 receive an input signal from a slgnal source 4 whlch is applled to the base of transistor 1 and compared with the ground reference on the base of transistor 2. A current sin~ 5 connected to the common emiteers permlts a current IT to be switched through elther transistor 1 or 2 in accord-ance with the polarity of the input signal. Transifitors 7 and 8 com-prise a second emitter-coupled pair, wlth the common emltters connected to a current sink 10 which provldes an operating current Ix. Tran-sistors 7 and 8 are coupled t~ the collector circuits of transistors l and 2 ln such a manner as to provide regeneratlve feedback. The co~-~0 lectors of transistors 7 and 8 are cross coupled and separated from therespective bases of the transistors by level shifting batteries 12 and 13, which may suitably be conventional d~odPs or Zener diodes. Resis-tors 15 and 16 having equal values RC provide the collectDr load for the circuit whlle the output is taken between termlnals 18 and 19. It may ~` be appreciated, as an example, that a positive signal at the base of .
transistor l results in a posltive signal at the base of transistor 8 so that these two trans:lstors are turnPd on while trans~stors 2 and 7 are .
. ~ .
~ ~ ' , , .
turned off. Hence, the current IT through transistor l i~ reinforced by the current IX through transistor 8 at node 21. On'the other hand, a negatlve pol~rity at the base of translstor l causes trnnslstors 2 and 7 to be conducting while translstors l and 8 are turned off.
When the hereinabove describec1 circuit ls operated as a strobed comparator, the current IT i8 switched between the flrst and second pairs of transistors, and transll3tors 7 and R operate as a latch.
The current IX in this case serves to prebias translstorfi 7 and 8 to the turn on threshold level to speed up turn on of either translstor 7 or 8 when strobed. The prebia~ing current IX causes the apparent impedance at the bases of transistors 7 and 8 to be negative, which ln turn has' the effect of increasing the gain of transistors l and 2 whenever the differentlal input voltage at the bases thereof l~ near zero. Thls negative impedance effect can be made large enough to cause hysteresls in the transfer'curve, as seen in Figs. lB and lC. The voltage gain of the strobed comparator ~ay be deflned by the following equation:
IT
AV = ~ c _ l+cosh(Vin/VT) ~ _ RC l+cosh(VOut/VT) Where VT is the well-known volt equivalent of temperature and i8 defined as Boltzmann's constan~ multlplied by the Kelvin temperature and divided 2 O by the charge of an electron and is equal to about 26 milllvolts at room temperature.
The condiiton for hysteresis in the transfer curve to exist is IXRc~2VT. The transfer curve of Pig. lB shows a hysteres~s loop at the zero crossing of the absciaaa nd the ordinate, and the amount of - hysteresis afectlng ehe co~parator is equal to the limits of the dead-bahd window, or ' VIN'. Assoclated wlth each VIN' polnt in Fig. lB ls a value of V0', which is representatlve of the comparator output voltage.
' ~ - .
3 r-, ~
The value of V0' may be iound from the followlng ~quatlon;
.
~ ~R
V Y h-l ( C
For values of VIN CkVT, the hyatere~is may be approximated as follows.
IN ITRC [ Vl' ~
The transfer curve of Flg. lB ifi dr~wn for a speclfic comparator wherein IX ~ 500 ~ A, IT ~ 2.0 ~A, and RC ~ 200 ohms. The amount of hysteresls 19 calculated to be *VIN~ ~ ~3.2 mV.
The tran6fer curve ahown in Flg. lC 1~ without hyateresls.
Thls cur~e exempllfles the increase ln galn about the dlfferentlal input l~ voltage point. As opposed eo the tran6fer curve wlth hysteresis, the condlton for the curve of Fig. lC wlthout hysteresis is IxRc ~ 2 VT.
The voltage gain ~, whlch 1~ defined as the ~lope of the tranRfer curve, may be found by the followlng equation:
) V( 3 ) The curve shown in Fig. lC is for a comparator wherein IX ~ 250 ~A, IT
2.0 mA, and RC ~ 200 ohms. The voltage gain of transi6tors 7 and 8 at VIN ~ 0 may be calculated to be 26.
It can be appreciated tha~ the transfer curves dlscussed in the two foregoing examples ~ay be ad~usted by selecting values of lx, , IT, and RC so that any amount of hysteresis mDy be designed into the comparator~to provlde the desired deadband window near the balanced dlfferential lnput condltion to ~lnlmize comparator response to low level signals, oscillation, and noise.
' ' - .
An encoding ci~cuit for an N-blt a~alog-to-dlgital converter is shown ln Fig. 2, An analog slgnal from signal source 25 i~ applied simultaneously to 2 compar~tors 27-33 and compared with independent discrete voltage level~ e~t~blished by a llnear vol~age divider ln-cluding resi~tors 36-42 whlch are serlally connected between two sources of reference voltage. The comparators ha~e complementary Q and Q
current outputs whlch are coupled to separate emitter6 of tranalstors 45-53, which transistors function as ~ogical AND gates as described hereinbelow.
~o Transistors 45-53 have a suitable biasing vol~age applled to the ba~es thereof, and these translstors include emltter re~isto~s S7-72 connected to ground, and collector load resi~tors 75-83 connected to a suitable source of positlve voltage. Also connected to the collectors of these transistors are emitter follower transistor~ 85-92. Each emitter follower has multiple emltters whlch are connected to the N
outpu~ lines in accordance wlth the quantlzed bits of the daea word that each emitter follower represents. The turn on of any one of the emltter followers 85-92 places approprlate lo~ical ones on the output llnes.
Resistors 95-99 are connected between the emltters and ground to provide the zero logic level for all output lines.
Transistors 46-52 provide the encoding for up to N logical bits and include dual emitters which for each transistor are connected to the complementary outputs of ad~acent coMparators. Transi~tor 53 ls connected to the Q output of comparator 33 and represents zero, while ; transistor 4S is connected to the Q output of comparator 27 and rep-resents an over-range condition. Consequently, the collector of tran-slstor 53 is not connected to a subsequent e~itter follower slnce no logical ones need to be placed upon any of the output lines. Transistor 45 is connected l:o emitter follower 85 which has a single emitter , ~ 7 _ .
~ .
', . ~ , ' ' 5~3 connected to the over-range~output line, To see how only one of the emitter followers 85-92 may be àc~iv~ed a~ sny given ~lme by the AND gates ~5-53, assume that the signal from slgnal sou~ce ~5 is more negatlve than the negative voltage applied to reslstor 42. In thi3 conditlon, all of the Q outputfi are low while all of the Q output~ are high. Ilpon examinatlon of the operatlng condltlon of the AND gates, it can be dlscerned that only transistor 53 is turned off by the logical high appli~d to the emitter thereof while each of the transistor6 45-52 has at lesst one logical low applied l~ thereto, turning that transistor on. The voltage developed across resistors 7S-82 by the conduction of these transistors holds the bases of emltter follower translstors 85-92 negative, and therefore the data word on the output llnes i~ all zeros. When the signal from slgnal source 25 moves positive through the voltage at the Junction of re-sistor~ 41 and 42, comparator 33 switches, placing a logicsl high on the Q output line and a logical low on the Q output line. Thls action turns transistor 53 on and a~ the same time transistor 52? ~lready having a logical high rom the Q output of comparator 32 applied thereto, turns of f. The base of transiitor 92 1~ carried posltlve, pulling up on the 2~ single emitter thereof and placing a logical one on the coded output line corresponding to 1. Further, as the sigslal from signal ~ource 25 moves toward the posi~ive refere~ce valtage applied to re~ls~or 36, each comparator is switched in turn. This results in the sequential Pnabllng of the emltter followers is~ one at a time fashion untll emitter follower 85 ls enabled representing the over-range condltion. In actual pract~ce the signal from signal ~ource 25 will be an analog signal and ls expected to vary within the llmits of the dynamlc range. As shown in Fig. 2, the encoding sche=e can be expanded to include as many blt~ as necessary.
The emitter and co:Llector resistors in the encoding circuit are chosen , ~ -8-~ ~ .
' : :` . - .
to provlde proper gain and fan out capabillties Eor the cl~cult. While the foregoing analog-eo-dlgltal converter may'be constructed of discrete component~, the clrcuit lenda itself ~o renli2a~ion ~n monollthlc integrated circuit Porm.
A complete 4-bit analog-to~digltal converter utillzlng ehe basic concepts set forth in t~e foregolng de~crlptlon ls shown ln block dlagram form in Flg. 3. An analog ~lgnal from ~ignal ~ource 102 i8 applied simultaneou~ly to comparators lb5-120 and compared to the refér ence voltage~ established by ~erially connected resistors 125-140 , IV between suitable ~ources of posltlve and negatlve reference voltage.
The resistor~ 125-140 mRy be fabricated utilizlng hybrld circult tech-niques whereln the thln film resistors may be trimmed withln close tolerances to values which provide flrse-order compen~atlon for the comparator input current IB. The values R~- R15 for these resistorfi may be calculated from the ollowlng equation ~herein K ~ 0, 1, ..., lS:
:
.
-16 -~
1 +
A strobe clock circui~ 145 generates a str~be signal for strobing the compsrators to increase the switching speed thereof to provide a high speed real time data acquisition rate~ The present 2 0 analog-to-digital converter~has performed at conversion rates in exce~s of 100 MHz. The complementary outputs of the comparators are applied to AND gate~ 150-166 to provide outputs corresponding to any one of 17 discrete levels including an over ran~e level. An encoder clrcuit 170 .
converts the AND gflte outputs to a 4 bit quantized representa~lon whlch is made available on output lines 172. An output stage 174 lncluding buffer amplifiers ~lay be provided ln ensure ECL compatib~lity.
-: :
' ' : ' : ' ' ~.. . . . .. . . .. . . .
A single comparator cell and lts a~sociated encoding circuit is shown in Fig. 4. Emitter followers 200 and 201, to which VINand a reference voltage are connected re6pectively, provlde lsolatlon to make the comparator appear as a constant load on the reference voltage dl~lder, independent of VIN. Transistors 204 and 205, connected through their respectlve emltter resistors 207 and 208 to a ~ultable source of negative voltage, provlde high lmpedance current sinks for emitter follower transistor6 200 and 201.
The comparator conslsts of e~ltter-coupled transistors 215 and 216 and cross-coupled latchlng translstors 218 and 219. Most of the avallable current for ~hese translstor palrs i8 furnlshed by constant-current slnk 225 and lts assoclated emltter resl6tor 226, and routed via a current switch comprising transl6tors 230 and 232. Latching tran-sl6tors 218 and 219 are pre-biased to the turn~on thre~hold by a slight amount of current provided by resi6tor 235 to increase the switching speed thereof. Emltter-follower~ lncluding translstor6 23~ and 240 and reslstors 242 and 244 are coupled between the collector~ of transis~ors 215 and 216 and the base3 of transistor6 218 and 219 respectlvely. The ~-comparator outputs are coupled through resistors 246 and 248 to AND gate transistors 250 and 252.
AN~ gate translstors 250 and 252 are dual emltter transistors and operate sub~tantially as descrlbed in connec~lon wlth transifitors 46-52 of Fig. 2. Only one emitter of each traDsi~tor 18 shown con-nected, but it 19 u~derstood that the second emltter of each transistor is connected to an output of an adjolning comparator cell. Resis~ors 254 and 256 provlde the proper load for the comparator outpu~ and .
thereby establish the galn ~hereof as well as set~ing up the proper biasing condltlons for transistors 250 and 252. The collectors of transistors 2~0 and 252 are connected through resistors 260 and 262 to ..
..
~ 5~3 a suitable sourc~ of positive voltage and also to emitt.er ollower output transistors 265 and 267. Tr~nsistors 265 and 267 have ~ultiple emltters as prevlou31y di~cussed for tr~nslstors 85-92. The emltters are connected to the encoded output bus.
Strobe signals having opposlite polarltles are applled ~o the bases of tran6istors 230 and 232 to swLtch the current from translstor 225 between the two pairs of emitter coupled translstors ~15-216 and 218-219. For this circult, assume that the strobe slgnal is occurring at a frequency of 100 MHz, has a duty cycle of 50%, and has sufficient amplitude to cleanly swltch the transiator pair 230-232. Strobe signals of either higher or lower frequencies wlll work ~ust as well in other applications, and the duty cycle may be ad~usted to any ratio Aesired.
The input slgnal VIN is applied to the base of translstor ~00 and compared with the reference voltage applied to the base of tran-sistor 201. Although the operating current for co~parator 215-216 ls continuously switched on and off, the comparator behave6 in a conven-- - tional manner in its active state. The ability of the comparator to respond to small input dlfPerences is made posslble by the use of switched posltlve feedback. When ~he operating current i9 suddenly æ o switched f~om transistor 230 to 2329 latch pair 218-219 responds to the signal polarlty at the collectors of translstors 215 and 216 and switches regeneratlvely to the appropriate state. The emitter followers 238 and 240 preven~ the latch pair from saturatiTIg. As mentioned previously, translstors 218 and 219 do not Xave to overcome the ~unction storage time due to the pre-biasing current`through resistor 235, thus switching A time ls minimlzed. In additio:n to ensuring a loglcal 1 or 0 declsion ; for the comparator, the switching of operating current has the effect of sampling the lnpot; that is to say, changes in input VI~, subsequent to :, : .
~ . . :
,, ~ . . ~ . . :
:, : . ~: -t~
stroblng do not effect the co~parator output until the strobe ~lgnal is removed. As discussed previously, a predeten~ined am~unt o hysteresi6 ~ay be designed into the clrcuit by selecting clrcult operatlng param-eters in'accordance with the herelnabove dlscussed equations.
The AND ~ste~ 250 and 252 act ln con~unction wlth the ad~oin-lng comparators to control the operating state of the output emitter followers 265 and 267. For example9 current into either emitter of translstor 250 will develop a voltage across resl6~0r 260 which wlll hold tr~nsistor 265 in ehe off state. It can be di~cerned that if the input signal VIN i6 posltive wlth respect to the reference slgnal at the base of transistor 201, flll of the available co~parator operating current will flow through reslstor 2~6 and into the emitter of tran-~lstor 25Q, leaving no current to flow through reslstor 248. If there is no current flowing into transistor 252 rom the ad~oin~ng comparator, the base of 267 will be pulled po~ltive thrnugh re6i~tor 262, turnlng transi8tor 267 on and placlng logical ones on the encoded output bus lines to which ~he transiRtor emitters are connected.
The circuit herelnabove deacrIbed is of such s~pliclty and consu~es such little power that ln~egratlng 16 comparators on a slngle ~0 chip together with an efficient 4-bit binary encoder has been achieved with a great deal of succea~. Powee consumptlon of a single comparator cell is approximately 32 milliwatts. Resolution ls 4-bits plus over range, and accuracy a~ the lO0 MHz conversion rate i8 8 blts.
In summary, a high speed analog~to-digital converter lncludlng a plurality of parallel connected strobed co~parators and a simplified encoding scheme hns been described~ Each com~arator exhiblts a non-linear transer characteri~tlc to boost the gain when the differential input voltage is n~ar zero, and a predetermined amount of hysteresls in the transfer characterlstic may be introduced to reduce the effects ' . ~ . ' .
.' .... ~ .
- ' :' , D ~ 3 of low level oscillatlon and nolse whlle stlll malntalnlng good gain and resolutlon characteristic3. The comparator output~ are con~ected to a plurality of ~ND gates and thelr associated outpu~ emitter followers, only one of whlch may be enabled at any given tlme, The output emitter followers have multlple emitters which are connected to the output bus in accordance with the data word that the emitter follower reprefients.
It will be obvlous to those Iskllled in the art that many changes may be made in the details of the hereinabove described pre-ferred embodiment of the present inven~ion wlthout departing from the spirit of the invention. For example, two or more of the hereinabove~
described analog-to-dlgital converters may be stacked to provide an expanded N-blt system.
, ...; ~: .
,' ~
.~` . .
,: . `: .
The value of V0' may be iound from the followlng ~quatlon;
.
~ ~R
V Y h-l ( C
For values of VIN CkVT, the hyatere~is may be approximated as follows.
IN ITRC [ Vl' ~
The transfer curve of Flg. lB ifi dr~wn for a speclfic comparator wherein IX ~ 500 ~ A, IT ~ 2.0 ~A, and RC ~ 200 ohms. The amount of hysteresls 19 calculated to be *VIN~ ~ ~3.2 mV.
The tran6fer curve ahown in Flg. lC 1~ without hyateresls.
Thls cur~e exempllfles the increase ln galn about the dlfferentlal input l~ voltage point. As opposed eo the tran6fer curve wlth hysteresis, the condlton for the curve of Fig. lC wlthout hysteresis is IxRc ~ 2 VT.
The voltage gain ~, whlch 1~ defined as the ~lope of the tranRfer curve, may be found by the followlng equation:
) V( 3 ) The curve shown in Fig. lC is for a comparator wherein IX ~ 250 ~A, IT
2.0 mA, and RC ~ 200 ohms. The voltage gain of transi6tors 7 and 8 at VIN ~ 0 may be calculated to be 26.
It can be appreciated tha~ the transfer curves dlscussed in the two foregoing examples ~ay be ad~usted by selecting values of lx, , IT, and RC so that any amount of hysteresis mDy be designed into the comparator~to provlde the desired deadband window near the balanced dlfferential lnput condltion to ~lnlmize comparator response to low level signals, oscillation, and noise.
' ' - .
An encoding ci~cuit for an N-blt a~alog-to-dlgital converter is shown ln Fig. 2, An analog slgnal from signal source 25 i~ applied simultaneously to 2 compar~tors 27-33 and compared with independent discrete voltage level~ e~t~blished by a llnear vol~age divider ln-cluding resi~tors 36-42 whlch are serlally connected between two sources of reference voltage. The comparators ha~e complementary Q and Q
current outputs whlch are coupled to separate emitter6 of tranalstors 45-53, which transistors function as ~ogical AND gates as described hereinbelow.
~o Transistors 45-53 have a suitable biasing vol~age applled to the ba~es thereof, and these translstors include emltter re~isto~s S7-72 connected to ground, and collector load resi~tors 75-83 connected to a suitable source of positlve voltage. Also connected to the collectors of these transistors are emitter follower transistor~ 85-92. Each emitter follower has multiple emltters whlch are connected to the N
outpu~ lines in accordance wlth the quantlzed bits of the daea word that each emitter follower represents. The turn on of any one of the emltter followers 85-92 places approprlate lo~ical ones on the output llnes.
Resistors 95-99 are connected between the emltters and ground to provide the zero logic level for all output lines.
Transistors 46-52 provide the encoding for up to N logical bits and include dual emitters which for each transistor are connected to the complementary outputs of ad~acent coMparators. Transi~tor 53 ls connected to the Q output of comparator 33 and represents zero, while ; transistor 4S is connected to the Q output of comparator 27 and rep-resents an over-range condition. Consequently, the collector of tran-slstor 53 is not connected to a subsequent e~itter follower slnce no logical ones need to be placed upon any of the output lines. Transistor 45 is connected l:o emitter follower 85 which has a single emitter , ~ 7 _ .
~ .
', . ~ , ' ' 5~3 connected to the over-range~output line, To see how only one of the emitter followers 85-92 may be àc~iv~ed a~ sny given ~lme by the AND gates ~5-53, assume that the signal from slgnal sou~ce ~5 is more negatlve than the negative voltage applied to reslstor 42. In thi3 conditlon, all of the Q outputfi are low while all of the Q output~ are high. Ilpon examinatlon of the operatlng condltlon of the AND gates, it can be dlscerned that only transistor 53 is turned off by the logical high appli~d to the emitter thereof while each of the transistor6 45-52 has at lesst one logical low applied l~ thereto, turning that transistor on. The voltage developed across resistors 7S-82 by the conduction of these transistors holds the bases of emltter follower translstors 85-92 negative, and therefore the data word on the output llnes i~ all zeros. When the signal from slgnal source 25 moves positive through the voltage at the Junction of re-sistor~ 41 and 42, comparator 33 switches, placing a logicsl high on the Q output line and a logical low on the Q output line. Thls action turns transistor 53 on and a~ the same time transistor 52? ~lready having a logical high rom the Q output of comparator 32 applied thereto, turns of f. The base of transiitor 92 1~ carried posltlve, pulling up on the 2~ single emitter thereof and placing a logical one on the coded output line corresponding to 1. Further, as the sigslal from signal ~ource 25 moves toward the posi~ive refere~ce valtage applied to re~ls~or 36, each comparator is switched in turn. This results in the sequential Pnabllng of the emltter followers is~ one at a time fashion untll emitter follower 85 ls enabled representing the over-range condltion. In actual pract~ce the signal from signal ~ource 25 will be an analog signal and ls expected to vary within the llmits of the dynamlc range. As shown in Fig. 2, the encoding sche=e can be expanded to include as many blt~ as necessary.
The emitter and co:Llector resistors in the encoding circuit are chosen , ~ -8-~ ~ .
' : :` . - .
to provlde proper gain and fan out capabillties Eor the cl~cult. While the foregoing analog-eo-dlgltal converter may'be constructed of discrete component~, the clrcuit lenda itself ~o renli2a~ion ~n monollthlc integrated circuit Porm.
A complete 4-bit analog-to~digltal converter utillzlng ehe basic concepts set forth in t~e foregolng de~crlptlon ls shown ln block dlagram form in Flg. 3. An analog ~lgnal from ~ignal ~ource 102 i8 applied simultaneou~ly to comparators lb5-120 and compared to the refér ence voltage~ established by ~erially connected resistors 125-140 , IV between suitable ~ources of posltlve and negatlve reference voltage.
The resistor~ 125-140 mRy be fabricated utilizlng hybrld circult tech-niques whereln the thln film resistors may be trimmed withln close tolerances to values which provide flrse-order compen~atlon for the comparator input current IB. The values R~- R15 for these resistorfi may be calculated from the ollowlng equation ~herein K ~ 0, 1, ..., lS:
:
.
-16 -~
1 +
A strobe clock circui~ 145 generates a str~be signal for strobing the compsrators to increase the switching speed thereof to provide a high speed real time data acquisition rate~ The present 2 0 analog-to-digital converter~has performed at conversion rates in exce~s of 100 MHz. The complementary outputs of the comparators are applied to AND gate~ 150-166 to provide outputs corresponding to any one of 17 discrete levels including an over ran~e level. An encoder clrcuit 170 .
converts the AND gflte outputs to a 4 bit quantized representa~lon whlch is made available on output lines 172. An output stage 174 lncluding buffer amplifiers ~lay be provided ln ensure ECL compatib~lity.
-: :
' ' : ' : ' ' ~.. . . . .. . . .. . . .
A single comparator cell and lts a~sociated encoding circuit is shown in Fig. 4. Emitter followers 200 and 201, to which VINand a reference voltage are connected re6pectively, provlde lsolatlon to make the comparator appear as a constant load on the reference voltage dl~lder, independent of VIN. Transistors 204 and 205, connected through their respectlve emltter resistors 207 and 208 to a ~ultable source of negative voltage, provlde high lmpedance current sinks for emitter follower transistor6 200 and 201.
The comparator conslsts of e~ltter-coupled transistors 215 and 216 and cross-coupled latchlng translstors 218 and 219. Most of the avallable current for ~hese translstor palrs i8 furnlshed by constant-current slnk 225 and lts assoclated emltter resl6tor 226, and routed via a current switch comprising transl6tors 230 and 232. Latching tran-sl6tors 218 and 219 are pre-biased to the turn~on thre~hold by a slight amount of current provided by resi6tor 235 to increase the switching speed thereof. Emltter-follower~ lncluding translstor6 23~ and 240 and reslstors 242 and 244 are coupled between the collector~ of transis~ors 215 and 216 and the base3 of transistor6 218 and 219 respectlvely. The ~-comparator outputs are coupled through resistors 246 and 248 to AND gate transistors 250 and 252.
AN~ gate translstors 250 and 252 are dual emltter transistors and operate sub~tantially as descrlbed in connec~lon wlth transifitors 46-52 of Fig. 2. Only one emitter of each traDsi~tor 18 shown con-nected, but it 19 u~derstood that the second emltter of each transistor is connected to an output of an adjolning comparator cell. Resis~ors 254 and 256 provlde the proper load for the comparator outpu~ and .
thereby establish the galn ~hereof as well as set~ing up the proper biasing condltlons for transistors 250 and 252. The collectors of transistors 2~0 and 252 are connected through resistors 260 and 262 to ..
..
~ 5~3 a suitable sourc~ of positive voltage and also to emitt.er ollower output transistors 265 and 267. Tr~nsistors 265 and 267 have ~ultiple emltters as prevlou31y di~cussed for tr~nslstors 85-92. The emltters are connected to the encoded output bus.
Strobe signals having opposlite polarltles are applled ~o the bases of tran6istors 230 and 232 to swLtch the current from translstor 225 between the two pairs of emitter coupled translstors ~15-216 and 218-219. For this circult, assume that the strobe slgnal is occurring at a frequency of 100 MHz, has a duty cycle of 50%, and has sufficient amplitude to cleanly swltch the transiator pair 230-232. Strobe signals of either higher or lower frequencies wlll work ~ust as well in other applications, and the duty cycle may be ad~usted to any ratio Aesired.
The input slgnal VIN is applied to the base of translstor ~00 and compared with the reference voltage applied to the base of tran-sistor 201. Although the operating current for co~parator 215-216 ls continuously switched on and off, the comparator behave6 in a conven-- - tional manner in its active state. The ability of the comparator to respond to small input dlfPerences is made posslble by the use of switched posltlve feedback. When ~he operating current i9 suddenly æ o switched f~om transistor 230 to 2329 latch pair 218-219 responds to the signal polarlty at the collectors of translstors 215 and 216 and switches regeneratlvely to the appropriate state. The emitter followers 238 and 240 preven~ the latch pair from saturatiTIg. As mentioned previously, translstors 218 and 219 do not Xave to overcome the ~unction storage time due to the pre-biasing current`through resistor 235, thus switching A time ls minimlzed. In additio:n to ensuring a loglcal 1 or 0 declsion ; for the comparator, the switching of operating current has the effect of sampling the lnpot; that is to say, changes in input VI~, subsequent to :, : .
~ . . :
,, ~ . . ~ . . :
:, : . ~: -t~
stroblng do not effect the co~parator output until the strobe ~lgnal is removed. As discussed previously, a predeten~ined am~unt o hysteresi6 ~ay be designed into the clrcuit by selecting clrcult operatlng param-eters in'accordance with the herelnabove dlscussed equations.
The AND ~ste~ 250 and 252 act ln con~unction wlth the ad~oin-lng comparators to control the operating state of the output emitter followers 265 and 267. For example9 current into either emitter of translstor 250 will develop a voltage across resl6~0r 260 which wlll hold tr~nsistor 265 in ehe off state. It can be di~cerned that if the input signal VIN i6 posltive wlth respect to the reference slgnal at the base of transistor 201, flll of the available co~parator operating current will flow through reslstor 2~6 and into the emitter of tran-~lstor 25Q, leaving no current to flow through reslstor 248. If there is no current flowing into transistor 252 rom the ad~oin~ng comparator, the base of 267 will be pulled po~ltive thrnugh re6i~tor 262, turnlng transi8tor 267 on and placlng logical ones on the encoded output bus lines to which ~he transiRtor emitters are connected.
The circuit herelnabove deacrIbed is of such s~pliclty and consu~es such little power that ln~egratlng 16 comparators on a slngle ~0 chip together with an efficient 4-bit binary encoder has been achieved with a great deal of succea~. Powee consumptlon of a single comparator cell is approximately 32 milliwatts. Resolution ls 4-bits plus over range, and accuracy a~ the lO0 MHz conversion rate i8 8 blts.
In summary, a high speed analog~to-digital converter lncludlng a plurality of parallel connected strobed co~parators and a simplified encoding scheme hns been described~ Each com~arator exhiblts a non-linear transer characteri~tlc to boost the gain when the differential input voltage is n~ar zero, and a predetermined amount of hysteresls in the transfer characterlstic may be introduced to reduce the effects ' . ~ . ' .
.' .... ~ .
- ' :' , D ~ 3 of low level oscillatlon and nolse whlle stlll malntalnlng good gain and resolutlon characteristic3. The comparator output~ are con~ected to a plurality of ~ND gates and thelr associated outpu~ emitter followers, only one of whlch may be enabled at any given tlme, The output emitter followers have multlple emitters which are connected to the output bus in accordance with the data word that the emitter follower reprefients.
It will be obvlous to those Iskllled in the art that many changes may be made in the details of the hereinabove described pre-ferred embodiment of the present inven~ion wlthout departing from the spirit of the invention. For example, two or more of the hereinabove~
described analog-to-dlgital converters may be stacked to provide an expanded N-blt system.
, ...; ~: .
,' ~
.~` . .
,: . `: .
Claims (4)
1. An analog-to-digital converter, comprising:
a reference voltage source providing 2N different discrete voltage levels;
switch means operatively coupled to said reference voltage source for providing 2N-1 complementary digital signals responsive to an analog signal in comparison with said voltage levels, said switch means including 2N-1 comparators connected in parallel, each of said comparators including a first pair of emitter-coupled transistors which operate as a switch responsive to the comparison of an analog signals with one of said discrete voltage levels applied to the respective bases thereof and a second pair of emitter-coupled transistors to operate as a regenerative latching means for reinforcing the complementary digital output therefrom, said second pair of emitter-coupled transistors having a selectable, pre-biasing current source connected to the emitters thereof to pre-bias said second pair of emitter-coupled transistors to a predetermined threshold level;
gate means operatively coupled to said comparators for receiving said complementary digital signals and providing 2N voltage levels, wherein only one of said digital outputs is enabled at a time; and encoding means operatively coupled to said gate means for receiving said digital outputs and producing N-bit data words therefrom wherein a different N-bit data word is provided for each of said 2N discrete voltage levels.
a reference voltage source providing 2N different discrete voltage levels;
switch means operatively coupled to said reference voltage source for providing 2N-1 complementary digital signals responsive to an analog signal in comparison with said voltage levels, said switch means including 2N-1 comparators connected in parallel, each of said comparators including a first pair of emitter-coupled transistors which operate as a switch responsive to the comparison of an analog signals with one of said discrete voltage levels applied to the respective bases thereof and a second pair of emitter-coupled transistors to operate as a regenerative latching means for reinforcing the complementary digital output therefrom, said second pair of emitter-coupled transistors having a selectable, pre-biasing current source connected to the emitters thereof to pre-bias said second pair of emitter-coupled transistors to a predetermined threshold level;
gate means operatively coupled to said comparators for receiving said complementary digital signals and providing 2N voltage levels, wherein only one of said digital outputs is enabled at a time; and encoding means operatively coupled to said gate means for receiving said digital outputs and producing N-bit data words therefrom wherein a different N-bit data word is provided for each of said 2N discrete voltage levels.
2. An analog-to-digital converter in accordance with claim 1 further including a source of strobe signals, wherein each of said comparator circuits includes a switchable current source for supplying operating current to said first and second pairs of emitter-coupled transistors, said switchable current source being responsive to said strobe signals to switch operating current from one of said pairs of emitter-coupled transistors to the other of said pairs.
3. An analog-to-digital converter in accordance with claim 1 wherein said gate means includes a plurality of transistors, each of said transistors having two emitters, each of which is coupled to the output of adjacent switch means, a base connected to a source of reference voltage and a collector connected to an output terminal, wherein a digital output is produced when both of said emitters are activated by digital signals of the same logic state.
4. An analog-to-digital converter in accordance with claim 3 wherein said encoding means includes 2N emitter follower transistors, the bases of which are connected to the collectors of said gating transistors to receive said digital outputs therefrom, each emitter follower transistor having a plurality of emitters coupled to N-bit output lines in coded fashion wherein each transistor produces an N-bit data word when enabled.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US657,414 | 1976-02-12 | ||
| US65741476A | 1976-04-09 | 1976-04-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1105143A true CA1105143A (en) | 1981-07-14 |
Family
ID=24637079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA267,300A Expired CA1105143A (en) | 1976-02-12 | 1976-12-07 | Parallel analog-to-digital converter |
Country Status (6)
| Country | Link |
|---|---|
| JP (2) | JPS5947497B2 (en) |
| CA (1) | CA1105143A (en) |
| DE (1) | DE2702681B2 (en) |
| FR (1) | FR2341231A1 (en) |
| GB (1) | GB1547918A (en) |
| NL (1) | NL7614244A (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2830304C2 (en) * | 1978-07-10 | 1986-01-16 | Siemens AG, 1000 Berlin und 8000 München | Analog-to-digital converter |
| US4276543A (en) * | 1979-03-19 | 1981-06-30 | Trw Inc. | Monolithic triple diffusion analog to digital converter |
| DE2939990A1 (en) * | 1979-10-02 | 1981-04-16 | Siemens AG, 1000 Berlin und 8000 München | Monolithic integratable A=D converter - has comparators consisting each of differential amplifiers with series connected memory cell and hysteresis control |
| JPS5732128A (en) * | 1980-08-04 | 1982-02-20 | Matsushita Electric Ind Co Ltd | Parallel analog to digital converter |
| JPS5732126A (en) * | 1980-08-04 | 1982-02-20 | Matsushita Electric Ind Co Ltd | Comparator circuit |
| JPS5731226A (en) * | 1980-08-04 | 1982-02-19 | Matsushita Electric Ind Co Ltd | Comparator circuit |
| GB2082411B (en) * | 1980-08-13 | 1985-07-10 | Hitachi Ltd | Parallel comparator and analogue-to-digital converter |
| JPS57106224A (en) * | 1980-12-24 | 1982-07-02 | Hitachi Ltd | Analogue-digital converter device |
| JPS57164618A (en) * | 1981-04-01 | 1982-10-09 | Matsushita Electric Ind Co Ltd | Comparator circuit |
| JPS58145220A (en) * | 1982-02-23 | 1983-08-30 | Nec Corp | Voltage comparison circuit |
| FR2563347B1 (en) * | 1984-04-19 | 1986-06-06 | Thomson Csf | COMPARATOR IMPROVEMENT WITH LOCKING CIRCUIT AND DIGITAL ANALOG CONVERTER USING SUCH COMPARATORS |
| NL8602294A (en) * | 1986-09-11 | 1988-04-05 | Philips Nv | ELECTRONIC CIRCUIT WITH COMPLEMENTARY SIGNALING DATA LINES. |
| US4737766A (en) * | 1986-09-12 | 1988-04-12 | North American Philips Corporation, Signetics Division | Code converter with complementary output voltages |
| DE3773940D1 (en) * | 1987-12-15 | 1991-11-21 | Itt Ind Gmbh Deutsche | SCAN HOLD LEVEL AND THEIR APPLICATION IN PARALLEL A / D CONVERTERS. |
| JPH04170226A (en) * | 1990-11-02 | 1992-06-17 | Nec Ic Microcomput Syst Ltd | A/d converter |
| JP3067903B2 (en) * | 1992-08-20 | 2000-07-24 | 沖電気工業株式会社 | Analog / digital converter |
| JPH08300221A (en) * | 1995-04-28 | 1996-11-19 | Fukutaro Yamazaki | Tap |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IL51176A (en) * | 1976-01-20 | 1978-12-17 | Hughes Aircraft Co | Analog to digital converter utilizing a quantizer network |
-
1976
- 1976-12-07 CA CA267,300A patent/CA1105143A/en not_active Expired
- 1976-12-08 GB GB51186/76A patent/GB1547918A/en not_active Expired
- 1976-12-22 NL NL7614244A patent/NL7614244A/en not_active Application Discontinuation
-
1977
- 1977-01-24 DE DE2702681A patent/DE2702681B2/en not_active Ceased
- 1977-02-09 FR FR7704296A patent/FR2341231A1/en not_active Withdrawn
- 1977-02-10 JP JP52014026A patent/JPS5947497B2/en not_active Expired
-
1983
- 1983-09-14 JP JP58170501A patent/JPS5972226A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE2702681A1 (en) | 1977-08-18 |
| JPS5298456A (en) | 1977-08-18 |
| FR2341231A1 (en) | 1977-09-09 |
| NL7614244A (en) | 1977-08-16 |
| GB1547918A (en) | 1979-06-27 |
| DE2702681B2 (en) | 1979-09-13 |
| JPS6245729B2 (en) | 1987-09-29 |
| JPS5972226A (en) | 1984-04-24 |
| JPS5947497B2 (en) | 1984-11-19 |
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