JPH04170226A - A/d converter - Google Patents

Abstract

PURPOSE:To cut off low level noise to make an output stable by providing hysteresis to a comparator. CONSTITUTION:The hysteresis is provided to each of comparators by providing an input buffer (5A-5(X-1)), a input resistor (6A-6(X-1)) and a feedback resistor (7A-7(X-1)) to each comparators (2A-2(X-1)). Thus, the input voltage at a transit point where a digital signal is changed has a width within 1LSB being a difference between an LTP and an HTP. Thus, even when noise is superimposed at sampling, if the level is within a sum of Vt(2) and 1/2LSB, the same result of conversion as without noise superimposition is obtained at the time of sampling.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an A/D converter, and particularly to an A/D converter such as a parallel comparison type.
/D converter.

[Conventional technology]

Conventionally, parallel comparison type A/D converters have been used for A/D conversion of high-speed signals such as video signals.

FIG. 4 is a block diagram of a parallel comparison type A/D converter showing an example of such a conventional type.

As shown in FIG. 4, the N-bit output A/D converter includes (2N-1) comparators 2A to 2(X-1) each having one input connected to the analog signal input terminal 1.
A reference voltage source (v,
) 3, this reference voltage source 3, and ground, and divides the reference voltage ■□ and sends each voltage to comparators 2A to 2 (
2N series-connected voltage dividing resistors 4A to 4X that are supplied as a comparison voltage to the other input of the comparators 2A to 2 (X-1) and the outputs of the comparators 2A to 2 ( A decoder circuit 8 determines how many of the voltages from the bottom of X-1) have exceeded the divided reference voltage and outputs the result to a binary digital signal output terminal 9.

In such an A/D converter, the (2"-1) comparators 2A to 2(X-1) receive a voltage obtained by dividing the reference voltage ■ by the analog signal and 2N voltage dividing resistors 4A to 4X. are applied, and v n /2'' is applied in order from the lowest comparator 2 (X-1).

3 VR/2 l'", 5 VR/2"'
The reference voltage of... is input. The result is decoded by the decoder circuit 8. In other words, the comparators 2A to 2 (X
-1), and the decoder circuit 8 decodes how many of these outputs from the lowest comparator 2 (X-1) exceed the divided reference voltage. is the A/D conversion result.

[Problem to be solved by the invention]

In the conventional parallel comparison type A/D converter mentioned above, the gain of the comparator used is high, so even if the analog signal of the same level is sampled near the transition of the digital signal, the influence of noise superimposed on the analog signal This has the disadvantage that the exchanged digital signals differ depending on the sampling timing. In particular, when the analog input signal is no signal, the digital pressure may fluctuate due to the influence of noise, resulting in a conversion result as if a low-level AC signal had been input. For example, noise outside the audible band may be superimposed and fall within the audible band due to A/D conversion, causing no-signal noise.

An object of the present invention is to provide an A/D converter that blocks such low-level noise and stabilizes its output.

[Means to solve the problem]

The A/D converter of the present invention includes 2N resistors connected in series between a reference voltage source and ground to divide the reference voltage, and a ( The device includes 2N-1) comparators with hysteresis, and a decoding circuit that decodes the outputs of the (2N-1) comparators and outputs an N-bit digital signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a parallel comparison type A/D showing a first embodiment of the present invention.
FIG. 2 is a block diagram of a converter.

As shown in FIG. 1, in this embodiment, compared to the conventional example described above, the number of terminals connected to the analog input terminal 1 is (2N-1).
comparators 2A to 2 (X-1) and a reference voltage source 3
Input the outputs of (2N-1) voltage dividing resistors 4A to 4 (X-1) connected in series between this reference voltage source 3 and ground, and the comparators 2A to 2 (X-1). The decoder 8 that outputs N bits to the digital output terminal 9 is the same, and the other input of the comparators 2A to 2 (X-1) is connected from the node of the voltage dividing resistor to the buffers 5A to 5 (]-1) and the input resistor 6A. ~6(X-1), and a feedback resistor 7A~7 to the other input of each comparator, respectively.
The difference is that (X-1) is connected.

First, the analog signal to be converted is input from the analog signal input terminal 1 to (2N-1) comparators 2A to 2(X
-1) are all input. Also, the reference voltage source 3 is
The voltage is divided by N resistors 4A to 4X, and the generated voltage is applied to buffers 5A to 5 (X-1) and resistors 6A to 6, respectively.
(X-1) to the other comparator 2A~2(
X-1) is the input signal. This buffer prevents the reference voltage of each comparator generated by dividing the voltage by the resistor from fluctuating due to the feedback current from the output via the input resistor and the feedback resistor. The output signals of all these comparators 2A to 2 (X-1) are connected to feedback resistors 7A to 7 (X
-1), and the comparators 2A to 2 (X-1) are fed back to the inputs through this input resistance and feedback resistance.
The threshold voltage of is expressed by the following equation (1).

However, VOL is the output voltage of the comparator when the output is 0', VOH is the output voltage of the comparator when the output is 1', LTP is the input voltage at which the output changes from 1' to 0, HTP is an input voltage at which the output changes from 0" to "1".

The above-mentioned input resistances 6A to 6 (X-1) and feedback resistance 7A
If ~7(X-1) is selected as an appropriate value, it is possible to have a threshold width within ILSB centered on ILSB, which is the resolution of the A/D converter. Therefore, the decoder circuit 8 can indicate in binary notation how many bits from the bottom of the comparator have exceeded the voltage obtained by dividing the reference voltage.

The conversion characteristics of the parallel comparison type A/D converter when the comparator has hysteresis will be explained below.

FIG. 2 is a conversion characteristic diagram of the A/D converter shown in FIG. 1.

As shown in FIG. 2, the parallel comparison type A/
Taking the operation of a D converter as an example when the input signal is near v t (2), the comparator has hysteresis, so the input voltage at the transition point where the digital signal changes is the difference between LTP and HTP. It has a width within a certain ILSB. Now, assume that the comparator has no hysteresis, and the analog input voltage is % lower than v t (2).
In the case of a DC signal as low as LSB, the conversion result when noise is not superimposed on the signal is a digital signal of "2''.

However, due to the influence of noise, V t
(2), the digital output signal is o 3 +
It becomes i. However, by providing hysteresis to the comparator, even if noise is superimposed during sampling and exceeds V t (2), the digital output signal will not become 3'' unless HTP is exceeded. Even if V
t (2) -! -: If the voltage is within the sum of C and SB, the same conversion result o 2 +1 as when no noise is superimposed during sampling can be obtained.

Similarly, even if the analog signal is higher than V t (2) by about LSB, ÷LSB
For the following noises, the same conversion result can be obtained regardless of the sampling timing.

In short, in this embodiment, comparators 2A to (X-1
), input buffer 5A~5(X-1), input resistance 6A~
6(X-1) and feedback resistors 7A to 7(X-1), the comparator is provided with hysteresis.

FIG. 3 shows a parallel comparison type A/D showing a second embodiment of the present invention.
FIG. 2 is a block diagram of a converter.

As shown in FIG. 3, this embodiment uses voltage dividing resistors 10A to IOX similar to voltage dividing resistors 4A to 4X and switches
(X-1,), and set the reference voltage of each comparator to an appropriate value within -LLSB with respect to the reference voltage at the transition point of a digital signal without normal hysteresis. Voltage dividing resistors 4A to 4X and -! -LSB
A voltage dividing resistor of an appropriate value that is as low as 10A to IO
X is switched according to the output of the comparator. Even when the comparator is apparently given hysteresis as in this embodiment, the same results as in the first embodiment described above can be obtained.

In the above embodiment, for example, in the case of an 8-bit, full-scale 5V A/D converter, ILSB is approximately 20mV.
Therefore, if the noise is within 20 mV, the conversion result will not be affected.

〔Effect of the invention〕

As explained above, the A/D converter of the present invention has the effect of being resistant to noise and stabilizing the digital output signal by providing the comparator with hysteresis.

[Brief explanation of drawings]

FIG. 1 shows a parallel comparison type A/D showing a first embodiment of the present invention.
A block diagram of the converter, FIG. 2 is a conversion characteristic diagram of the A/D converter shown in FIG. 1, and FIG. 3 is a parallel comparison type A/D converter showing the second embodiment of the present invention. Block diagram of
FIG. 4 is a block diagram of a parallel comparison type A/D converter showing a conventional example. 1...Analog signal input terminal, 2A~2 (X
-1)...Comparator, 3...Reference voltage source, 4A to 4X, IOA to IOX...Voltage dividing resistor, 5A to 5(X-1)... Buffer, 6A~6(
X-1)...Input resistance, 7A~7(X-1)・
...Feedback resistor, 8...Decoder circuit, 9
・・・・・・Digital signal output terminal, IIA~11(X
-1)...Switch. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] 1. 2^N resistors connected in series between a reference voltage source and ground to divide the reference voltage, and a resistor for comparing the voltage divided by the resistors and the voltage of the analog signal, respectively. (
2^N-1) comparators having hysteresis; and a decoding circuit that decodes the outputs of the (2^N-1) comparators and outputs an N-bit digital signal. A/D converter. 2. The A/C according to claim 1, wherein the comparator for comparing the analog signal and the divided voltage has means for controlling the divided voltage by its output.
D converter. 3.Claim 1, wherein two sets of (2^N-1) resistors are connected in series between the reference voltage source and the ground, and the resistors are switched and supplied to the comparator via a switch means. The A/D converter described.