CA1096465A - Pulse generator - Google Patents

Abstract

PULSE GENERATOR ABSTRACT OF THE DISCLOSURE A pulse generator for producing two output pulse trains A and B where the total number of pulses in both train A and B over a fixed time period remains a constant. The two pulse trains axe derived from a master clock which gates a plurality of cascade connected synchronous decade rate multipliers. A selector is set either statically or dynamically to the value N where N is the number of pulses desired in one pulse train out of every M pulses produced by the master clock. A summing means is coupled to all the multipliers to produce a first intermediate pulse train with N pulses for every M clock pulses. A difference means is coupled to each multiplier and to the master clock to produce a pulse in a second intermediate pulse train every time a clock pulse occurs and a pulse in the first pulse train does not occur. A pulse counter is coupled to each intermediate pulse train output to produce two output pulse trains A and B each having a substantially constant pulse frequency.

Description

BACKGROUND OF THE INVENTION

The invention relates broadly to th~ fie~ld of pulse generators and particularly to a generator for producing two pulse trains where the sum o~ ~he pulses in both pulse ~ra:LnS over a given period o~ tim2 is a constan~.
The invention is particularly adapted for use in a liquid chromatograph although it may be used in ~thex devices where one desires to control the percent of component A in a two component solution wh~re the s~lm o the two components in a given ~vlume is a constan~ i.e., the % A in A + B equals a con~tant. In a liquid chromatograph, the invention has particular applioation in controlling the flow rate of two so~ven~s where it is ~esired to main~ain the total flow o~ the two sol~ents constant while permi~ting precise control of the percent of one sol~ent in the mixture.
In the prior art, variou~ devices have been devel~ped ~or producing a constant total 10w while controlling the flow rate of two constltuents. One approach relies OIl first starting two pumps and analyzing the mix~d output solution from both pump~ to de~ermine the concent~ation of each component. Thereafte~, the rate of at lea~t one pump is adjusted to thereby change the concentration of one fluid component. O~h~r apparatus is provided to ~aintain the sum of fluid ~low through the two pumps at a constantO This apparatus is ~uite complicated be~ause it relies on dynamic ~eedback to control fluid flvw ~hrough the pumps and other con~-rols to maintain total flow at a constant.
Other approaches have been trisd in other device~ or - maintai~ing the total flow of two fluids at a constant rate while permitting the percent of OnQ fluid in the total to be controlled.
.~ One such approach i~ de~cribed in U~SO Patent No. 3,398,689. In 3G the apparatus of that patent, the speed ~f two motor~ wh:ich power two pump~ is controlled by an el~ctrical circuit with the ~ontrol ~ignal~ being derived from a pxogramming me~hanism. The programmi~g

2 - ~

mechanlsm comprises a set oE potentiometers who~e w.ipers are connec~ed in sequence to voltage controlled oscill2tor~, the first oscillatox p.roduces pulses at a maXiMum rate, whi:Le the s~cond oscillatvr produces pulses at a minimum rate~ both in response to a maximum wiper voltag~. The secolld oscillator produces pulses at a maxim~ rate and the first oscillator produces pulses at a minimum rate in respon~e to a minimum potentiometer wiper voltage. The oscillator pulses drive the pump motors at a speed proportional to the pulse rate.
While the approach described in the above mentioned patent generally functions well, it does suffer from many problems typica~ to analog sy~tems, i.e., the apparatus has reso.Lution, drift and linearity problems. Indeed, many of the problems are directly attributable to the fact that two independent voltage controlled oscillators are used each to produce a signal f~r driving one of the pump motors. Since the oscillators are independent circuits, the output frequency of each is difficult to prec~e~ycontrol and they cannot be precisely synchronized with each other. Hence, the pumps controlled thereby do not necessarily maintain the same total flow when the speed of each is changed.
In the above mentioned~patent, large changes in total flow rate are accompli~hed by changing gears located between the drive motors an~ the pumps. Accordingly~ there i~ a considerable period o time, expense and inconvenience required to convert the patented apparatu~ to op~rate a~ a different total flow rate.
~ynamic total flow rate change is impossible to achieve with this device Accordingly, it is a principal object of the invention to pro~ide a pulse generator for control of two pumps or the like which is simpla in design and does not suffer from linearity, drift or resolution problems.

~ 3 --It is another object o.~ the invention to provide a pul~e generator or control.~in~ the total number of pulses in two pulse trains over a ixed period of ~ime wherei.n the total number of pulses is more accurately maintained then by prior analoy controllers.
It is still another objec~. of the invenltion to provi~e a pulse ~enera-tor for dynamlcally controlling ~he to~al numbex of pulses pxoduced in two pulse trains over a fixed period of time while also mai~taining dynamic control over the pulse rate oE
each pulse train.
It is still a ~ur~her object of the invention to provide a pulse generator useful fox controlling two pumps wherein the total flow from both pumps is a dynamically selectable constant and the percent of fluid pumped by one of the pumps in the total flow is directly and dynamically adjustable.
It is sti.ll a further objective of the invention to provide a pulse generator for finsly controlling the flow rate o two pumps so tha~ the combined flow r~te of both pumps is a selectable : .
constant which can be duplicated with different systems reyardless of operating charactexistic differences be~ween the nomimally identical pumps o the differen~ system~ which usually arises from physical diferences therebetween.
~RIEF DESCRIPTION
The invention includes a master clock for producing a pulse train at a selectable rate which, for an illustrative application of the invention, is proportional o the total flow rate of two fluids. The oscilla~or pulses are coupled ~o a plurality of synchronous decade rate multipliexs connected in cascade.
Each of the multipliers couples to a selector means to control the operation of each multiplier so that it produces M pulses, corresponding to the number set into the coupled selec~or means, : for evexy 10 pulses input thereto while the rate multiplier i5 enabled. A summing cirucit responds to all the multipliers to pxoduce a first intermedia-te pulse -train which corresponds to one pulse for each pulse produced by all the rate multipliers.
A diFference circuit, responsive to the master clock and ~o all the rate multipliers, produGes a second inte~media~e pulse train where a pulse i9 produced each time a master clock pulse occurs and a pulse does not occur in the first intermediate pulse txain.
Each intermediate pulse ~rain passes through a pulse counker to obtain a more spectrally pure output pulse train. The to~al ;~
number of pulses in both output pulse trains over a fixed time period is a constant and the nu~ber o pulses in one output ~ -pulse train over the fixed time period is selectable by adjusting the selector means. For the later illustrated application of the invention, a pump responds to each output pulse train to pump a fluid at a rate propoxtional to the rate of pulses coupled khereto. Accordingly, the flow rate of each fluid is sel~ckable within the constraint that the total flow of both fluids must remain a constant.
BRIEF DESCRIPTION OF THE l:~RAWI2~GS
The foregoing objects, advantages and features of the inve~tion shall be described in greater detail below in connection with the drawings which show an illu~rative application of the invention wherein:
Fig. 1 is a block diayram of the new pulse generator coupled to two pumps for pumping two fluids at a constant tokal ~low rate while controlling the constituenk percentage;
Fig. 2 is a detailed circuit diagram of the n~w pulse generator;
Fig. 3 shows how Figs. 3A and 3B are positioned to form a

3~ pulse diagram;
Fig. 3A and 3B comprise a pulse diagram fox repr~sentative pins in the circuit of Fig. 2; and Fig. ~ is a circuit dia~ram for the summing circuit oE Fig. 2;
Fig. 5 is a block cliagram of a pulse generator of -the type shown in Fig. 1 additionally including circuit:ry to ad~ust the flow rate of each pump to compellsate for slight physical differences b~tween the pumps.
D~TATLED DESCRIPTION
Re~erring ~irst to the block diagram of Fig~ 1, an illustrative application of the invention is shown wherein an external pulse generator (not shown~ supplies pulses on a line 10 which are converted into two output pul~e trains A and B on output lines 12 and 14. These output pulse trains A and B respectively control pumps A and B for pumping ~luid A and B respectively through conduiis 16 and 18 wh.ich merge in~o a single conduit 20 where the flow rate of each pump is controlled by the frequency of pulses in the pulse train coupled thereto. In accordance with the principal of operation o the cîrcuit in Fig. 1, the total flow rate of fluids A and B in conduit 20 is controlled by khe rate of pulses input to the cixucit at line 10. ~he percent of fluid A in the total fluid in conduit 20 is controlled directly by the setting o~ a selector, indicated generally at 22 which s~lects the number of pulses app*aring in pulse train A and B o~er a fixed period of time.
The electronic circuitry of Fig. 1 includes thr e cascade connected decade xate multipliers 24, 26 and ~8. Coupled respectively to these decade rate multipliers 24, 26 and 28 are three digit switches 30, 32 and 34 which are operative to produce a unique signal, transmittedto the decade rate multiplier coupled thex~to~ r~presentative of the digit to whi~h each respective digit switch YS set ana the set digits are rela~ed to the percent o fluid A in the flow of fluids A and B. In the illustrati~e embodiment of the invention, each digit switch 30, 32 and 34 is operative to produce a un.ique signal or each possible decimal :~

~igit between zero and nine to which thc switch may he selcctively set. Accordingly, the digit switches 30, 32 and 34 can be set to a number rangin~ from 0 to 999. For the embodiment shown, if the decimal number in the selector 22 i9 divided by 10, ~he result.ing numbe~r corresponcls identicalLy to ~he percentage of fluid A in the -to~al ~luid flowing in conduit 20.
Alternatively, the sele~tor switches 30, 32 and 34 can be replaced by a selector means responsive to an external condition or conditions to dynamically alter the unique signals coupled to the decade rate multipliers 24, 26 ana 28. For example~ the selector means may include one or mo~e analog to dicJital converters for dynamically converting an ex~ernal an~log condition in~o a digital number whose magnitude is equivalent thereto. Alternatively, the selector means may comprise one or mor~ digital cotmters ox any other means producing a digital number. In this manner, the pulse generator can be made to produce a different number of pulses in each output pulse ~rain over a given ~ime period in response to dynamically changing conditions.
Each decade rate multiplier 24, 26 and 28 is operatively connected to receive pulses appearing on line 10 and respec~ively coupled to the digit switches 30t 32 and 34. ~ach decade rate multiplier 24, 26 and 28 is operative to respectively place on its output 36, 38 and 40 the same number of pulses as indicated by the settin~ of the coupled digit switch 30, 32 or 34 for each-ten clock pulses appearing on line 10 for which the particular decade rate multiplier 24, 26 or 28 is enabled. By reason of the enablin~
circuitry, which will be d~scrihed hereinafter in greater detail, the decade rate multiplier 24 is enabled during every clock cycle for the signal on line 10 where the time between the beginning of two successive pulses comprises a clock cycle, rate multiplier 26 is enabled ~or only one clock cycle for every 10 clock cycl~s appearing on line 10 and the decade rate multiplier 28 is enabled for only one clock cycle for every 100 clock cycles appearing on ~3~

line 10. Accordingly, when each of the digi-t switches 30, 32 and 34 is set to a fiv~, the following pulse ~trings ~xe produc~d.
For every ten pulses appearing on line 10, the decade rate multipl.ier 24 produc~s five pulses on its ou~put line 3~. For every 10~
pulses on line .10, decade rate mul~iplie.r 26 produce3 5 pulses on its output line 38. For every 1000 pulse~ on l~ne 10, decade rate multiplier 2~ produces 5 pulse~ on its ou~put line 40.
Thus, for every lOOQ pulses on line 10, a tot,al of 555 pulse~ are produced on these output lines 36, 38 and 40.
The decade rat~ multiplier 24 transmits enahling informa~ion on line 42 to the nex~ casc~de coupled data rate multiplier 26.
The enabling i~orma~ion on li~e 42 is operative ~o enable the decade rate multiplier 26 to operate during one clock cycle out of every 10 clock cycles appear~ng on line 10. As will become clearer later, the cycle duriny which the decacle rate multiplier 26 is enabled corresponds to a cycle when the decade rate multiplier 24 never produces a pulse on its outpu~ 36.
The decade rate multiplier 26 re~ponds to the setting of the digit switch 32 to produce a corresponding number of pulse~ on its output line 38 or every ten pulses that it is enabled.
Accordingly, when the digit switch 32 i5 se~ to a five, five pulses appear on the outpu~ line 38 for eYery ten clock pulses input to khe de~ade rate multiplier 26 while i~ is enahled, Therefore, thP five pulses appearing at output line 3~ occux ov~r a period when one hundred clock pulses occur at line 10.
Enabling information is transmitted from the decade rate multiplier 26 via the line 44 to contxol the operation of the next cascade coupled decade rate multiplier 28. The decade rate :
multiplier 28 xesponds to the enabling and da~a informatiorl so 30 as to produc:e a number of puls~s on it:5 output line 40 coxresponding to the setting of the digit switch 34 for ev~ry ten pu:Lses that the decade rate multiplier 28 is enabled~ The enabling circuitry~

as will be clescr.ibed hereina~ter in greater d~tail, in decade xate multiplier 26 produces an enablin~ pul~e which enables decade rate multiplier 28 to ope.rate duri.ng only one clock cycle appearing at line 10 out of every 100 clock cycles. As will become clearer, the decade rate multiplier 28 is enable~ at a time when nei-ther decade rate multipller 24 ox 26 produces An output pulse. Accordingly, when the dîgi~ switch 34 is set to a five, the decade rate multiplier 28 produces five pulses on its output line 40 over a period of time corresponding to 1,G00 pulses at line 10.
The circuitxy of Fig. 1 includes a summing circuit to produce a pulse on the summing circuit output line 46 whenever a pulse appears on any o the decade rate multiplier output lines 36, 38 or 40. The summing ci~cuit is internal to each of the decade rate multipliers 24, 26 and 28. As part of the summing circuit, khe pulses transmitted over line 36 are transmitted to deGade rate multiplier ~6. ~nternal to the decade ra~e multiplier 26 is circuitry responsive to the pulses on line 36 and 38 o produce a pulse on line ~5 during each clock cycle that a pulse appears at either output line 36 or 38. Internal to the decade rate multiplier 28 is circuitry responsive to pulses on line 45 and 40 to produce a ~ixst intermediate pulse train with a pulse on line 46 during each clock cy~le ~hat a pulse appears on line 45 or line 40, i.e.~ a pulse appears on line 46 during each clock cycle that a pulse appears on either line 36, 38 or 40 and for every 1000 pulses on line 10, N pulses appear on line 46 where N is the number set onto switches 30, 32 and 34. One circuit for accomplishing this su~ming unction ~s described later in connection with Fig. 4~
The circuitry o Fig. 1 al`~o includes a difference circuit 48 responsiveto ~he clock pulses on line 10 a~d to the pulses appearing at the outputs 36, 38 and 40. The difference circuit 48 is operati~e to produce a second intermediate pulse t:rain with a pulse at its outpu~ e 50 during each clock c~cle for the g _ -pulses on line 10 when no pulse appears on ally of the vutput lines 36, 38 or ~0. ~ccordinclly; for every l.,000 pu19~s appearinCJ
on line 10, (1,000 - N~ pulses appear on line 50 where N is -the nwmber to which -thc switches :30, 32 and 34 are set.
Coupled to the output line ~ .is a counter 52 which is opera-tive to procluce an output pulse train on lin~ 12 whexein the time between pulses is substantially constan~ even though the time between pulses on line 46 is not constallt. This is accomplished by a pulse counter which, Eor the illustrated embodiment of Fig.
1 is operative to place one~pulse on t~e line 12 for every 100 pulses appearing on line 46.
Similarly, a.counter 54 is coupled to the output line 50 from the difference circuit 48 and comprises, for the illustrated embodiment, a pulse counter which places a pulse at its output 14 or every 100 pulses appearing on line 50. Accordingly, the output pulse train on line 14 has a substantially constant time period between pulses.
By reason of the counting and the summing and difference operations performed by the circuitry of Fig. 1, the frequency of N

pulses appearing at line 12 is equal to 1OOO x f where the input frequency at line 10 is lOOf. The frequency of the signal ap~earing at line 14, on the other hand, is equal to (1 - lOOO)f.
The pulse train appearing at line 12 is coupled by a stepper driver 56 to a steppin~ motor 58 which drives ~mp A. The stepper m~

ariver 56 converts the pulse s.ignal appearing a~ line 12 into a signal suitable for dxiving -the stepping motor 58. The steppin~
motor 58 itself responds to the signals from the stepper dri~er .5~ t~ drive the pump at a speed ~hich is proportional to the fre~uency of the pulse signal appearing at line 12. This causes pump A to pump fluid A at a rate proportional to the frequency of the pulse train appearing on line 12. In ~ sim.ilar manner, the pulses at line 14 are converted by a stepper driver 60 which is couplad to ~ stepp.in~ motor 6~ which powers pump n. Pump ~, however, operates at a spe~d wh.ich i5 proportional to the E.requ~ncy of the pulse train appearin~ on line 14. Since -the number of pulses appearing at lines 12 and 14 over a gi~en time per.iod is a constant/ the rate of flow of fluid ~ and fluid B over the sam~ p~riod o.f time is also a constant. ~ccor.dingly/ the circuitry of Fig. 1 is ~erative to con-trol the total 10w of fluids A and B in conduit 20 while selec~ing the percentaye of each fluid in ~he total by setting the selector means 220 Fig. 2 is an exemplary circuit diagram for the electron c circuitry shown in the block diagram o~ Fig. 1. The circuitry of Fig~ 2 includes an adjustable clock pulse generator 100 for producing a square wave signal at its output 102 having a fre-quency of lOOf. This square wave signal is coupled to the clock p~n 9 of three decade rate mul pliers 104, 106 and 108. In the embodiment shown in Fig. 2, ~hese decade rate multipliers 104, 106 and 108 each comprise a Texas Instruments SN74167 synchronous decade rate multiplier. Other synchronous decade rate multiplier circui~ types are a~ailable and they may be substituted~ with appropriate wiring modification, into the circuit of Fig. 2. Switches 1, 2 and 3 are respectively coupled to the decade rate multipliers 104, 106 and 108 and produce, in cooperation with the resistors and power supply coupled thereto, a binary coded signal at ~he input pins 2, 3, 14 and 15 of each rate multiplier 104, 106 and 108 which corresponds to the decimal digit to which the switch is set. Each switch 1, 2 or 3 is opPrative along with ths coupled re~istors and power supply to ~èlect a decimal digit from between zero and nine and it places a cor~e~ponding binary coded decimal si~nal pattern9 repxesentative of either a logic 1 or 0, onto the input pins ~; 3, 14 and 15 o the coupl~d rate multiplier which is utili~ed thereby to produ~e a corresponding number of pulses at its output pin 5 for every ten p~slses appearing at its input pin 9 at times when thc xate multipl.ier is enabled by a logic 0 ~low~ signal on pin 11. For rate multipliex 10~, the signal at pin 6 equals ~ .
Figs~ 3A and 3B show a pulse dia~xam for various pins in the 3 cascaded decimal xate multipliers 104, 106, and 10~ o Fig. 2.
O par~icular interest, however, is the ou~put at pin 5 of decimal rate multiplier 104 which is a function of thle setting for digit switch 1. As viewed in Fig. 3A, th2 pulse tr,ain la~elled clock is applied to pin 9 of the rate multiplier 104. When switch 1 is ~et to zero ~ no pulses appear at the output pin 5.
On the other hand, if the digit switch i5 s~t to any o her number ~etween zero and nine, the output pulse pattern at pin 6 i~ shown or each possible digit to which switch 1 can ~e ~et. For exampla, when digit switch 1 is set to a one, one pulse occurs at the output pin 6 for every ten pul~es appearing at pin 9 while the rate multipliex 104 is enabled. Since pins 4, 8, 10, 11 and 13 are always held at ground potenti~l5 the rate multiplier 104, in accordance with the operation or tha Texas Instruments SN741S7, is continually enabled. Therefore, one pulse appears at pin 6 ~0 ~or e~ery 10 appearing at pin g and it appears during the 4th clock cycle out of every 10 clock cycles~
On the other hand, when switch 1 is sek to ~ive, for example, ive pulses appear at output pin 6 fs:~r every 10 pulses input to ~:
pin 9. Consequently, the setting o swit~h 1 defines the number of pulses appearing at pin 5 for every ten pul~es input to pin 9 of rate multiplier 104.
It should be noted that the specified decade rate multiplier 104 never produces an output pul~e at pin 6 during each ninth clock cycle out of 10 clock cycle~ appearing at pin 9. This a~pect o~ the specified modul~ is exploited by the cascade coniguration of Fig. 2 in that the enable signal, appearing at pin 7 of decade rate multiplier 104 goes to ground potential only during the ninth clock cycle during which decade rate multiplier 104 is enablPd. Accordin~Jly, clecade rate multiplier 106 i~
enabled by ~he qrowld connection at pillS 10 a:nd 11 every ninth clock cycle out o~ ~en appearing at decade rate multiplier 104.
As such, a pu:lsa may ~e produced at pin 5 of clecade rate multiplier 106 only during one clock cycle out of every ~en or which the decada ra~e multipli.er 104 is enabled~
The decade rate multiplier 106 responds to the setting of switch 2 by pro~ucing a corresponding llumber of pulse9 at its output pin 5 for ev~ry ten pulses appearing at pin 9 while pins 10 and 11 are at ground potential. In other words, a pulse may appear at pin S of d~ade ratP multiplier 106 during the n:inth, nineteenth, the twenty-ninth etc. clock cycles of the signal appearing at pin 9 of the decade rate multiplier 104.
Since decade rate multiplier 106 is ~he same ci~cuit type as that for decade rate multiplier 104, it functionally operates in the same manner and, therefore, if switch 2 is set to a five, a pulse is produced at pin 5 of decade rata multiplier 106 durin~
the ninth clock cycle. Other pulses are produced at pin 5 of decimal rate multiplier 106 during ~lock cycles 29, 39, 59 and 79 so that out v 100 pulses appearing at pin 9 of rate multiplie.r 106, fi.ve pulses are produced at its output pin 5. I digit switch 2 were set to another ~alue, a corrasponding number of pulses would b~ produced at output pin S of the decade rate multiplier 106 for ever~ 100 clock cycles on line 102.
By reason of circuitry internal to the decade rate multiplier 106, the o~put ~ignal from pin 5 of decade rate multiplier 104 which couples to pin 1~ of rate multiplier 106 al50 appears at pin 6 of decade rate multiplier 106 NANDed with the OlltpU`t pulses appearing at pin 5 of the decade rate multiplier 106. These pulses are inve~ted by an i.nverter 110 whose output forms the input to pin 12 of the decade rate multiplier 108. As such, a pu:Lse appeaxs

4~
at pin 12 at decade rate multiplier 108 du.ring every cloGk cycle that a pulse appears at pin 5 o either decade rate multiplier 10~ or ln~.
By rPason of the fac~ that the enable output 7 of the decade ra-te multipli.ex 106 is coupled to pins 10 and 11 o;E the decade rate multipller 108, the decade rate multiplier 108 i9 enabled by the preceedin~ decade ~ate multip~ier 106 during the a9th clock period, as indicated in Fig. 3B. Consequently, the decade rate multiplier 108 is enabled during one clock cycle out of every one hundred cloc}; cycles at its clock input pin 9. ~ decade rate multiplier 108 is al50 enabled, although not indicated in Figs.
3A or 3B during clock periods 189, 289J 389, etcO As suc:h, decade rate multipli~r 108 produces the number of pulses identiied by the digit in switch 3 at its output pin 5 for every 1,000 pulse~
input to p.in 9 thereof~
By reason of circuitry internal to decade rate multiplier 108, the input pulses appearing at pin 12 are ~ANDed with the ~:
pulses appearing at pin 5 so that a pulse appears at pin 6 of decade rate multiplier 108 duriny evexy clock cycle that a pulse :
is generated at pin 5 of either decade rate multiplier lC4, 106 or 108. Therefore, the pulse pattern appearing at pin 6 of de~ade rate multiplier 108 compr ses a first intermediate pulse train with the num~er of pulse~ over 1000 clock cy~les at line 112 which coveritSto equalling the sum of the pulses appearing at output pin 5 of each decade rate multiplier 104, 106 and 108. A
:~ diagram for the summing circuitry, both internal and external to the modules 104, 106 and 108, is shown in detail in Fig. 2~
An alternative thereko, however, is simply a 3 input N~ND gate coupled to output pin 5 of each decade rate multiplier 104, 10 and 108 where the NAND gate output connects to inpu~ n l o~
counter 114. The output line 112 is disconnected.
In opera~ion, the circuitry described so far is operative to produce a irst interme~ te pulse train with N pulses on the line ~12 for every 1,000 pulses appe~ring on linc 10~ where N iS
a decimal number having three dig:its Nl, N2 and N3 and switches 1, 2 and 3 are raspectively set to values Nlr N2, arld N3. This ~irst intermediate pulse train is coupled to tlle inpu-t of a ~ulse counter 114 whose function is described below in ~reater detail.
Referring again to Fig. 2, a di~ference circu.it sllown within dotted line 116 couples to the clock pulse generator and the output signals appeari~g at pin 5 of each decade rate multiplier 104, 106 and 108. The difference circui~ 116 has an inverter 118 for inverting the clock pulses on line 10~ thereby producing an inverted clock pulse signal on line 120 which forms one input to a NAND gate 122. The other three înputs to NAND gate 122 couple directly to output pin 5 from each decade rate multiplier 104, 106 and 108. The output of the NAND at 122 is inverted by an inverter 124 and coupled to a line 126 to a pulse counter 128 whsse function is described below in greater detail.
Functionally a puls~ is produced on the line 126 duxing every clock cycle ~hat a pulse does not appear at any output pin 5 from either decade rate multiplier 104, 106 or 108. As such, for every 1,000 pulses appearing on line 102 from the clock pulse generator 100, 1,000 pulses are produced on the lines 112 and 126 with N pulses appearing vn line 112 and (1,000 - N) pulses appearing on line 126. Add~tionally, the puises appearing on line 112 always occur during different clock cycles than th~ clock c~cles durin~ whi~h pulses appear on line 126.
The pulse counters 114 and 128 eac:h comprise a spectral purif.ication means to produce a single pulse al: their output for every 100 pulses appearing at their inputO For the~ }~articular embodiment ~hown in Fig~ 2, each counter is comprised of ~wo d~cade divide cixcuits connected in cascade where each divid~r cir~it comprises a Texas Instruments SN7490 although other equivcllent ;fl~

c.ircuit types may be substituted there:Eor~ Each p~l5e coun~er 114 or 128 may also compri~e any other circuit for dividing ~he n~ber of pulses input thereto by a given number. ~s ~uch, when the inpu~ requency on line 102 is ~qual to QE, the frequency of pulses appearing at the line labelled f~ no x ~ x f. l'he frequency o~ pulse~ ~ppearing at the line labelled fB i~ OOO) X f. Ac~ordingly, the sum of pUlSQS appearing on the li~es labelled f~ and B is a cDnst~nt over a given period time and directly related to the requency of the clock pulse generator 100.
The number of pulses appearin~ at the line labelled fA over the fixed time period, however, is selected by the setting of the three swit~he~ 30, 3~ and 34 respectively to the value of Nl, N2 ~nd N3 Should greater ~requency stability be desired, however, a thixd divide by ten circuit can couple in ca~cade with the other two counters 114 or 128 so as to divide the incoming pulse train by 1,000. To achieve the same pulse rate at the output of the cou~ters 114 or 128 where it divides the input by 1,000, the pulse rate of the clock pulse generator 100 must be increased to equal l,OOOf. Gxeater output frequency stabllity can be achieved by adding still more division skeps to each oountex 114 and 128.
Should further resolution of the n~ber N be desired, further decade rate multipliers can be coupled in cascade ~o those ~hown in Fig. 2 and these further decade rate multipliers would be coupled into the remainder of the circuitry in a manner substan~ially identical to that shown for the decade rate multipli.ers in ~ig. 2. In this manner, i one furthe~ decade rate multiplier were included, the number N would comprise a four decimal digit number and the rate of pulses appearing at the output line labelled N

fA would be 1~0 ooo-~ where the frequency of pulses from the clock pulse generator 100 is lOOf and the pulse rate on line 126 would r~
be (1 10,0003f-w 16 -From the forego.in~ descr.iption, it i5 evident that the ci.r~
cuitry of Fig. 2 is operative to produce two output pulse trains at lines labellecl -~A and ~ whe.re the percen-t o pulses in pul~e train A as compared to the numbex o:E pulses i,n hoth pulse traill A and ~ o~er a fixed time period is conkrolled by th~ number N .in the selector means comprisin~ switches 1, 2 and 3. The -total number of pulses in pulse ~rain A and B over a fixed time period is controlled by the pulse rate of genera~or 100 and hy the pulse count~rs 114 and 128. For the illustrative embodiment oE the . .
invention, thereEore, the total flow rate of fluid A and B is controlled ~y the frequency of clock pulses from generator 100 and the percentage of each constituent (fluid A and fluid B) in the tQtal ~low of both fluid A and B is con~rolled by the number.N.
While the oregoing description has emphas.i2ed an exemplary embodiment of the invention, those of skill in the art will recognize o~hex applica~ions for the new two component pulse rate synthesizer. In additiont alternative circuit configuxations for implementing the described func~ion ~ speci~ic circuit elements ~ill readily occur to skilled circuit designers. Fox example, the BCD digital rate multipliers speci~ied above may be replaced by binary rate multiplier circuits. The selector mean-~associated with such binary rate multiplier must be compatihle therewith 9 The output pulse train produced by this alternative configuxation has a conskant number of pulses produced over a given time period with the proportion in each of two pulse trains being selectable.
It should be no-~ed that pumps such as pump A and pump B o Fig. 1 are requently of the same type and nominally pump fluid theret.hrough ak khe same rate when ~riven at khe ~ame speed~
As such pumps are mechanical devices, the tolerances to which they can be manufactured does in actuality cause one pump tv pump 1uids at a sligh~ly diEferent rate than another pump even when driven at the same speed~ As such, the collfig~lration of E'ig. 1 may not produce -the s~me flow of fluicl ~ and fluid B.
Fi~. S shows al~ernative em~diment of the present invention which include~ circui~ry or changing the rate o:~ pul~es applied to the stepper driver circuits 56 and 60 -thereby caus.ing the respectively coupl~d s-tepping motor 58 and 62 to rotate at a slightly different speed than is achieved by t:he circuit of Fig.
1 thus causing ~he respecti~el~ coupled pump }~ and pump B to pump at a dif~erent rate than or the circuit of E'ig. 1~ The capability to modify the individual flow rate for the two pumps permits the.circuit of Fig. 5 tG maintain a truly constant total flow rate of two fluids while selecti~ely being able ~o ~e~ the flow rate of one such fluid~
The circuitry of Fi~. 1 is modified in ~ig. 5 by breaking the output line 46 between the decade rate multiplier 28 and the digital counter 52 and inserting a decade rate multiplier 200 (similar to circuits 24 and 26) which is coupled to a selector switch 202 arrangement similar to switches 30 and 320 The outpu~
of the decade rate multiplier 200 is coupled by an ou~.put wire 204 to the digi~al counter 52. In a similar manner, the output line 50 betw~en the diEference circuit 48 and the digital counter 54 is broken and coupled to the input of yet another decade rate multipliex 206 which is coupled to a selector switch 208. The output of the decade rate multiplier is coupled by an output wixe 210 to the input of the digital counter 54.
The function of the additional decade ra~e multipliers 200 and 206 is to modify the pulse string which i5 coupled to .~ach digital counter 52 and 54. Assuming for the ~ment that the decade rate multiplier 200 is identical in function to the decade rate multiplier 24, if the switch 202 is set to a di~ital number Y ta digital number between 0 and 9), for ~ery ten pulses appe~ring on the output wire 46 which couples to the decade rate multiplier 200 inpu-t, Y pulses will appear on its output wire 204, Accord ingly, the decade rate mul~ipli~r 200 unctions -to reduce the average pulse rate appearing at the output of co~ ter 5~. In a similar manner, the decade ra-te mult:iplier 206 is operative to reduce the average pulse ra~e of pulses appearin~ at the input to the diyital counter 54.
In the preferred arra~gement of the presen~ invent.ion, howe~er, the decade rate.mult.ipliers ~00 and 206 do not compris~
a single stage decade rate multipliar such as decade rate multiplier 24 but in fact preferrably compris,e two or more cascade connected decade rate multipliers such as for the arrangement shown for decade rate multiplier 24 and 26~ Accord- ~.
ingly, the switches 202 and 208 actually comprise a plurality of decads switches with each switch being coupled to one decade rate multiplier cixcuit such as switch 30 is coupled to decade rate multiplier 24.
Accordingly, if decade rate multiplier 200 comprises two stages and the switch 202 correspondingly has two selecta~le decade switches, the number Y which may be set by the switch 202 oan range from O to 99. The function thereof is to perrnit Y
p~lses to appear on the output wire 204 for every hOO puls~s appearing at its input as coupled thereto by the output wire 46.
The preferred arrangement acco~cling to the pxesent :inve~tion for th~ decade rate multiplier 206 also comprises two ~ascade couplad de~ade rat~ multiplier circuits and the swit~h 208 includ~s two decade switches so that a digital number Z between O and 99 can be selected thereby as wallc Accordingly, for evexy 100 pulses appearing on the output wire 50~ Z pulses appear on the output wire 210 rom the decade rate m~ltiplier 206.
Those of skill in thQ art will readily realize that the abo~e-me~tioned function~ for the decade rate multipliers 200 and 206 and their coupled switch ~ele~tor switches 202 a~d Z08 can be accomplished by circuitry such as for the decade rate multipliers ?~ ~ 2~ and switchgs 30 and 32 wherein ~he input wire corresponds to wire 10 a~d the OUtpllt wire correspond~ to output Lin~ 45.
Other cir~uit conficJurations may also be used to accomplish the desired objective.
In the norma~ operation o~ ~he circu:itxy~ accordin~ to Fig.

5 as oppos~d to the operation oE the circuitry~ accordincJ to E'ig.
1, the frequency of pulses appeariny at the input of tha circuitry of Fig. 5 is preferrably higher than the frequency o pulses appearin~ at ~he input line 10 for the circuit of Fig, 1. The reason for this input ~requency differen~e will become more appaxent rom the following discussion. hssuming that the input frequency for the circuit of Fig. 1 remains lOOf and the input frequency on line 10 for the circui ry of Fit3. 5 is 117.6f. Also assume that the switches 30, 32 and 34 are set to a number N which equals 800. Accoxdingl~, for every 1000 pulses appearing on input line 10 of Fig. 1, 800 pulses will app2ar at the output line 46. For the circuitxy of FigO 5~ the same switches 301 32 and ~4 are set there as for Fig. 1, however, the requency of signals appearing at the output line 46 is increased. Accordingly, in the same time period that 1000 pulses wexe input on line 10 in Fig. 1, a~out 1176 pulses appeared at the input line 10 of Fig. 5.
According to the operation of the circuitry of Fig. 1 which is common to that of ~ig. 5, approximately 940 pulses will appear at ~:
output line 46 during the same time period that 800 puLses appeared at output line 46 of Fig. 1.
Assume fur~her that number Y to which the selector ~witch 202 is set i5 equal to 85. Accordingly, the decade rate multiplier 200 will produce 85 pulses vn its output wire 204 for every 100 pulses at its input from the line 46~ Consequently~ during the time period when 940 pulses appear on output line 46 in Fig. 5 when the switches 30, 32 and 34 are preset as .indicated above, approximately 799 pulses will appear at the output line 204 from J~

the decade rate mu.ltipl.:ier 200. ~ccord~incJl.y, t:he circu.i-try of Fi~. 5 when the frequency on ~he input line 10 i5 raised to 117~6f and the selec-~or switch ~02 is se~ to 85 causes appro.ximate].y the same number of pulses to appear at the input o the digital counter 52 during the same period of time as appear at the input to the d.igit~l counter 5~ for ~he circuit of ]?ig. 1, assuming that the selecto.r switches 30, 32 and 34 of bo~h c:ircuits are set to the same digital value. As such, ~he circuitxy o Fig. 5 can be made to produce the same n~nber of pulses during the same period of time at the input to the digital counter 52.
The same analysis can be applied to the circuitry of Figs.
1 and 5 with respect to tha decade rate multiplier 206. Accordingly, when the decade rate multiplier 206 has its coupled switch 208 set ~o that Z is 85, almost the exact same n~nber of pulses appear at the output line 210 during a given period of time as appear on the output line 50 of Fig. 1, assuming that the selector switches 30, 32 and 34 o~ both circuits are se~ to the s~me.value.
Accordingly, by properly raisîng the frequency of pulses appearing at the input line ~0 of FigO 5 and by selecting the proper digital value ~ and Z for the ~etting of switches 202 and 208 r the circui~ry of Fig. 5 can be made to function substantially identically to the circuitry of Fig. 1.
The circuI~ry of Fig. 5, however, can also be made to increase or decrease the number of pulses appearing during a given period af time at the input to either digital counter 52 or 54 as compared to the number of pulses appearing at ~he input to counters 52 or 54 when ~witches ~00 and ~06 are each set to 85. Assuming for the moment that the selec~or switches 30,32 and 34 remain set to 800 and the input requency at the input line 10 is 117.6f/ i~ the selector switch 202 is set ~o 90, approx lna~ely 846 pu:l.ses will appear a~t the outpu~t line ~04 during the s~ne time period that O0 pulses appeared there when the selector switch 202 was set to 85. As such, by adjustin~ the value of the selector swi.tc~h 202 upwardly from 85, the num~er of pu.Lses appea.r.ing on oUtput line 204 durin~ a given period o~ time is yreater than appear on line 204 when the switch 202 i.s set to 85. As sucht a higher pulses rate appears a~ the inputt the 6tepper driver 56 and 58 in accordance with -the opera-tion of the invention as heretofore descrihed. This causes a corresponding increlase o~ the spaed of pump A thereby increasing the rate o flow of 1uid A throuyh conduit 16.
~y a ~imilar analysis, if the switch 202 is set below 85, the average pulse rate appearing on thc output line 204 is lower than when switch 202 is set to 85 thereby causing a reduction in the pulse rate appearing at the input to the stepper driver 56 which correspondingly causes a reduction in the p~ping rate of pump A. As such, by adjusting the setting of switch 202, tha pumping rate of pump A is somewhat increased or decreased depending on the setting of the switch 202 as compared to the pumping rate achieved ~ the circuitry of Fig. 1 when switches 30, 32 and 34 of both Fig.l and Fig~ 5 are set tc:~h~ same value. This observation, of cours~, assumes that the ~requency o pulses appearin~ at th ~-input line 10 of FigO 5 is greater than the frsquency of pulses appearing on line 10 o Fig. 1. A~s such~ the pumping rate of an individual pump can be slightly modified by the additional circuitry of Fig. 5 thereby p~rmitting the flow xate through the conduits 16 aEd 1~ to be precisely adjustad to compensatio~ for physical differences between pumps A and B so as to assure that the total pumping rate of fluids A and B is always equal to a ~onstant,~
This feature is particularly advantageous, as is readily recognized hy those Q.~ skill in the art, for permitting precise control of :-the combined flow rate of fluids A and B in separate systems or even in one sys~em where a pump must be replaCed by anot:her one having slightly diferent pumping characteristics.

$~

Those of ski].l in the ar~ reacl:ily recogrli~e that the circultry of Fig. 5 may be ;~urt:ller modified from ~hat desc~ibed by, ~or examp.le, permitting the decade rate mul-tiplier6 200 and 206 to have ~.reater than -two s~ages w.i~h a co3-responding increase in -the n~lmber of sta~es for the coupled swi~ches 202 and 208.
By further increasing the number of stages for the decade xate multipl.iers 200 and 20~, mor~ precise adjustmerlt of the pumping rate of the coupled pumps A and B can b~ achlev2d.
The foregoing and other modifications to the circui.try described ahove can be made without departing from the spirit an scope of the invention as defined in the following claims.

Claims (30)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A pulse generator for producing two pulse trains where the sum of pulses in both pulse trains is a constant over a fixed time period and the pulse rate of one train is selectable, the generator comprising, in combination:
a source of clock pulses with one clock pulse occurring per clock cycle;
a plurility of selector means each selectively providing a unique signal representative of a decimal digit correlated to the pulse rate of one pulse train;
a plurality of synchronous decade rate multipliers each coupled to said source of clock pulses and to one selector means to receive unique signals therefrom, said decade rate multipliers being connected in cascade so that the first decade rate multiplier is operative during each clock cycle and capable of producing an output pulse during nine out of every ten clock cycles, each succesive decade rate multiplier is operative during only the one clock cycle that the previous rate multiplier cannot produce an output pulse, each said decade rate multiplier producing X pulses at its output for each ten clock cycles that it is operative where X corresponds to the setting of the selector means coupled thereto;
summing means responsive to the output pulses from each said decade rate multiplier to produce a pulse in a first inter-mediate pulse train for each output pulse from any decade rate multiplier;
difference means responsive to said clock pulses and the output from each said decade rate multiplier to produce a second intermediate pulse train having a pulse whenever a clock pulse occurs in the absence of an output pulse from any said decade rate multiplier; and a first pulse counter responsive to said first intermediate pulse train and a second pulse counter responsive to said second intermediate pulse train, each said pulse counter being operative to produce one output pulse in a pulse train for every N intermediate pulses input thereto, the output of said first: pulse counter comprises a first output pulse train and the output of said second pulse counter comprises a second output pulse train, where N is the whole decimal number.

2. The pulse generator of claim 1 wherein the rate of said source of clock pulses is adjustable so that the constant sum of said two output pulse trains is adjustable.

3. The pulse generator of claim 1 wherein each said selector means includes means to actuate a plurality of output lines to place a binary coded signal thereon corresponding to the digit to which it is set.

4. The pulse generator of claim 1 wherein said difference means comprises, in combination:
a first inverter to invert said clock pulses to produce inverted clock pulses; and a NAND gate responsive to said first inventer and to the output pulses from each said decade rate multiplier to produce output pulses comprising the inverse of said second intermediate pulse train.

5. The pulse generator of claim 1 additionally including pump means responsive to said first output pulse train to pump a first fluid at a rate correlated to the frequency of pulses in said first output pulse train and including means responsive to said second output pulse train to pump a second fluid at a rate correlated to the frequency of pulses in said second output pulse train.

6. A control circuit for controlling the rate of flow of two fluids so that the total rate of flow of the two fluids is a constant while the ratio of one fluid flow rate to the other is adjustable, the control circuit comprising, in combination:
a pulse generator producing clock pulses at an adjustable rate wherein the clock pulse rate is correlated to the total flow rate of the two fluids;
selector means for producing signals representative of a plurality of decimal digits correlated to the flow rate of one fluid;
a plurality of synchronous decade rate multipliers connected in cascade and responsive to said pulse generator and said selector means, each decade rate multiplier producing output pulses correlated to the signals representative of one said decimal digit;
summing means responsive to each output from each said decade rate multiplier to produce a first intermediate pulse train with one pulse for each pulse input to said summing means;
difference means responsive to said clock pulses and each said decade rate multiplier to produce a second intermediate pulse train having a pulse occurring at the time each clock pulse occurs in the absence of an output pulse from any said rate multiplier;
first spectral purifying means to produce one pulse in a first train of output pulses for every N pulses in said first intermediate pulse train where N is a whole decimal number;
second spectral purifying means to produce one pulse in a second train of output pulses for every N pulses in said second intermediate pulse train;

first pump means responsive to said first train of output pulses to pump a first fluid at a rate proportional -to the pulse rate of said first train of output pulses; and second pump means responsive to said second train of output pulses to pump a second fluid at a rate proportional to the pulse rate of said second train of output pulses.

7. The control circuit of claim 6 wherein said summing circuit logically ORs the output pulses from each said rate multiplier to produce said first intermediate pulse train.

8. The control circuit of claim 6 wherein said difference means comprises:
an inverter responsive to said clock pulses to produce inverted clock pulses;
a NAND gate responsive to the output pulses from each said rate multiplier and to said inverse clock pulses to produce an inverse second intermediate pulse string; and an inverter responsive to said inverse second intermidate pulse string to produce said second intermediate pulse string.

9. The control circuit of claim 6 wherein said first and said second spectral purifying means each comprise a pulse divider circuit for dividing the pulse train input thereto by N.

10. A pulse generator for producing two pulse trains A and B comprising, in combination:
a clock pulse generator for producing clock pulses at a rate QF where Q is a number and F is a pulse rate;

P selector means for a number N where P corresponds to the number of digits in the number N where N1 is the most significant digit and Np is the least significant digit;
P pulse rate changing circuits coupled in cascade where each said pulse rate changing circuit is coupled to said clock pulse generator and to one said selector means, each successive pulse rate changing circuit producing Nq pulses for every 10q clock pulses where q corresponds to the digit significance of the number N where q=1 for the most significant digit and q=P for the least significant digit;
means for summing the pulses produced at each said pulse rate changing circuit to produce a first output pulse train wherein the number of pulses produced whereby equals N for every 10P clock pulses;
difference means responsive to said clock pulse generator and each said pulse rate changing circuit to produce a second output pulse train with (10P - N) pulses for every 10P clock pulses;
first division means to divide said first output pulse train by Q to produce pulse train A with an output frequency fA
equal to F x ? ; and second division means to divide said second output pulse train by Q to produce pulse train B with an output frequency fB
equal to F(1 - ?).

11. The pulse generator of claim 10 wherein said clock pulse generator includes means to vary the rate of pulses produced thereby.

12. The pulse generator of claim 10 wherein said summing means comprises a circuit to produce a pulse for each pulse produced by any said pulse rate changing circuit.

13. The pulse generator of claim 10 wherein said difference means includes:

an inverter responsive to said clock pulse generator to produce inverted clock pulses;
a NAND gate responsive to said invertered clock pulses and to said pulses from each said pulse rate changing circuit for producing a pulse whenever a pulse is not produced at any pulse rate changing circuit at the time of a pulse from said clock generator.

14. The pulse generator of claim 10 wherein said difference means includes a circuit to produce a pulse at the time of a clock pulse if no pulse is produced at that time by any said pulse rate changing circuit,

15. The pulse generator of claim 10 additionally including pump means responsive to pulse train A to pump a fluid at a rate proportional to the frequency fA of pulses in pulse train A.

16. The pulse generator of claim 10 additionally including:
pump means responsive to pulse train B to pump a fluid at a rate proportional to the frequency fB of pulses in pulse train B.

17. The generator of claim 10 additionally including first pump means responsive to pulse train A to pump a first fluid at a rate proportional to the frequency fA of pulses in pulse train A; and second pump means responsive to pulse train B to pump a second fluid at a rate proportional to the frequency fB of pulse train B.

18. The pulse generator of claim 17 wherein said clock pulse generator includes means to vary the rate of pulses produced thereby to adjust the total flow rate of said first and said second fluid.

19. The pulse generator of claim 10 wherein said P selector means includes means responsive dynamically to an external condition to vary the number N in response to changes in said external condition.

20. The pulse generator of claim 1 wherein said plurality of selector means includes means responsive to changes in at least one external condition to dynamically change the decimal digit signal produced thereby.

21. The control circuit of claim 6 wherein said selector means includes means responsive to an external condition to dynamically produce signals representative of that changing condition which comprises said signals representative of a plurality of decimal digits.

22. A pulse generator for producing two pulse trains suitable for controlling the operation of two pumps so that the total flow rate of both pumps remains a constant while the rate of one pump is selectable, the generator comprising, in combination:
a source of clock pulses with one clock pulse occurring per clock cycle;
a plurality of selector means each selectively providing an unique signal representative of a decimal digit correlated to a first pulse rate;
a plurality of first decade rate multipliers each coupled to said source of clock pulses and to one selector means to receive unique signals therefrom, said first decade rate multipliers being connected in cascade so that the first decade rate multiplier is operative during each clock cycle and capable of producing an output pulse during nine out of every ten clock cycles, each successive first decade rate multiplier is operative during only the one clock cycle that the previous first decade rate multiplier cannot produce an output pulse, each said first decade rate multiplier being capable of producing X pulses at its output for each ten clock cycles that it is operative where X

corresponds to the setting of the selector means coupled thereto;

summing means responsive to the output pulses from each said first decade rate multiplier to produce a pulse in a first intermediate pulse train for each output pulse from each first decade rate multiplier;
difference means responsive to each said clock pulse and said output pulses from each first decade rate multiplier to produce a second intermediate pulse train having a pulse during each clock cycle occurring in the absence of a pulse from any said first decade rate multiplier;
at least one second decade rate multiplier coupled to first intermediate pulse train and to a selector means for each said second decade rate multiplier to receive unique signals therefrom, said second decade rate multipliers producing a third intermediate pulse train having Y pulses for each 10p pulses in the first intermediate pulse train where Y corresponds to the setting of the selector means coupled to said second decade rate multipliers and p corresponds to the number of said second decade rate multi-pliers; and at least one third decade rate multiplier, each coupled to said second intermediate pulse train and to a selector means to receive unique signals therefrom, said third decade rate multi-pliers producing a fourth intermediate pulse train having Z
pulses for every 10q pulses in said second intermediate pulse train where Z corresponds to the setting of the selector means coupled to said third decade rate multiplier and where q equals the number of third rate multipliers.

23. The pulse generator of claim 22 additionally including a first pulse counter responsive to said third intermediate pulse train and a second pulse counter responsive to said fourth intermediate pulse train, each said pulse counter producing one pulse at its output for each N pulses input thereto where N is a whole decimal number.

24. The pulse generator of claim 23 additionally including a first pump means responsive to said first pulse counter and a second pump means responsive to said second pulse counter, each said pump means being operative to pump a fluid at a flow rate related to the rate of pulses received from the pulse counter coupled thereto.

25. The pulse generator of claim 22 wherein said source of clock pulses is adjustable to produce clock pulses at an adjustable rate.

26. The control circuit of claim 6 additionally including a second selector means to produce a unique signal for each digit in a second number Y having q digits therein correlated to adjust-ment of the flow rate of said first pump means;
a second plurality of decade rate multipliers coupled to said summing means and to said second selector means to produce modified first intermediate pulse train having Y pulses therein for every 10q pulses input thereto, said modified first intermediate pulse train being coupled to said first spectral purifying means in place of said first intermediate pulse train.

27. The control circuit of claim 6 additionally including a further selector means to produce a unique signal for each digit in a number Z having q digits therein correlated to adjustment of the rate of flow of said second pump means; and a further plurality of decade rate multipliers coupled to said difference means and to said further selector means to produce a modified second intermediate pulse train having Z pulses therein for every 10q pulses input thereto, said modified second inter-mediate pulse train being coupled to said second spectral purifying means in place of said second intermediate pulse train.

28. The control circuit of claim 26 additionally including a further selector means to produce a unique signal for each digit in a number Z having q digits therein correlated to adjust-ment of the rate of flow of said second pump means; and a further plurality of decade rate multipliers coupled to said difference means and to said further selector means to produce a modified second intermediate pulse train having Z
pulses therein for every 10q pulses input thereto, said modified second intermediate pulse train being coupled to said second spectral purifying means in place of said intermediate pulse train.

29. The pulse generator of claim 10 additionally including an adjustable pulse division means for selectively producing from said first output pulse train a modified first output pulse train having no more than N pulses every 10p clock pulses, said modified first output pulse train being coupled to said first division means in place of said first output pulse train.

30. The pulse generator of claim 10 additionally including an adjustable pulse division means for selectively producing from said second output pulse train a modified second output pulse train having no more than (10p - N) pulses every 10p clock pulses, said modified second output pulse train being coupled to said second division means in place of said second division means in place of said second output pulse train.